Department of

Electrical Engineering

Digital System Design (ESE-412)

Handout#02Verilog
Operators
Instructor: Engr Irsa Jan

Lab Learning Objectives:

After completing this session, student should be able to:

• use Verilog HDL operators with ease.

Note: Submit the lab report (solved activities and exercises) before the next lab.
Lab Hardware and Software Required:

1. Desktop/Laptop Computer with internet connection.

Background Theory:
Every computer language has a set of predefined operators to perform arithmetic and
logical operations. In this lab, you will explore numerous operators available in Verilog
HDL. These operators are listed in table #1.

Table 1: Verilog Operators

Lab Activity:
You are required to make a hardware design that uses pre-defined operators in Verilog
HDL. To achieve this goal, you will make a module that takes some inputs, uses some of
the available operators (listed in table#1), and produces an output. Later, write a
testbench program to analyse the behaviour of your hardware design against the input
test vectors. The usage of all the operators is explained in chapter#3 of the textbook.
Please use syntaxes from your textbook for this activity.
Exercise:

1. Explain the working of the four shift operators through a Verilog HDL design. You
may use 2 places for shifting.

2. Make a 2-bits max comparator HDL design using ‘?’ operator. You may take three
2-bit inputs (a, b, c), and a 2-bit output should be a max number of all the three
inputs.

Note: You also need to write a testbench code for the above exercises. Please provide your explanation
with supporting waveforms obtained from your design.