Lab Manual of ‘Digital Design’

EXPERIMENT 3 Date Perform: ________________

Designing half adder, full adder, half subtractor and full subtractor in VHDL

Objectives:
 To learn how to write VHDL code for given logic
 To simulate given system in XILINX
 To verify the function of implemented logic by writing testbench

Equipment Required:
 Computer with XILINX ISE tool

Background:

This lab focuses on the implementation of basic arithmetic operations including half adder, full
adder, half subtractor, and full subtractor. After implementing the given system in Xilinx,
verification will be done by writing useful test benches. Before starting the implementation in Xilinx
ISE, let’s quickly revise the given operations.

HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘S’ and
other from the carry ‘c’ into the higher adder position. Sum can be computed by X-OR gate while
carry is a simple AND operation between the circuit inputs.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three
inputs and two outputs. A full adder is useful to add three bits at a time, but a half adder cannot do
so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input and
two outputs. The outputs are difference and borrow. The difference can be applied using X-OR Gate,
borrow output can be implemented using an AND Gate and an inverter.

FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the logic
circuit should have three inputs and two outputs. The two half subtractor put together gives a full
subtractor. The first half subtractor will be C and A B. The output will be difference output of full
subtractor. The expression AB assembles the borrow output of the half subtractor and the second
term is the inverted difference output of first X-OR.

Starting the ISE Software

To start ISE, double-click the desktop icon, or start Project Navigator from the
Start menu. Figure 1 shows the snapshot of a Xilinx project navigator interface.

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Lab Manual of ‘Digital Design’

Figure 3.1

Design Entry in VHDL

Creating a New Project
Create a new ISE project that will target the FPGA device on the Spartan 3E board.
To create a new project, follow these steps:

1. Select File > New Project, The New Project Wizard appears.
2. Type Lab3 in the Project Name field (Figure 3.2).
3. Enter or browse to a location (directory path) for the new project. A Lab3 subdirectory is
created automatically.

Figure 3.2

NOTE: all the design paths should be pointing to the designated LAB folder that you are using
for rest of your projects.

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 Lab Manual of ‘Digital Design’

4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page. (Figure 3.3)

Figure 3.3

6. Fill in the properties in the table as shown below:

 Product Category: All
 Family: Spartan3E
 Device: XC3S500E
 Package: FG320
 Speed Grade: -4
 Top-Level Module Type: HDL
 Synthesis Tool: XST (VHDL/Verilog)
 Simulator: ISE Simulator (VHDL/Verilog)
 Preferred Language: VHDL
 Leave the default values in the remaining fields. Click Next to move the project summary
page.

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 Lab Manual of ‘Digital Design’

 Then click Finish on project summary page. (Figure 3.4)

Figure 3.4

Creating and Adding a New VHDL Source File to Project

Create a Verilog source file for the project as follows:
7. Click the New Source button in the Project tab in file menu bar.
8. Select VHDL Module as the source type.
9. Type in the file name.
10. Verify that the Add to project checkbox is selected.
11. Click Next to move to Define Module page.
12. A window will appear with VHDL basic code written. Complete the architecture as required
in task and save it.

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 Lab Manual of ‘Digital Design’

TASKS:

Exercise 1

1. Write Boolean expression and truth table for the half adder circuit. Implement your circuit in
VHDL. Synthesize the code and check the RTL Schematic generated by the compiler. Paste
its screenshot in the lab submission file.
2. View the technology schematic and paste the screenshot in your report.
3. Compare your Boolean expression with the one observed in technology schematic
4. Create a test bench and simulate your design. Paste a screenshot of the test-bench in your
report. Simulate your circuit by setting AB to “01”, “10”, “11, “00”.

Exercise 2

1. Write Boolean expression and truth table for the full adder circuit. Implement your circuit in
VHDL. Synthesize the code and check the RTL Schematic generated by the compiler. Paste
its screenshot in the lab submission file.
2. View the technology schematic and paste the screenshot in your report.
3. Compare your Boolean expression with the one observed in technology schematic
4. Create a test bench and simulate your design. Paste a screenshot of the test-bench in your
report. Simulate your circuit by setting ABC to “101”, “110”, “011, “111”.

Exercise 3

1. Write Boolean expression and truth table for the half subtractor circuit. Implement your
circuit in VHDL. Synthesize the code and check the RTL Schematic generated by the
compiler. Paste its screenshot in the lab submission file.
2. View the technology schematic and paste the screenshot in your report.
3. Compare your Boolean expression with the one observed in technology schematic
4. Create a test bench and simulate your design. Paste a screenshot of the test-bench in your
report. Simulate your circuit by setting AB to “01”, “10”, “11, “00”.

Exercise 4

1. Write Boolean expression and truth table for the full subtractor circuit. Implement your
circuit in VHDL. Synthesize the code and check the RTL Schematic generated by the
compiler. Paste its screenshot in the lab submission file.
2. View the technology schematic and paste the screenshot in your report.
3. Compare your Boolean expression with the one observed in technology schematic
4. Create a test bench and simulate your design. Paste a screenshot of the test-bench in your
report. Simulate your circuit by setting AB to “011”, “110”, “111, “010”.

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 Lab Manual of ‘Digital Design’

EL320 DIGITAL DESIGN LAB

The focus of this lab is to cover principles of digital system design. Also, to combine classical
design methodologies to demonstrate successful designing, implementation and debugging of
digital systems using computer aided design tools.
CLO Statement ↓ Exemplary Proficient Developing Beginning Novice
Score → (5) (4) (3) (2) (1)

Create
sequential as Understand
Attempts Attempts lab
1 well as Attempts all the given
partial lab tasks with
combinational lab tasks with concept but No attempt
tasks with incorrect
circuits using correct output unable to
correct output output
HDL models. apply it

Behaves
responsibly Completes
3 and Completes
the lab task
individually Completes the lab task Poorly
with help of Does not
performs the the lab task with minor attempts lab
instructor and work
lab. on his own help of tasks
students
instructor
around

CLO MARKS OBTAINED

1
3

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