SVCE TIRUPATI

COURSE MATERIAL

DIGITAL ELECTRONICS &

SUBJECT MICROPROCESSOR (19A05301)

UNIT 2

COURSE B.Tech

SEMESTER III

DEPARTMENT COMPUTER SCIENCE & ENGINEERING

PREPARED BY Dr.G.CHANDRAIAH
(Faculty Name/s) Assoc.Professor

VERSION V-5

PREPARED /REVISED DATE 08.09.2022

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TABLE OF CONTENTS – UNIT 3

SNO CONTENTS PAGE
1 COURSE OBJECTIVES 1
2 PREREQUISITES 1
3 SYLLABUS 1
4 COURSE OUTCOMES 1
5 CO - PO/PSO MAPPING 1
6 LESSON PLAN 2
7 ACTIVITY BASED LEARNING 2
8 LECTURE NOTES 2
2.1 INTRODUCTION COMBINATIONAL CIRCUITS 2
2.2 ANALYSIS OF COMBINATIONAL CIRCUITS,DESIGN PROCEDURE 3
2.3 BINARY ADDER ,HALF ADDER ,FULL ADDER 3
2.4 BINARY SUBTRACTOR,HALF SUBTRACTOR,FULL SUBTRACTOR 6
2.5 DECODERS 8
2.6 ENCODERS 14
2.7 MULTIPLEXERS 17
2.8 DEMULTIPLEXERS 23
9 PRACTICE QUIZ 28
10 ASSIGNMENTS 29
11 PART A QUESTIONS & ANSWERS (2 MARKS QUESTIONS) 29
12 PART B QUESTIONS 31
13 SUPPORTIVE ONLINE CERTIFICATION COURSES 31
14 REAL TIME APPLICATIONS 31
15 CONTENTS BEYOND THE SYLLABUS 31
16 PRESCRIBED TEXT BOOKS & REFERENCE BOOKS 32
17 MINI PROJECT SUGGESTION 32

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1. COURSE OBJECTIVES
The objectives of this course is to
1. Introduce the classification of digital circuits and combinational circuits.
2. Outline knowledge on analysis of combinational circuits and design procedure
of combinational circuits.
3. Apply knowledge of K-maps to attain simplified Boolean function.
4. Acquainting with classical hardware design of combinational circuits.
5. Knowledge and hands-on experience that will enable them to work in a digital
system design.

2. PREREQUISITES
Students should have knowledge on
1. Basic Electronics
2. Basic Mathematics

3. SYLLABUS
UNIT III

Combination Logic: Combinational Circuits, Binary Adder-Subtractor, Decoders,

Encoders, Multiplexers and Demultiplexers.

4. COURSE OUTCOMES
1. Apply Boolean algebra for describing combinational digital circuits.
2. Select fundamental combinational circuits.
3. Analyze standard combinational circuits such as adders, subtractors, decoders,
encoders etc.
4. Design various combinational logic circuits.
5. Implement Boolean function with decoders and multiplexer.

5. Co-PO / PSO Mapping

DLD PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 P10 PO11 PO12 PSO1 PSO2

CO1 3 3 2 2

CO2 3 3 2 2

CO3 3 3 2 2

CO4 3 3 2 2

CO5 3 3 2 2

6. LESSON PLAN
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LECTURE WEEK TOPICS TO BE COVERED REFERENCES

Combinational Circuits, Analysis of Combinational Circuits, Design
1 T1
Procedure
2 Binary Adder, HalfAdder, Full Adder T1, R1
1
3 Binary Subtractor ,HalfSubtractor, FullSubtractor T1, R1

4 4-bit Binary Adder – Subtractor, Decimal Adder T1, R1

5 Decoders,2*4 decoder,3* 8 decoder,4*16 decoder T1, R2

6 4* 16 Decoders using 3* 8 decoder T1, R1

2
7 Encoder ,4*2 encoder,8*3 encoder,16* 4 encoder T1, R1

8 Multiplexers and Demultiplexers T1, R1

9 Discussion of objective type questions & Short answer questions T1, R1

3
10 Discussion of Previous year university questions in question papers T1, R1

7. ACTIVITY BASED LEARNING

1. Through project based teaching learning to apply the theoretical concepts.
2. Through worksheets is used to facilitate project based learning by strengthening
the fundamental concepts during classroom teaching.
8. LECTURE NOTES
2.1 INTRODUCTION
Combinational circuit is a circuit in which we combine the different gates in the
circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of
the characteristics of combinational circuits are following −
• The output of combinational circuit at any instant of time, depends only on
the levels present at input terminals.
• The combinational circuit do not use any memory. The previous state of input
does not have any effect on the present state of the circuit.
• A combinational circuit can have an n number of inputs and m number of
outputs.
Block diagram

Fig.2.1.The block diagram of a combinational circuit

2.2 ANALYSIS OF COMBINATIONAL CIRCUITS, DESIGN PROCEDURE

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2.2.1 DESIGN PROCEDURE
The design procedure for combinational logic circuits starts with the
problem specification and comprises the following steps:
1. Determine required number of inputs and outputs from the
specifications.
2. Derive the truth table for each of the outputs based on their relationships
to the input.
3. Simplify the boolean expression for each output. Use Karnaugh Maps or
Boolean algebra.
4. Draw a logic diagram that represents the simplified Boolean expression.
Verify the design by analysing or simulating the circuit.
2.2.2. Different types of Combinational Circuit
There are three main types of combinational logic circuits.
1. Arithmetic and logical combinational circuits – Adders,
Subtractors, Multipliers, Comparators.
2. Data handling combinational circuits – Multiplexers,
Demultiplexers, priority encoders, decoders.
3. Code converting combinational circuits – Binary to Gray, Gray to
Binary, Binary to Excess 3, seven-segment, etc.

2.3. BINARY ADDER

2.3.1 HALF ADDER
Half adder is a combinational logic circuit with two inputs and two outputs. The
half adder circuit is designed to add two single bit binary number A and B. It is
the basic building block for addition of two single bit numbers. This circuit has
two outputs carry and sum.
Block diagram

Fig.2.2. Half Adder

Truth Table

Table.2.1. Half Adder Truth Table

Circuit Diagram
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Fig.2.3.Logic diagram of a Half Adder

2.3.2 FULL ADDER
Full adder is developed to overcome the drawback of Half Adder circuit. It can
add two one-bit numbers A and B, and carry cin. The full adder is a three input
and two output combinational circuit. The same two single bit data
inputs A and B as plus an additional Carry-in (C-in) input to receive the carry
from a previous stage as shown below.

Block diagram

Fig.2.4. Full Adder

Then the full adder is a logical circuit that performs an
addition operation on three binary digits and just like
the half adder, it also generates a carry out to the next
addition column. Then a Carry-in is a possible carry
from a less significant digit, while a Carry-out represents
a carry to a more significant digit.

Truth Table

Table.2.2. Full adder Truth Table

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Circuit Diagram

Fig. 2.5. Logic diagram of Full Adder

2.3.3.N-Bit Parallel Adder

The Full Adder is capable of adding only two single digit binary number along
with a carry input. But in practical we need to add binary numbers which are
much longer than just one bit. To add two n-bit binary numbers we need to use
the n-bit parallel adder. It uses a number of full adders in cascade. The carry
output of the previous full adder is connected to carry input of the next full
adder.
2.3.4.4-Bit Parallel Adder
In the block diagram, A0 and B0 represent the LSB of the four bit words A and B.
Hence Full Adder-0 is the lowest stage. Hence its Cin has been permanently
made 0. The rest of the connections are exactly same as those of n-bit parallel
adder is shown in fig. The four bit parallel adder is a very common logic circuit.

Block diagram

Fig. 2.6. Logic diagram of a 4-bit binary Parallel Adder

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2.4. BINARY SUBTRACTOR

3.4.1. Half-Subtractors
Half-subtractor is a combination circuit with two inputs and two outputs
(difference and borrow). It produces the difference between the two binary bits
at the input and also produces an output (Borrow) to indicate if a 1 has been
borrowed. In the subtraction (A-B), A is called as Minuend bit and B is called as
Subtrahend bit.
Truth Table

Table 2.3. Truthtable of half subtractor

Circuit Diagram

Fig.2.7. Logic diagram of Half subtractor

2.4.2. Full-Subtractor
The disadvantage of a half subtractor is overcome by full subtractor. The full
subtractor is a combinational circuit with three inputs A,B,C and two output D
and C'. A is the 'minuend', B is 'subtrahend', C is the 'borrow' produced by the
previous stage, D is the difference output and C' is the borrow output.
Truth Table

Table 2.4. Full Subtractor Truthtable

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Circuit Diagram

Fig. 2.8. Logic diagram of a Full subtractor

2.4.3. N-Bit Parallel Subtractor
The subtraction can be carried out by taking the 1's or 2's complement of the
number to be subtracted. For example we can perform the subtraction (A-B) by
adding either 1's or 2's complement of B to A. That means we can use a binary
adder to perform the binary subtraction.
2.4.3.1.4 Bit Parallel Subtractor
The number to be subtracted (B) is first passed through inverters to obtain its 1's
complement. The 4-bit adder then adds A and 2's complement of B to produce
the subtraction
Block Diagram

Fig. 2.9. Logic diagram of a 4-bit parallel subtractor

S3 S2 S1 S0 represents the result of binary subtraction (A-B) and carry output Cout
represents the polarity of the result. If A > B then Cout = 0 and the result of binary
form (A-B) then Cout = 1 and the result is in the 2's complement form

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2 .5. DECODER
A decoder is a combinational circuit. It has n input and to a maximum m = 2n
outputs. Decoder is identical to a demultiplexer without any data input. It
performs operations which are exactly opposite to those of an encoder.
Block diagram

Fig.2.10. General block diagram of a decoder

Examples of Decoders are following.
• Code converters
• BCD to seven segment decoders
• Nixie tube decoders
• Relay actuator
2.5.1. 2 to 4 Line Decoder
The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two
inputs where D0 through D4 are the four outputs. Truth table explains the
operations of a decoder. It shows that each output is 1 for only a specific
combination of inputs.
Block diagram

Fig.2.11. Block diagram of 2 line to 4-line decoder

Truth Table

Table.2.5. Truth table of 2-to-4 decoder

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Logic Circuit

Fig.2.12. Logic diagram of 2- to -4 decoder

ii. 3 to 8 Decoder.
• A 3 to 8 decoder has three inputs (A,B,C) and eight outputs (DO to D7).
• Based on the 3 inputs one of the eight outputs is selected.
• The truth table for 3 to 8 decoder is shown in table (1).
• From the truth table, it is seen that only one of eight outputs (DO to D7) is
selected based on three select inputs.
• From the truth table, the logic expressions for outputs can be written as
follows:
Truth table of 3 to 8 decoder.

Inputs Outputs
A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Table.2.6. Truth table of 3 to 8 decoder.

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• Using the above expressions, the circuit of a 3 to 8 decoder can be implemented
using three NOT gates and eight 3-input AND gates as shown in fig
• The three inputs A, B and C are decoded into eight outputs, each output
representing one of the midterms of the 3-input variables.
• The three inverters provide the complement of the inputs and each one of the
wight AND gates generates one of the midterms.
• This decoder can be used for decoding any 3-bit code to provide eight outputs,
corresponding to eight different combinations of the input code.
• UpThis is also called a 1 of 8 decoder, since only one of eight output lines is HIGH
for a particular input combination.

Fig.2.13. Logic diagram of 3 to 8 decoder.

• It is also called a binary-to-octal decoder, since the inputs represent 3-bit

binary numbers and the outputs represent the eight digits in the octal
number system.
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2.5.3. Implementation of Full adder using decoder
In this topic we will try to discuss about Combinational Logic Implementation full
adder circuit with a decoder and two OR Gates.
To do this at first we need to review the truth table of Full Adder circuit.
Truth table of Full Adder Circuit

Table.2.7. Truth Table of a full adder

From the truth table we have been found that

S(a,b,cin)=sum(1,2,4,7).,Co(a,b,c)=sum(3,5,6,7)
As there are three inputs and eight min-terms, so have to use 3 to 8 line
decorder. The generates the eight min-terms for a, b, c.
The OR Gate for output S forms the sum of min-terms 1, 2, 4 and 7. The OR Gate
output C forms the sum of min-terms 3, 5, 6 and 7.
Circuit Diagram

Fig.2.14. Logic diagram of a full adder using a decoder

A function with a long list of min-terms requires an OR Gate with a large number
of inputs. A function F having a list of K min-terms can be expressed in its
complemented form F’ with 2^n-K min-terms. If the number of min-terms in a
function is greater than 2^n/2, then F’ can be expressed with fewer min-terms
than required for F. In such a case, it is suitable to use a NOR Gate to sum the
min-terms of F’. The output of the NOR Gate will generate the normal output F.
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The decoder method can be used to implement any combinational circuit. It is
necessary to implementing with comparing to all other possible
implementations to determine the solution.

2.5.4. Implementation of Higher-order Decoders

Now, let us implement the following two higher-order decoders using lower
order decoders.
• 3 to 8 decoder
• 4 to 16 decoder

2.5.4.1. 3 to 8 Decoder
In this section, let us implement 3 to 8 decoder using 2 to 4 decoders. We
Know that 2 to 4 Decoder has two inputs, A1 & A0 and four outputs, Y3 to Y0.
Whereas, 3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to
Y0.
We can find the number of lower order decoders required for implementing
higher order decoder using the following formula.
Required number of lower order decoders=m2/m1
Where,m1 is the number of outputs of lower order decoder.
m2 is the number of outputs of higher order decoder.
Here, m1= 4 and m2 = 8. Substitute, these two values in the above formula.
Required number of 2to4 decoders=8/4=2.
Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder.
The block diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the
following figure.

Fig.2.15. Connecting two 2-to - 4 decoders to obtain 3-to- 8 decoder

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The parallel inputs A1 & A0 are applied to each 2 to 4 decoder. The
complement of input A2 is connected to Enable, E of lower 2 to 4 decoder in
order to get the outputs, Y3 to Y0. These are the lower four min terms. The input,
A2 is directly connected to Enable, E of upper 2 to 4 decoder in order to get the
outputs, Y7 to Y4. These are the higher four min terms.

2.5.4.2 4 to 16 Decoder
In this section, let us implement 4 to 16 decoder using 3 to 8 decoders. We know
that 3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0.
Whereas, 4 to 16 Decoder has four inputs A3, A2, A1 & A0 and sixteen outputs,
Y15 to Y0
We know the following formula for finding the number of lower order decoders
required.
Required number of lower order decoder =m2/m1
Substitute, m1= 8 and m2= 16 in the above formula.
Required number of 3to8 decoders=16/8=2
Therefore, we require two 3 to 8 decoders for implementing one 4 to 16
decoder. The block diagram of 4 to 16 decoder using 3 to 8 decoders is shown
in the following figure.

Fig.2.16. Connecting two 3- to- 8 decoders to obtain a 4- to -16 decoder.

Three parallel inputs A2, A1 & A0 are applied to each 3 to 8 decoder. The

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complement of input, A3 is connected to Enable, E of lower 3 to 8 decoder in
order to get the outputs, Y7 to Y0. These are the lower eight min terms. The input,
A3 is directly connected to Enable, E of upper 3 to 8 decoder in order to get the
outputs, Y15 to Y8. These are the higher eight min terms.

2.6. Encoder
Encoder is a combinational circuit which is designed to perform the inverse
operation of the decoder. An encoder has n number of input lines and m
number of output lines. An encoder produces an m bit binary code
corresponding to the digital input number. The encoder accepts an n input
digital word and converts it into an m bit another digital word.
Block diagram

Fig.2.17. Block diagram of Encoder

Examples of Encoders are following.

• Priority encoders
• Decimal to BCD encoder
• Octal to binary encoder
• Hexadecimal to binary encoder

2.6.1. 4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0.
The block diagram of 4 to 2 Encoder is shown in the following figure.

Fig.2.18. Block diagram of 4 -to- 2 encoder

At any time, only one of these 4 inputs can be ‘1’ in order to get the respective
binary code at the output. The Truth table of 4 to 2 encoder is shown below.

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Truth table

Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Table.2.8. Truth table of 4-to -2 encoder

From Truth table, we can write the Boolean functions for each output as
A1=Y3+Y2

A0=Y3+Y1

We can implement the above two Boolean functions by using two input OR
gates.
The circuit diagram of 4 to 2 encoder is shown in the following figure.

Fig.2.19. Logic diagram of a 4-to-2 encoder

The above circuit diagram contains two OR gates. These OR gates encode the
four inputs with two bits.

2.6.2 Octal to Binary Encoder

Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0.
Octal to binary encoder is nothing but 8 to 3 encoder. The block diagram of
octal to binary Encoder is shown in the following figure.
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Fig.2.20 Octal to binary encoder

At any time, only one of these eight inputs can be ‘1’ in order to get the
respective binary code. The Truth table of octal to binary encoder is shown
below.

Inputs Outputs
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Table.2.9. Truth table of an Octal to binary encoder

From Truth table, we can write the Boolean functions for each output as
A2=Y7+Y6+Y5+Y4
A1=Y7+Y6+Y3+Y2
A0=Y7+Y5+Y3+Y1
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We can implement the above Boolean functions by using four input OR gates.
The circuit diagram of octal to binary encoder is shown in the following figure.

Fig.2.21. Logic diagram of a octal to binary encoder

The above circuit diagram contains three 4-input OR gates. These OR gates
encode the eight inputs with three bits.
Drawbacks of Encoder
Following are the drawbacks of normal encoder.
• There is an ambiguity, when all outputs of encoder are equal to zero. Because,
it could be the code corresponding to the inputs, when only least significant
input is one or when all inputs are zero.
• If more than one input is active High, then the encoder produces an output,
which may not be the correct code. For example, if both Y3 and Y6 are ‘1’, then
the encoder produces 111 at the output. This is neither equivalent code
corresponding to Y3, when it is ‘1’ nor the equivalent code corresponding to Y6,
when it is ‘1’.
So, to overcome these difficulties, we should assign priorities to each input of
encoder. Then, the output of encoder will be the binary code corresponding to
the active High inputs, which has higher priority. This encoder is called as priority
encoder.

2.7. Multiplexers
Multiplexer is a special type of combinational circuit. There are n-data inputs,
one output and m select inputs with 2m = n. It is a digital circuit which selects
one of the n data inputs and routes it to the output. The selection of one of the
n inputs is done by the selected inputs. Depending on the digital code applied
at the selected inputs, one out of n data sources is selected and transmitted to
the single output Y. E is called the strobe or enable input which is useful for the

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cascading. It is generally an active low terminal that means it will perform the
required operation when it is low.
Block diagram

Fig.2.22. Block diagram of MUltiplexer

Multiplexers come in multiple variations

• 2 : 1 multiplexer
• 4 : 1 multiplexer
• 16 : 1 multiplexer
• 32 : 1 multiplexer

2.7.1. 2 :1 multiplixer
Block Diagram

Fig.2.23. Block diagram of 2:1 multiplexer

Truth Table

Table.2.10. Truth table of 2:1 multiplexer

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2.7.2 4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and
one output Y. The block diagram of 4x1 Multiplexer is shown in the following
figure.
One of these 4 inputs will be connected to the output based on the
combination of inputs present at these two selection lines. Truth table of 4x1
Multiplexer is shown below.
Truth table

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

Table.2.11. Truth table of 4 * 1 multiplexer

From Truth table, we can directly write the Boolean function for output, Y as

Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

We can implement this Boolean function using Inverters, AND gates & OR gate.

The circuit diagram of 4x1 multiplexer is shown in the following figure.

Fig.2.24. Logic diagram of 4*1 multiplexer

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We can easily understand the operation of the above circuit. Similarly, you can
implement 8x1 Multiplexer and 16x1 multiplexer by following the same
procedure.

2.7.3. Implementation of Higher-order Multiplexers.

Now, let us implement the following two higher-order Multiplexers using lower-
order Multiplexers.

• 8x1 Multiplexer
• 16x1 Multiplexer

2.7.3.1. 8x1 Multiplexer

In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1
Multiplexer. We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines
and one output. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection lines
and one output.

So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs.
Since, each 4x1 Multiplexer produces one output, we require a 2x1Multiplexer in
second stage by considering the outputs of first stage as inputs and to produce
the final output.

Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 &
s0 and one output Y. The Truth table of 8x1 Multiplexer is shown below.

Truth table

Selection Inputs Output

S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

Table.2.12. Truth table of 8*1 multiplexer.

We can implement 8x1 Multiplexer using lower order Multiplexers easily by

considering the above Truth table. The block diagram of 8x1 Multiplexer is
shown in the following figure.

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Fig.2.25. 8*1 multiplexer using two 4*1 multiplexer and one 2*1 multiplexer

The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data
inputs of upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1
Multiplexer are I3 to I0. Therefore, each 4x1 Multiplexer produces an output
based on the values of selection lines, s1 & s0.

The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer
that is present in second stage. The other selection line, s2 is applied to 2x1
Multiplexer.

• If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3 to
I0 based on the values of selection lines s1 & s0.

• If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I 7 to
I4 based on the values of selection lines s1 & s0.

Therefore, the overall combination of two 4x1 Multiplexers and one 2x1
Multiplexer performs as one 8x1 Multiplexer.

2.7.3.2 16x1 Multiplexer

In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1
Multiplexer. We know that 8x1 Multiplexer has 8 data inputs, 3 selection lines
and one output. Whereas, 16x1 Multiplexer has 16 data inputs, 4 selection lines
and one output.

So, we require two 8x1 Multiplexers in first stage in order to get the 16 data
inputs. Since, each 8x1 Multiplexer produces one output, we require a 2x1
Multiplexer in second stage by considering the outputs of first stage as inputs
and to produce the final output.

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Let the 16x1 Multiplexer has sixteen data inputs I15 to I0, four selection lines s3 to
s0 and one output Y. The Truth table of 16x1 Multiplexer is shown below.

Truth table

Selection Inputs Output

S3 S2 S1 S0 Y
0 0 0 0 I0
0 0 0 1 I1
0 0 1 0 I2
0 0 1 1 I3
0 1 0 0 I4
0 1 0 1 I5
0 1 1 0 I6
0 1 1 1 I7
1 0 0 0 I8
1 0 0 1 I9
1 0 1 0 I10
1 0 1 1 I11
1 1 0 0 I12
1 1 0 1 I13
1 1 1 0 I14
1 1 1 1 I15

Table.2.13. Truth table of 16*1 multiplexer.

We can implement 16x1 Multiplexer using lower order Multiplexers easily by

considering the above Truth table.

The block diagram of 16x1 Multiplexer is shown in the following figure.

Fig.2.26. 16*1 multiplexer using two 8*1 multiplexer and 2*1 multiplexer

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The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The data
inputs of upper 8x1 Multiplexer are I15 to I8 and the data inputs of lower 8x1
Multiplexer are I7 to I0. Therefore, each 8x1 Multiplexer produces an output
based on the values of selection lines, s2, s1 & s0.
The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer
that is present in second stage. The other selection line, s3 is applied to 2x1
Multiplexer.
• If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is 7 to
I0 based on the values of selection lines s2, s1 & s0.
• If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I15 to
I8 based on the values of selection lines s2, s1 & s0.
Therefore, the overall combination of two 8x1 Multiplexers and one 2x1
Multiplexer performs as one 16x1 Multiplexer.
2.8. Demultiplexers
A demultiplexer performs the reverse operation of a multiplexer i.e. it receives
one input and distributes it over several outputs. It has only one input, n outputs,
m select input. At a time only one output line is selected by the select lines and
the input is transmitted to the selected output line. A de-multiplexer is equivalent
to a single pole multiple way switch as shown in fig.
Demultiplexers come in multiple variations.
• 1 : 2 demultiplexer
• 1 : 4 demultiplexer
• 1 : 16 demultiplexer
• 1 : 32 demultiplexer

2.8.1. 1x4 De-Multiplexer

1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3,
Y2, Y1 &Y0. The block diagram of 1x4 De-Multiplexer is shown in the following
figure.
Block diagram

Fig.2.27. Block diagram of 1* 4 demultiplexer

Thee single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based
on the values of selection lines s1 & s0. The Truth table of 1x4 De-Multiplexer is
shown below.
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Truth table

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

Table.2.14. Truth table of 1*4 Demultiplexer.

From the above Truth table, we can directly write the Boolean functions for
each output as
Y3=s1s0I
Y2=s1s0′I
Y1=s1′s0I
Y0=s1′s0′I

We can implement these Boolean functions using Inverters & 3-input AND gates.
The circuit diagram of 1x4 De-Multiplexer is shown in the following figure.

Fig.2.28. Logic diagram of 1*4 demultiplexer

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We can easily understand the operation of the above circuit. Similarly, you can
implement 1x8 De-Multiplexer and 1x16 De-Multiplexer by following the same
procedure.

2.8.2 Implementation of Higher-order De-Multiplexers

Now, let us implement the following two higher-order De-Multiplexers using

lower-order De-Multiplexers.

• 1x8 De-Multiplexer
• 1x16 De-Multiplexer

2.8.2.1. 1x8 De-Multiplexer

In this section, let us implement 1x8 De-Multiplexer using 1x4 De-Multiplexers and
1x2 De-Multiplexer. We know that 1x4 De-Multiplexer has single input, two
selection lines and four outputs. Whereas, 1x8 De-Multiplexer has single input,
three selection lines and eight outputs.

So, we require two 1x4 De-Multiplexers in second stage in order to get the final
eight outputs. Since, the number of inputs in second stage is two, we require 1x2
DeMultiplexer in first stage so that the outputs of first stage will be the inputs of
second stage. Input of this 1x2 De-Multiplexer will be the overall input of 1x8 De-
Multiplexer.

Let the 1x8 De-Multiplexer has one input I, three selection lines s2, s1 & s0 and
outputs Y7 to Y0. The Truth table of 1x8 De-Multiplexer is shown below.

Selection Inputs Outputs

s2 s1 s0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 I

0 0 1 0 0 0 0 0 0 I 0

0 1 0 0 0 0 0 0 I 0 0

0 1 1 0 0 0 0 I 0 0 0

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1 0 0 0 0 0 I 0 0 0 0

1 0 1 0 0 I 0 0 0 0 0

1 1 0 0 I 0 0 0 0 0 0

1 1 1 I 0 0 0 0 0 0 0

Table.2.15. Truth table of 1*8 demultiplexer

We can implement 1x8 De-Multiplexer using lower order Multiplexers easily by

considering the above Truth table. The block diagram of 1x8 De-Multiplexer is
shown in the following figure.

Logic Diagram

Fig.2.29.Implementing 1* 8 demultiplexer using 1*4 demultiplexer

The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers. The
outputs of upper 1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower 1x4
De-Multiplexer are Y3 to Y0.

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The other selection line, s2 is applied to 1x2 De-Multiplexer. If s2 is zero, then one
of the four outputs of lower 1x4 De-Multiplexer will be equal to input, I based on
the values of selection lines s1 & s0. Similarly, if s2 is one, then one of the four
outputs of upper 1x4 DeMultiplexer will be equal to input, I based on the values
of selection lines s1 & s0.
2.8.2.2. 1x16 De-Multiplexer
In this section, let us implement 1x16 De-Multiplexer using 1x8 De-Multiplexers
and 1x2 De-Multiplexer. We know that 1x8 De-Multiplexer has single input, three
selection lines and eight outputs. Whereas, 1x16 De-Multiplexer has single input,
four selection lines and sixteen outputs.
So, we require two 1x8 De-Multiplexers in second stage in order to get the final
sixteen outputs. Since, the number of inputs in second stage is two, we
require 1x2 DeMultiplexer in first stage so that the outputs of first stage will be
the inputs of second stage. Input of this 1x2 De-Multiplexer will be the overall
input of 1x16 De-Multiplexer.
Let the 1x16 De-Multiplexer has one input I, four selection lines s3, s2, s1 & s0 and
outputs Y15 to Y0. The block diagram of 1x16 De-Multiplexer using lower order
Multiplexers is shown in the following figure.

Fig.2.30.Implementing 1* 16 demultiplexer using 1*8 demultiplexer

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The common selection lines s2, s1 & s0 are applied to both 1x8 De-Multiplexers.
The outputs of upper 1x8 De-Multiplexer are Y15 to Y8 and the outputs of lower
1x8 DeMultiplexer are Y7 to Y0.
The other selection line, s3 is applied to 1x2 De-Multiplexer. If s3 is zero, then one
of the eight outputs of lower 1x8 De-Multiplexer will be equal to input, I based on
the values of selection lines s2, s1 & s0. Similarly, if s3 is one, then one of the 8
outputs of upper 1x8 De-Multiplexer will be equal to input, I based on the values
of selection lines s2, s1 & s0.

9. Practice Quiz
1.A binary adder can be constructed with
a) Cascaded connection of full adders
b) parallel connection of half adders
c) Cascaded connection of Half adders
d)parallel connection of full adders

2. In a binary adder-subtractor circuit 1’s complement can be achieved with

a) NAND gates
b) NOR gates
c) Xor gates
d) 1inverters
3. A decoder with enable input can function as
a) multiplexer
b) priority encoder
c) comparator
d) demultiplexer
4. A combinational circuit that performs 3-bitaddition is called?
a) Half adder
b) Full adder
c)Half Subtractor
d) Full Subtractor
5. How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?
a) 1
b) 2
c) 4
d) 8 none
6.Which combinational circuit is renowned for selecting a single input from multiple
inputs & directing the binary information to output line?
a) Multiplexer
b) demultiplexer
c) both multiplexer and demultiplexer
d) decoder
7.In 1-to-4 demultiplexer, how many select lines are required?
a) 2
b) 3
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c) 4
d) 5
8.The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
9. A code converter is a logic circuit that _____________
a) Inverts the given input
b) Converts into decimal number
c) Converts data of one type into another type
d) Converts to octal

10.Assignments

S.No Question BL CO
1 Design a full adder and full subtractor? 4 1
Design of a combinational circuit to produce the 2’s
2 4 1
complement of a 4-bit binary number?
3 Design a decimal to BCD encoder circuit ? 4 1
4 Design a 2 line to 4 line decoder using NAND gates? 4 1
Implement the following logic function using an 8*1 MUX
5 F(A,B,C,D)=m(1,3,4,11,12,13,14,15) 3 1

6 Design a 32:1 MUX using two 16:1 muxs and one 2:1 mux? 4 1

11. Part A- Question & Answers

S.No Question& Answers BL CO

1 What are combinational circuits?
A combinational circuit consists of logic gates whose
outputs at any time are determined from the present
combination of inputs. A combinational circuit performs an 1 1
operation that can be specified logically by a set of
Boolean functions. It consists of input variables, logic gates,
and output variables.
2 Give the design procedures for the designing of a
combinational circuit.
The procedure involves the following steps, From the
specification of the circuit, determine the required number of
inputs and outputs and assign a symbol to each. Derive the 1 1
truth table that defines the required relationships between
inputs and outputs. Obtain the simplified Boolean functions for
each output as a function of the input variables. Draw the
logic diagram and verify the correctness of the design.
3 Define half adder. 4 3

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A combinational circuit that performs the addition of
two bits is called a half adder. A half adder needs two binary
inputs and two binary outputs. The input variables designate
the augend and addend bits; the output variables produce
the sum and carry
4 Define full adder?
A combinational circuit that performs the adtion of
4 3
three bits is a full adder.It consists of three inputs and two
outputs.
5 Define binary adder.
A binary adder is a digital circuit that produces the
arithmetic sum of two binary numbers. It can be constructed
4 3
with full adders constructed in cascade, with the output
carry from each full adder connected to the input carry of
the next full adder in the chain.
6 Define multiplexer?
A multiplexer is combinational circuit that selects
binary information from one of many input lines and directs it
to a single output line. The selection of a particular input line is 4 4
controlled by a set of selection lines. Normally there are 2n
input lines and n selection lines whose bit combinations
determine which input is selected.
7 Define magnitude comparator?
A magnitude comparator is a combinational circuit
that compares two numbers, A and B, and determines their
4 3
relative magnitudes. The outcome of the comparison is
specified by three binary variables that indicate whether
a>b, A = b, or A < B.
8 What are decoders?
A decoder is a combinational circuit that converts
binary information from n input lines to a maximum of 2n 2 4
unique output lines. If the n bit coded information has unused
combinations, he decoder may have fewer than 2n outputs.
9 What are encoders?
An encoder is a digital circuit that performs the inverse
operation of a decoder. An encoder has 2n and n output 2 4
lines. The output lines generate the binary code
corresponding to the input value
10. Define priority encoder?
A priority encoder is an encoder circuit that includes the
priority function. The operation of priority encoder is such that 4 4
if two or more inputs are equal to 1 at the same time, the
input having the highest priority will take precedence.

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12. Part B- Questions

S.No Question BL CO
1 What is a combinational circuit? Explain with one example. 1 1
2 Design a full adder with two halfadders and OR gate. 4 3
3 Design a 4-bitadder-subtractorcircuitand explain the operation 2 3
in detail
4 With neat diagram,explain 3 to 8 line decoder. 2 3
5 With neat diagram,explain decimal adder. 2 3
6 3 5
ImplementthefollowingBooleanfunctionusing4x1MUX.
F(a,b,c)=∑m (1,3,5,6)
7 Realize the functionF(a,b,c)=∑m (0,3,5,6,7)using 8:1 multiplexer. 3 5
8 Design 2 bit magnitude comparator and draw its logic circuit 4 3
diagram.
9 Design 32:1 Multiplexer using two 16:1 Multiplexers and one 2:1 3 4
Multiplexer.
10 Briefly explain the operation of a carry look ahead adder 3 4

13. Supportive Online Certification Courses

1. Digital Circuits and systems ByProf.S.Srinivasan,coordinated by IIT Madras– 12
weeks
2. Digital Electronics CircuitsBy Prof.GoutamSaha, conducted by IIT Kharagpur –
12 weeks.

14. Real Time Applications

S.No Application CO
1 Combinational logic circuits as arithmetic and logic circuits have 3
applications as Comparators ,Programmable logic devices,Adders &
Subtractors.
2 Combinational logic circuits as data transmission circuits have 3
applications as Parallel to serial convertors,Data routing,Serial to parallel
converters,Bit Compression,ADC and DAC,Encoders & Decoders.
3 Combinational logic circuits as code converter circuits have applications 3
as Binary to gray code conversion,Gray to Binary conversion,BCD to
Excess-3,Excess-3 to BCD,Seven segment code

15. Contents Beyond the Syllabus

1. Binary Serial Adder
Serial binary adder is a combinational logic circuit that performs the addition of
two binary numbers in serial form. Serial binary adder performs bit by bit addition.
Two shift registers are used to store the binary numbers that are to be added.
A single full adder is used to add one pair of bits at a time along with the carry.
The carry output from the full adder is applied to a D flip-flop. After that output is
used as carry for next significant bits. The sum bit from the output of the full adder
can be transferred into a third shift register.
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2. Excess-3 adder
It is a basically a binary code which is made by adding 3 with the equivalent
decimal of a binary number and again converting it into binary number. So if
we consider any binary number we have to first convert it into decimal number
then add 3 with it and then convert it into binary and we will get the excess 3
equivalent of that number.
The operation of addition can be done by very simple method we will illustrate
the operation in a simple way using steps.
1.Convert the numbers (which are to be added) into excess 3 forms by adding
0011 with each of the four bit groups them or simply increasing them by 3.
2. Now the two numbers are added using the basic laws of binary addition,
there is no exception for this method.
3. Now which of the four groups have produced a carry we have to add 0011
with them and subtract 0011 from the groups which have not produced a carry
during the addition.
4. The result which we have obtained after this operation is in Excess 3 form and
this is our desired result

16. Prescribed Text Books & Reference Books

Text Book
1. M.Morris Mano,M.D.Ciletti,” Digital Design”,5th edition.Pearson,2018
References:
1. Donald P Leach, Albert Paul Malvino, Goutam Saha, “Digital Principles and
applications”,Mc Graw Hill , 8th Edition,2015.
2. David J. Comer, “Digital Logic & State Machine Design”, Oxford University Press,
3rd Reprinted Indian Edition, 2012
3. R.D. Sudhakar Samuel, “Digital Logic Design”, Elsevier Publishers.

17. Mini Project Suggestion

1. Secret code Enabled Secure Communication using RF Technology

The project is designed to send secure message by using a secret code from a
computer keyboard connected to the transmitting unit via RF technology. The
message is retrieved at the receiver end only upon entering the secret code
used by the transmitter. Thus, complete secrecy is maintained in this
communication process. This project has a unique feature of tagging the
message with a secret code as selected by the sender. The message is then
transmitted through the RF transmitting module. At the receiver end, the signal
is received by the RF receiver module. The message is then retrieved only if the
secret code is known to the receiving personnel. In this project, the encoders
and decoders are used to transmit and receive the information. Once the
secret code is entered, then message is displayed on the receiving unit on the
LCD display.
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2. FM Remote Encoder/Decoder Circuit

This is a simple post which shows you how to design FM remote encoder and
decoder circuit using RF600E and RF600D ICs. This pair of encoder and decoder
ICs establishes the communication with high level security. The operating
voltage of these ICs is from 2V to 6.6V DC.

3. Health Monitoring System using 7-Segment Display

This health monitoring system is a very useful system, which can be used to
monitor the health parameters of the patient. This system continuously monitors
the heart rate and the temperature reading of the patient. In this health
monitoring system project, we use two 7 segment modules to display the
parameters, as the display has a greater viewing distance. We can select the
upper limit and lower limit for the temperature and heartbeat as well. While
monitoring, if the temperature is increased beyond the set high limit or is
decreased below the set limit then the buzzer sounds and the load turns off.
Similarly, when we remove the heartbeat sensor and system detects low
heartbeat and buzzer buzzes and the load is switched off. This buzzer can help
the patient’s well-wishers to take action in an emergency. When the
temperature and heart rate come into control the bulb turns on and the alarm
gets off.

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