DIGITAL PRINCIPLES AND SYSTEM DESIGN L T P C

19EC303
Common to ECE, BME, CSE, IT, ME 3 0 2 4

Preamble
Digital electronic circuits are the heart of cell phones, digital cameras, computers, personal
digital assistants, GPS and many other consumer products that process and use information in
digital format. This course, Digital Principles and System Design, introduces the basics of
digital circuits and fundamental concepts used in their design. The course gives elaborate
description of analysis and design of combinational and sequential circuits. Application
Specific Integrated Circuits are designed by using a Hardware Description Language (HDL),
such as Verilog or VHDL. In this course, introduction to VHDL is given, to design the
circuits.

Prerequisite
NIL

Course Outcomes
On the successful completion of the course, students will be able to

CO1 Understand Boolean algebra and minimization of logic expressions Apply

CO2 Design and analyze various combinational digital circuits Analyze

CO3 Introduce the analysis and design procedures for synchronous sequential circuits Analyze

Introduce the analysis and design procedures for asynchronous sequential circuits Analyze
CO4

CO5 Introduce the electronic circuits involved in the making of logic gates Remember

Mapping of COs with POs and PSOs

CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3

CO1 3 2 1 3 3 3 - - - - 3 2 3 2 1

CO2 3 2 3 2 3 2 - - - - 1 3 3 2 2

CO3 2 3 2 3 1 1 - - - - 1 2 3 2 1

CO4 3 2 1 2 1 3 - - - - 3 1 3 2 1

CO5 3 3 2 3 3 1 - - - - 1 2 3 2 1

1
Concept Map

Syllabus

UNIT I DIGITAL FUNDAMENTALS 12

Number Systems – Decimal, Binary, Octal, Hexadecimal, 1„s and 2„s complements, Codes –
Binary, BCD, Excess 3, Gray, Alphanumeric codes, Boolean theorems, Logic gates, Universal
gates, Sum of products and product of sums, Minterms and Maxterms, Karnaugh map
Minimization and Quine- McCluskey method of minimization.
Verification of Boolean law using logic gates.

UNIT II COMBINATIONAL CIRCUIT DESIGN 26

Design of Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry look
ahead Adder, BCD Adder, Code Converters, Multiplexer, Demultiplexer, Magnitude
Comparator, Decoder, Encoder, Priority Encoder, Parity Generator and Checker, HDL models
of Combinational circuit.
Design and Verification combinational circuit: Half and Full Adders, Half and Full
Subtractors, Binary Parallel Adder – Carry look ahead Adder, BCD Adder, conversion of Binary
to BCD code, Binary to Excess-3, Excess-3 to Binary, Binary to Gray and Gray code to
Binary.Multiplexer, Demultiplexer, Magnitude Comparator, Decoder, Encoder, Priority
Encoder. Simulation of Combinational circuit: Half and Full Adders, Half and Full

2
Subtractors, Multiplexer, Demultiplexer, Magnitude Comparator, Decoder, Encoder, Priority
Encoder.

UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS 18

Flip flops – SR, JK, T, D, Master/Slave FF – operation and excitation tables, Triggering
of FF, Analysis and design of clocked sequential circuits – Design – Moore/Mealy
models, state minimization, state assignment, circuit implementation – Design of Counters-
Ripple Counters, Ring Counters, Shift registers, Universal Shift Register, HDL models of
counters.
Verification of Flipflops: SR, JK, T, D using digital ICs, Design and verification of
synchronous sequential circuit: Counters- Ripple Counters, Ring Counters. Simulation of
Synchronous Sequential circuit: Mod -10 Counter, up/down counter.

UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS 10

Introduction - Analysis procedure –Transition table – Flow table – Races - Design
procedure – Reduction of state and flow table – Hazards

UNIT V MEMORY DEVICES AND DIGITAL INTEGRATED CIRCUITS 9

Introduction - Basic memory structure – ROM -PROM – EPROM – EEPROM, RAM – Static
and dynamic RAM – Programmable Logic Devices – Programmable Logic Array (PLA) –
Programmable Array Logic (PAL) – Field Programmable Gate Arrays (FPGA) –
Implementation of combinational logic circuits using PLA, PAL.

Digital integrated circuits: Logic levels, propagation delay, power dissipation, fan-out and fan-
in, noise margin, logic families and their characteristics-RTL, TTL, ECL, CMOS.

Total Periods: 75
Lab Requirements for a batch of 30 Students:
Hardware Required

1 Personal Computer - 15 Nos.

.2 IC Trainer kit - 15 Nos
3. Bread Board - 15 Nos
4. Dual power supply/ single mode power - 15 Nos
5. Seven
supplySegment display - 15 Nos
6. Multimeter - 15 Nos
.7 IC each 50 Nos
7400/ . 7402/ 7404/ 7486/ 7408/ 7432/ 7483/ 74150/ 74151/ 74147/ 7476/ 7445/ 555/
74180/ 7485/ 7411/ 7474/ 74138

Software Required

S.NO EQUIPMENT REMARKS

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 1 Xilinx ISE/Altera Quartus/ equivalent EDA Tools 10 User License

Text Books
1. M. Morris Mano and Michael D. Ciletti, Digital Design, 5th Edition, Pearson, 2014.
2. Charles H.Roth. ―Fundamentals of Logic Design, 6th Edition, Thomson Learning, 2013

Reference Books
1. Thomas L. Floyd, Digital Fundamentals, 10th Edition, Pearson Education Inc, 2011.
2. S.Salivahanan and S.Arivazhagan, Digital Electronics, 1st Edition, Vikas Publishing
House Private Ltd, 2012.
3. Soumitra Kumar Mandal, Digital Electronics, McGraw Hill Education Private Limited,
2016.

Course Designers

1. Dr. C. Sheeba Joice – sheebajoice@saveetha.ac.in

2. Mr. R. Jagadeshwaran – jagadeshwaran@saveetha.ac.in