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COURSEMATERIAL

DIGITAL ELECTRONICS &

SUBJECT MICROPROCESSOR)

UNIT 3

COURSE B.TECH

SEMESTER III

COMPUTER SCIENCE AND

DEPARTMENT
ENGINEERING & INFORMATION
TECHNOLOGY

PREPAREDBY
Dr. G CHANDRAIAH
(Faculty Name/s) Assoc. Professor

VERSION V5

PREPARED/REVISEDDATE

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TABLEOF CONTENTS– UNIT-4

SNO CONTENTS PAGE
1 COURSE OBJECTIVES 1
2 PREREQUISITES 1
3 SYLLABUS 1
4 COURSE OUTCOMES 1
5 CO-PO/PSOMAPPING 2
6 LESSONPLAN 2
7 ACTIVITYBASEDLEARNING 2
8 LECTURE NOTES 2
3.1 INTRODUCTION 2
3.2 S R Latch,D latch 3
3.3 S R flip-flop,D flipflop 4
3.4 Master and Slave flip flop 6
Delay flip flop
3.5 8
3.6 T flip flop 9
3.7 Registers ,shift registers 10
3.8 Universal Shift Registers 15
3.9 Counters 16
9 PRACTICEQUIZ 23
10 ASSIGNMENTS 24
11 PARTA QUESTIONS & ANSWERS (2MARKS QUESTIONS) 25
12 PARTB QUESTIONS 26
13 SUPPORTIVE ONLINE CERTIFICATION COURSES 26
14 REAL TIME APPLICATIONS 26
15 CONTENTS BEYOND THE SYLLABUS 26
16 PRESCRIBED TEXT BOOKS & REFERENCE BOOKS 26
17 MINI PROJECT SUGGESTION 27

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1. COURSE OBJECTIVES
The objectives of this course are to
1. Introduce the classification of digital circuits and sequential circuits.
2. Outline knowledge on analysis of sequential circuits and design procedure of
combinational circuits.
3. Apply knowledge of K-maps to attain simplified Boolean function.
4. Acquainting with classical hardware design of combinational circuits.
5. Knowledge and hands-on experience that will enable them to work in a digital
system design.

2. PREREQUISITES
Students should have knowledge on
1. Basic Mathematics
3. SYLLABUS
UNIT III
Synchronous Sequential Circuits: Latches, Flipflops, Analysis of clocked Synchronous
Sequential Circuits,.
Registers and Counters: Registers, shift registers, Ripple counters, Synchronous
counters and other counters.
4. COURSE OUTCOMES
1. Describe behavior of Flip-Flops and Latches. (L2)

2. Design synchronous sequential circuits using flipflops and construct digital systems
using components such as registers and counters(L4)
3. Utilize concepts of state and state transition for analysis and design of sequential
circuits(L3)

4. Design synchronous sequential circuits using flipflops and construct digital systems
5. CO-PO/PSOMapping

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 P10 PO11 PO12 PSO1 PSO2
DLD
CO1 3 2 3

CO2 2 3 2

CO3 2 2 2

CO4 3 2 3

CO5 2 3 3

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6. LESSON PLAN

LECTURE WEEK TOPICSTOBECOVERED REFERENCES

1 SEQUENTIAL CIRCUITS ,LATCHES & FLIPFLOPS T1,R1

2 S R LATCH ,D LATCH T1,R1

1
3 S R FLIPFLOP,D FLIPFLOP T1,R1

4 J K FLIP FLOP ,RACE AROUND CONDITION T1,R1

5 MASTER AND SLAVE FLIPFLOP,T FLIPFLOP T1,R2

6 REGISTERS,SHIFT REGISTERS T1,R1

2
7 UNIVERSAL SHIFT REGISTERS T1,R1

8 RIPPLE COUNTERS T1,R1

9 Up-Down ASynchronous counters T1,R1

10 Modulus-n Counter T1,R1

3
11 Synchronous counter T1,R1

12 Up-Down Synchronous counter T1,R1

13 Discussion of objective type questions & Short answer questions T1,R1

4
14 Discussion of Previous year university questions in question papers T1,R1
7. ACTIVITYBASEDLEARNING
1. Crossword Puzzle–Code Convertors
8. LECTURE NOTES
3.1. INTRODUCTION
The combinational circuit does not use any memory. Hence the previous state of
input does not have any effect on the present state of the circuit. But sequential circuit
has memory so output can vary based on input. This type of circuits uses previous input,
output, clock and a memory element.

Block diagram

Fig.3.1.The block diagram of a Sequential circuit

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Flip Flop

Flip flop is a sequential circuit which generally samples its inputs and changes its outputs
only at particular instants of time and not continuously. Flip flop is said to be edge sensitive
or edge triggered rather than being level triggered like latches.

3.2. SR Latch

The bistable element is able to remember or store one bit of information. However,
because it does not have any inputs, we cannot change the information bit that is stored
in it. In order to change the information bit, we need to add inputs to the circuit. The
simplest way to add inputs is to replace the two inverters with two NAND gates. This circuit
is called a SR latch. In addition to the two outputs Q and Q', there are two inputs S' and R'
for set and reset respectively. Following the convention, the prime in S and R denotes that
these inputs are active low. The SR latch can be in one of two states: a set state when Q =
1, or a reset state when Q = 0.

Fig.3.2.SR latch using NAND gates

To make the SR latch go to the set state, we simply assert the S' input by setting it to 0.
Remember that 0 NAND anything gives a 1, hence Q = 1 and the latch is set. If R' is not
asserted (R' = 1), then the output of the bottom NAND gate will give a 0, and so Q' = 0. This
situation is shown in Figure 4 (d) at time t0. If we de-assert S' so that S' = R' = 1, the latch will
remain at the set state because Q', the second input to the top NAND gate, is 0 which will

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keep Q = 1 as shown at time t1. At time t2 we reset the latch by making R' = 0. Now, Q'
goes to 1 and this will force Q to go to a 0. If we de-assert R' so that again we have S' = R'
= 1, this time the latch will remain at the reset state as shown at time t3. Notice the two
times (at t1 and t3) when both S' and R' are de-asserted. At t1, Q is at a 1, whereas, at t3, Q
is at a 0. When both inputs are de-asserted, the SR latch maintains its previous state.
Previous to t1, Q has the value 1, so at t1, Q remains at a 1. Similarly, previous to t3, Q has
the value 0, so at t3, Q remains at a 0.

Fig.3.2.SR latch using NOR gates

If both S' and R' are asserted, then both Q and Q' are equal to 1 as shown at time t4. If
one of the input signals is de-asserted earlier than the other, the latch will end up in the
state forced by the signal that was de-asserted later as shown at time t5. At t5, R' is de-
asserted first, so the latch goes into the normal set state with Q = 1 and Q' = 0.
A problem exists if both S' and R' are de-asserted at exactly the same time as shown at
time t6. If both gates have exactly the same delay then they will both output a 0 at
exactly the same time. Feeding the zeros back to the gate input will produce a 1, again
at exactly the same time, which again will produce a 0, and so on and on. This oscillating
behavior, called the critical race, will continue forever. If the two gates do not have
exactly the same delay then the situation is similar to de-asserting one input before the
other, and so the latch will go into one state or the other. However, since we do not know
which is the faster gate, therefore, we do not know which state the latch will go into. Thus,
the latch’s next state is undefined.

3.3 .S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input. It is also called
as level triggered SR-FF. For this, circuit in output will take place if and only if the enable
input (E) is made active. In short this circuit will operate as an S-R latch if E = 1 but there is
no change in the output if E = 0.

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Block Diagram

Circuit Diagram

Fig.3.3.SR Flipflop using NAND gates

Truth Table

Table.3.1. S R flipflop

Operation

S.NO. Condition Operation

If S = R = 0 then output of NAND gates 3 and 4

are forced to become 1.

1 S = R = 0 : No change Hence R' and S' both will be equal to 1. Since S'
and R' are the input of the basic S-R latch using
NAND gates, there will be no change in the state
of outputs.

Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1

the output of NAND-4 i.e. S' = 0.
2 S = 0, R = 1, E = 1

Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset

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condition.

Output of NAND-3 i.e. R' = 0 and output of

NAND-4 i.e. S' = 1.
3 S = 1, R = 0, E = 1
Hence output of S-R NAND latch is Qn+1 = 1 and
Qn+1 bar = 0. This is the reset condition.

As S = 1, R = 1 and E = 1, the output of NAND

gates 3 and 4 both are 0 i.e. S' = R' = 0.
4 S = 1, R = 1, E = 1
Hence the Race condition will occur in the basic
NAND latch.

3.4. Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the output of second to
input of first. Master is a positive level triggered. But due to the presence of the inverter in
the clock line, the slave will respond to the negative level. Hence when the clock = 1
(positive level) the master is active and the slave is inactive. Whereas when clock = 0 (low
level) the slave is active and master is inactive.

Circuit Diagram

Fig.3.4.JK Flipflop

Truth Table

Table.3.2.J K flipflop
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Operation

S.N. Condition Operation

When clock = 0, the slave becomes active and

master is inactive. But since the S and R inputs have
J = K = 0 (No
1 not changed, the slave outputs will also remain
change)
unchanged. Therefore outputs will not change if J =
K =0.

Clock = 1 − Master active, slave inactive. Therefore

outputs of the master become Q1 = 0 and Q1 bar =
1. That means S = 0 and R =1.

Clock = 0 − Slave active, master inactive. Therefore

outputs of the slave become Q = 0 and Q bar = 1.

Again clock = 1 − Master active, slave inactive.

J = 0 and K =
2 Therefore even with the changed outputs Q = 0
1 (Reset)
and Q bar = 1 fed back to master, its output will be
Q1 = 0 and Q1 bar = 1. That means S = 0 and R = 1.

Hence with clock = 0 and slave becoming active

the outputs of slave will remain Q = 0 and Q bar =
1. Thus we get a stable output from the Master
slave.

Clock = 1 − Master active, slave inactive. Therefore

outputs of the master become Q1 = 1 and Q1 bar =
0. That means S = 1 and R =0.

Clock = 0 − Slave active, master inactive. Therefore

J = 1 and K =
3 outputs of the slave become Q = 1 and Q bar = 0.
0 (Set)

Again clock = 1 − then it can be shown that the

outputs of the slave are stabilized to Q = 1 and Q
bar = 0.

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Clock = 1 − Master active, slave inactive. Outputs
of master will toggle. So S and R also will be
inverted.

Clock = 0 − Slave active, master inactive. Outputs

of slave will toggle.
J = K = 1
4
(Toggle) These changed outputs are returned back to the
master inputs. But since clock = 0, the master is still
inactive. So it does not respond to these changed
outputs. This avoids the multiple toggling which
leads to the race around condition. The master
slave flip flop will avoid the race around condition.

3.5. Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected
between S and R inputs. It has only one input. The input data is appearing at the output
after some time. Due to this data delay between i/p and o/p, it is called delay flip flop. S
and R will be the complements of each other due to NAND inverter. Hence S = R = 0 or S =
R = 1, these input condition will never appear. This problem is avoid by SR = 00 and SR = 1
conditions.

Block Diagram

Circuit Diagram

Fig.3.5.D Flipflop

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Truth Table

Table.3.3. D flipflop

Operation

S.N. Condition Operation

1 E=0 Latch is disabled. Hence no change in output.

If E = 1 and D = 0 then S = 0 and R = 1. Hence

irrespective of the present state, the next state is
2 E = 1 and D = 0
Qn+1 = 0 and Qn+1 bar = 1. This is the reset condition.

If E = 1 and D = 1, then S = 1 and R = 0. This will set

the latch and Qn+1 = 1 and Qn+1 bar = 0 irrespective
3 E = 1 and D = 1
of the present state.

3.6.Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected
together. It has only input denoted by T as shown in the Symbol Diagram. The symbol for
positive edge triggered T flip flop is shown in the Block Diagram.

Symbol Diagram

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Block Diagram

Fig.3.5.D Flipflop

Truth Table

Table.3.4. T flipflop

Operation

S.No. Condition Operation

1 T = 0, J = K = 0 The output Q and Q bar won't change

Output will toggle corresponding to every leading

2 T = 1, J = K = 1
edge of clock signal.

3.7SHIFT REGISTERS:

Flip-flop is a 1-bit memory cell which can be used for storing the digital data. To
increase the storage capacity in terms of number of bits, it is required to use a group of
flip-flops. Such a group of flip-flops is known as a Register .Then-bit register will consist of n
number of flip-flop and it is capable of storing an n-bit word. The binary data in a register
can be moved within the register from one flip-flop to another. The registers that allow
such data transfers are called as shift registers. There are four mode of operations of a shift
register.

● Serial Input Serial Output

● Serial Input Parallel Output
● Parallel Input Serial Output

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● Parallel Input Parallel Output
3.7.1.Serial Input Serial Output

Let all theflip-flop be initially in the reset condition i.e.,Q3=Q2=Q1=Q0 = 0. If an entry

of a four-bit binary number 1 1 1 1 is made into the register, this number should be applied
to Din bit with the LSB bit applied first. The D input of FF-3 i.e., D3 is connected to serial
data input Din. Output of FF-3 i.e., Q3 is connected to the input of the next flip-flop i.e.,D2
and soon.

Block Diagram

Fig.3.6. Serial Input Serial Output

3.7.2 .Serial Input Parallel Output

● In such types of operations,the data is entered serially and taken out in parallel
fashion.

● Data is loaded bit by bit. The outputs are disabled as long as the data is loading.
● As soon as the data loading gets completed, all the flip-flops contain their required
data; the outputs are enabled so that all t he loaded data is made available over
all the output lines at the same time.
● 4 clock cycles are required to load a four-bit word. Hence the speed of operation
of SIPO mode is same as that of SISO mode.

Fig.3.7. Serial Input Parallel Output

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3.7.3.Parallel Input Serial Output(PISO)

● Data bits are entered in parallel fashion.

● Thecircuitshownbelowisafour-bitparallelinputserialoutputregister.
● Output of previous FlipFlop is connected to the input of the next one viaa
combinational circuit.
● ThebinaryinputwordB0,B1,B2,B3 is applied though the same combinational circuit.
● Therearetwomodesinwhichthiscircuitcanworknamely-shiftmodeorloadmode.
Load mode

When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they
will pass B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of clock, the
binary input B0, B1, B2, B3 will get loaded into the corresponding flip-flops. Thus, parallel
loading takes place.

Shift mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become in active.
Hence the parallel loading of the data becomes impossible .But the AND gate 1,3 and 5
become active. Therefore, the shifting of data from left to right bit by bit on application of
clock pulses. Thus, the parallel in serial out operation takes place.

Fig.3.7 Parallel Input Serial Output(PISO)

3.7.4.Parallel Input Parallel Output(PIPO)
In this mode, the 4-bit binary input B0, B1, B2, B3 is applied to the datainputs D0, D1,
D2, D3 respectively of thefour flip-flops. As soonas anegative clock edge is applied, the
input binary bits will be loaded intothe flip-flops simultaneously. The loaded bits will appear
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simultaneously to the output side. Only clock pulse is essential to load all the bits.
Block Diagram

Fig.3.7. Parallel Input Parallel Output(PIPO)

3.7.5.Operation of 4-bit Register
Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the
number to be entered to Din. So Din = D3 = 1. Apply the clock.On the first falling edge of
clock, the FF-3 is set, and stored word in theregisterisQ3Q2Q1Q0=1000.

Fig.3.8.1. Serial Input Serial Output

Apply the next bit to Din. So Din=1.Assoonasthenextnegativeedgeof the clock hits,

FF-2 will set and the stored word change to Q3 Q2 Q1Q0=1100.

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Apply the next bit to be stored i.e.1toDin.Apply the clock pulse.As soon as the third
negative clock edge hits, FF-1 will be set and output will be modifiedtoQ3Q2Q1Q0=1110.

Fig.3.8.2. Serial Input Serial Output

Truth Table

Table.3.5. Loading data in register

Waveforms:

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The simplest register is a 1-bit register. A 1-bit register is simply a single Dflip-flop.It
holds a logical value of exactly one bit in length.Larger registers can hold longer strings of
bits. For example, an 8-bit register holds an 8-bit logical value(i.e.,10110110),and it is
formed by a collection of eight D flip-flops.In order to form a register,form a collection of
flip-flops, the flip-flops must all run on the same clock signal. In general, there are two
majorty pes of registers:
3.7.6. Parallel-Load Registers Shift Registers.

Parallel load registers are a type of register where the individual bit values are
loaded simultaneously. More specifically, every flip-flop with in the register takes an
external data input, and these inputs are loaded in to the flip-flops on the same edge in a
clock cycle.

Fig.3.9. Parallel Input Parallel Output(PIPO)

It is a simple 4-bit parallel-load register where D0, D1, D2, and D3 are theindividual
data bits; Q0, Q1, Q2, and Q3 form the output value (as a 4-bitwordQ3Q2Q1Q0);and
Clock is the single clock signal.
Load Signal

Many commonly used parallel-load registers, however, also implement a load

signal. A load signal is used to synchronize the loading of a register'sflip-
flopsincaseswheretheindividualdatainputsarenotprovidedsimultaneously. When the load
signal is set, all the flip-flops in the register are loaded with the provided data inputs during
the next clock cycle.When the load signal is clear, all the flip-flops retain their current
value.This functionality is often implemented using multiplexers, or multiplexers.

3.8.Universal Shift Register

A shift registers which can shift the data in only one direction is called a
unidirectional shift register. A shift registers which can shift the data inboth directions is
called a bi-directional shift register. Applying the same logic, a shift registers which can
shift the data in both directions as well as loads it parallelly, is known as a universal shift

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register. The shift register is capable of performing the following operation−

● Parallel loading
● Left Shifting
● Right shifting
The mode control input is connected to logic 1 for parallel loading operation where
as it is connected to 0 for serial shifting. With mode control pin connected to ground, the
universal shift register acts as a bi-directional register. For serial left operation, the input is
applied to the serial input which goes to AND gate-1 shown in figure. Whereas for the shift
right operation ,the serial input is applied to D input.

Block Diagram

Fig.3.10. Universal Shift Register

Applications of shift Registers

● The shift registers are used for temporary data storage.

● The shift registers are also used for data transfer and data manipulation.
● The serial-in serial-out and parallel-in parallel-out shift registers are used to produce
time delay to digital circuits.

● The serial-in parallel-out shift register is used to convert serial data into parallel data
thus they are used in communication lines where demultiplexing of a data line into
several parallel line is required.

● A Parallel in Serial out shift register is used to convert parallel data to serial data.

3.9.COUNTERS

A register that goes through a prescribed sequence of states

upon the application of input pulses is called a counter.A counter that follows
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the binary number sequence is called a binary counter. An n-bit binary counter
consists of n flip-flops and can count in binary from 0 through 2n-1.

3.9.1.RIPPLE BINARY COUNTER (BRC)

• A binary ripple counter consists of a series connection of complementing flip-flops,

with the output of each flip-flop connected to the c‘ input of the next higher order
flip-flop.
• The flip-flop holding the least significant bit receives the incoming count pulses.
• The counter is constructed with the complementing flip-flops of the T type,D type
andJK type.
• Complementing flip-flops can be obtained from JK Flip-flop – with the J&K inputs tied
together=1TFlip-flop–Tinput=1DFlip-flop
–D input is connected to complement output.
Using T Flip-Flop:

• The T inputs are connected to permanent logic1.

• This complements the flip-flop, if the clock input goes through a negative transition
(i.e)1to0.
• The negative transition occurs when the output of the previous flip-flop to which c is
connected goes from 1to 0.

Fig.3.11. counter using T flipflop

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Count starts with binary 0, initially Since T=1, A0 = 1 (complemented) , the transition
of A0 is 0 to 1, so positive transition, which does not affect the other higher order bits.
In the next clock pulse, since T = 1, A0 = 0, complemented again, the transition of A0 from
1 to 0 is negative transition, so triggers the next flip-flop,whose output A1 is
complemented.
A1‘s transition from 0to1 is not propagated. Like wise,the counter counts upto 15 and
goes back to 0 to repeat the count.

ClockPulse A3 A2 A1 A0

Initially 0 0 0 0

1stClock pulse 0 0 0 1
T1=1,A0 is complements.
A0 from 0 to 1 is +ve transition doesnot affect
other flipflops
2ndClock pulse 0 0 1 0
A0from1to0is–vetransition
,so affectA1from0to1(+ve transition) does not
affect other flipflops

3rdclock pulse 0 0 1 1
A0 from 0 to 1 (+ve transition)does not affect
other flipflops
4thclock pulse 0 1 0 0
A0 from1to0(-ve)A1from1to0(-ve)
A2 from 0 to1(+ve)does not affect A3.

5thclock pulse 0 1 0 1

3.9.2.SYNCHRONOUS COUNTER

• Clock pulses are applied to the inputs of all flip-flops.

• A common clock triggers all flip-flops simultaneously.
• The design whether a flip-flop is to be complemented is determined from the
values of the data inputs such as T or JK at the time of the clock edge. If T=0 or
J=K=0, the flip flop does not change.T=1 or J=K=1,the flipflop complements.

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I) Design a 4 BIT BINARY UP COUNTER
State Table:
PresentState Next State Flip-Flop Inputs

A B C D A B C D JA KA JB KB JC KC JD KD
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X

0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X

0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1

1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X

1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1
1 1 0 0 1 1 0 1 X 0 X 0 0 X 1 X

1 1 0 1 1 1 1 0 X 0 X 0 1 X X 1
1 1 1 0 1 1 1 1 X 0 X 0 X 0 1 X

1 1 1 1 0 0 0 0 X 1 X 1 X 1 X 1

Excitation table for JK Flip-Flop StateDiagram

Q(t) Q(t+1) J K

0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

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II) DESIGN A BINARY UP-DOWN COUNTER
• The two operation (up & down) can be combined together in one circuit to form a
counter capable of counting whether up or down.
• When the up input is‗1‘,the circuit counts up. When the down inputis‗1‘,the circuit
counts down.

UP DOWN Operation

0 0 No Change

0 1 Counts down

1 0 Counts up

1 1 Counts up

The up input has priority over the down input

JA=BCD+B‘C‘D‘ JB =CD+C‘D‘JC=D+D‘ JD=1
KA=BCD+B‘C‘D‘ KB=CD+C‘D‘KC =D+D‘ KD=1
TA=BCD+B‘C‘D‘ TB =CD+C‘D‘TC=D+D‘ TD=1

Fig.3.12. Binary up down counter

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iii) Design a MOD10 counter using JK FlipFlips

MOD-10 counter reaches state10 (1010).i.e.,Q3Q2Q1Q0=10 10 .The outputs Q3 and Q1

are connected to the NAND gate and the output of the NAND gate goes LOW and resetting
all Flip-Flops to zero. Therefore MOD-10 counter counts from 0000to 1001. And then recycles to
the zero value. TheMOD-10 counter circuit is shown below.

Fig.3.12. MOD-10 counter circuit

iv) Design a 3-Bit Asynchronous Binary Counter (or) binary ripple counter
The basic operation is the same as that of the 2-bit counter except that the 3-bit
counter has eight states, due to its three Flip-Flops. A timing diagram is shown below for
eight clock pulses. Notice that the counter progresses through a binary count of zero
through seven and then recycles to the zero state. This counter can be easily expanded
for higher count, by connecting additional toggle Flip-Flops.

Fig.3.12. 3-bit Asynchronous binary counter

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9. PracticeQuiz:
(a) Multiple Choice Questions:
1. In which of the following circuits the output of a flip flop will be applied as a
clock input to next stage flip flop
(a)Binary synchronous counter (b)ripplecounter
(c) Ring counter (d) shiftregister
2. Mod60 binary counter requires flipflops
a)60 (b)4 (c)5 (d) 6
3. A 5 bit Johnson counter can count
(a)5 (b)32 (c) 10 (d)31
4. A universal shift register can perform
(a) Serial right shift (b)serial left shift(c)parallel load(d)all the above
5. Assume that a 4-bit counter starts in 0000 state. What will be the count
after10 clock pulses and then active reset occurs?
(a)1100 (b)1001 (c)0000 (d)1111
6. The shift in which 0 getsappendedatLSBpositionis
(a) Right shift(b)logical left shift(c)parallel load(d)none
7. Amod-12 binary counter will count in the sequence ranging from0000 to----
(a)1111 (b)1011 (c)1101 (d)1100
8. The design of mod 6 counter requiresjk flip
flops(a)2(b)6 (c)12 (d) 3
9. The binary data 1101 is loaded into a 4-bit ring counter, the data on the
register after being shifted twice is
(a)0001 (b)1110 (c)0110 (d)1011
10. In order to implement a state diagram of seven states we need minimum of
(a) 5flipflops(b)4flipflops (c) 2flip flops(d)7flipflops
(b) Fill in the blanks
1. The condition SR=11is known as (Ans: not applicable condition)
2. An SR latch can be implemented using---NOR gates NAND gates(Ans:2,4)
3. A latch responds to ----- where as a flip flop responds to (Ans: level, edge)

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4. A sequential counter counts in ----- while anon-sequential counter counts in a
Fashion (Ans: sequence, random)
5. The maximum clock frequency with the increase the flip flops in an
asynchronous counter (Ans: decreases)
6. The modulus of a10-bit ripple counter is(Ans:1024)
7. T=D xor q converts (Ans:T flipflopto D flipflop)
8. Race problem can be solved by (Ans: using master-slave concept)
9. Asynchronous circuits do not operate with the(Ans:clock)
10. An N bit counter that divides the clock frequency by N called
(Ans:ringcounter)
(c) Trueorfalse
1. An bit ring counter can count n clock pulses(2n) [ F]
2. The purpose of RESET input in a sequential circuit is to clear flip flop input[ F]
(f/foutput)
3. The number of flip flops required to realize mod-16 Johnson counter is 8[T]
4. The type o fflipflop used in a shift register is Dflipflop [ T]
5. The shift register can be used as time delay circuit [ T]
6. A4bitserialadderconsistsof3fulladders,2dflipflops(1,1) [ F]
7. The shift in which ‘0’getsappendedatMSBpositionislogicalrightshift[T]
8. JK flipflop complements its outputs whenJ=K=1 [ T]
9. A ring counter which can count5 clockpulsescontains10 flip flops(10)[F]
10. the counting sequence of a modulo -6 gray code counter is
000,001,011,010,100,101,111,110[ T]
10. Assignments:
1. Design a 4-bit binary ripple down-counter using D-flip flops with relevant
timing diagrams
2. Explain the design procedure for sequential logic circuits and give the
classification of sequential logic.
3. Design, Draw and explain a synchronous mod-12 down counter using J-K
flipflop?
4.Explain the following.
i. Race-around condition in flip-flop
ii. J-K Master Slave flip-flop

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iii. Excitation table for flip-flops
5. Convert SR Flip-Flop into JK-Flip-Flop?

11. PARTA QUESTIONS & ANSWERS (2MARKS QUESTIONS)

1. Define sequential circuit?
In sequential circuits the output variables dependent not only on the
present input variables but they also depend upon the past history of these
input variables.

2. Give the comparison between combinational circuits and sequential

circuits.MemoryunitisnotrequiredMemoryunityisrequiredParalleladderisa
Combinational circuit Serial adder is a sequential circuit.

3. What do you mean by present state & next state?

The information stored in the memory elements at any given time
definesthepresentstateofthesequentialcircuit.Thepresentstateandtheextern
al inputs determine the outputs and the next state of the sequential circuit.
4. What are the types of sequential circuits?
Synchronoussequentialcircuits2.Asynchronoussequentialcircuits
5. Define shift Registers? What are the types of shift register?
The binary information in a register can be moved from stage to stage
within the register or into or out of the register upon application of clock
pulses. This type of bit movement or shifting is essential for certain arithmetic
and logic operations used in microprocessors. This gives rise to a group of
registers called shift registers.
Type of shift registers:
1. Serial in serial out shift register

2. Serial in parallel out shift register

3. Parallel in serial out shift register
4. Parallel in parallel out shiftregister
5. Bidirectional shift registers shift register.
6. What are the types of counter?
1. Synchronous counter 2.AsynchronousCounter

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12. Part-B Questions:
1. Compare synchronous and Asynchronous Sequential circuits with examples.
2. Draw the circuit diagram of 4-bit ring counter D-flipflop and explain its
operation.
3. Draw a mod- 6,counter with the following sequence:5,6,7,8,9,10
4. Design a 4-bit binary ripple down counter using a negative edge trigger D-flip
flop.
5. Discuss about synchronous and ripple counters. Compare their merits
and demerits.
6. What do you mean by universal shift register? Draw and explain its
circuit diagram and operation.
7. With neat diagram, explain in detail the operation of a bidirectional
shift registers and also write applications of shift register.
13. Supportive online Certification Courses
1. Digital Systems Design by Prof.D .Roychoudhury ,conducted by IITKharagpur–12
weeks.
2. Digital Electronics circuit By Prof. Gowtham Saha conducted by IIT Kharagpur-12
weeks.
14. Real-TimeApplications
1. Microcontrollers
2. Frequency Synthesizers
3. Digital Clocks
4. Timing circuits
5. Circuits in Communication systems.
15. Content Beyond Syllabus
1. Twisted Ring counter
2. Universal Shift Register
3. Reduction of state flow tables
4. Race-free state assignment
5. Cascaded Counters
16. Prescribed Text Books & Reference Books
Text Book
1. M.MorrisManoandMichaelD.Ciletti,“DigitalDesign",4thEdition,PearsonEducation,2
013.
2. Z.KohaviandN.K.Jha,“SwitchingandFiniteAutomataTheory”,3rdEdition,TataMcGr
awHill,2010.
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3. R.P.Jain,"ModernDigitalElectronics",4thedition,McGrawHillEducation(IndiaPrivate
Limited),2012.
References:
1. Simon Haykin,“ Communication Systems”,3rdEdition,Wiley,2010.
17. Mini Project suggestion
1. Digital Counter
2. Scoring game circuit

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