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COURSE MATERIAL

Linear and Digital IC Applications

SUBJECT (15A03503)

UNIT 2

COURSE B.TECH

SEMESTER 31

ELECTRICAL and ELECTRONICS

DEPARTMENT ENGINEERING

PREPARED BY Dr. DILEEP KUMAR P,

(Faculty Name/s) Assistant Professor

VERSION 1.0

PREPARED / REVISED DATE 20-12-2020

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TABLE OF CONTENTS – UNIT 2

SNO CONTENTS PAGE
1 COURSE OBJECTIVES 1
2 PREREQUISITES 1
3 SYLLABUS 1
4 COURSE OUTCOMES 1
5 CO - PO/PSO MAPPING 1
6 LESSON PLAN 2
7 ACTIVITY BASED LEARNING 2
8 LECTURE NOTES 2
8.1 INTRODUCTION TO 555 TIMER 2
8.2 FUNCTIONAL BLOCK DIAGRAM OF 555 TIMER 4
8.3 MONOSTABLE OPERATION OF 555 TIMER 6
8.4 ASTABLE OPERATION OF 555 TIMER 8
8.5 SCHMITT TRIGGER 11
8.6 BLOCK SCHEMATIC OF PHASE LOCKED LOOP(PLL) 12
8.7 INDIVIDUAL BLOCKS OF 565 PLL 14
8.8 BASIC DAC TECHNIQUES 20
8.9 Different Types of ADC 28
8.10 DAC and ADC Specifications 36
9 PRACTICE QUIZ 37
10 ASSIGNMENTS 38
PART A QUESTIONS & ANSWERS (
11 38
2 MARKS QUESTIONS)
12 PART B QUESTIONS 39
13 SUPPORTIVE ONLINE CERTIFICATION COURSES 40
14 REAL TIME APPLICATIONS 41
15 CONTENTS BEYOND THE SYLLABUS 41
16 PRESCRIBED TEXT BOOKS & REFERENCE BOOKS 42
17 MINI PROJECT SUGGESTION 42

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1. COURSE OBJECTIVES
The objectives of this course is to
1. Introduce the fundamentals of 555 Timer
2. Develop knowledge and importance of Phase Locked Loop
3. Apply knowledge of basic ADC and DAC techniques
4. Acquire knowledge on specifications of DAC and ADC.
5. Knowledge and hands-on experience that will enable them to work in real time environment

2. PREREQUISITES
Students should have knowledge on
1. Basic Mathematics
2. Analog Circuits

3. SYLLABUS
UNIT II
Introduction to 555 timer , Functional diagram of 555 Timer, monostable and astable
operations and applications, Schmitt Trigger, PLL – Introduction, block schematic,
principles and description of individual blocks of 565. Basic DAC techniques –
Weighted resistor DAC, R-2R ladder DAC, inverted R-2R DAC, and IC 1408 DAC,
Different types of ADCs – parallel comparator type ADC, Counter type ADC,
successive approximation ADC and dual slope ADC, DAC and ADC specifications.

4. COURSE OUTCOMES
1. Apply the knowledge on fundamentals of 555 timer for doing various real time applications.
2. Design and analyse the various application of 555 timer
3. Explain and compare the working of multivibrators using special application IC 555 and general
purpose opamp.
4. Illustrate the function of application specific ICs such as PLL and its application in
communication.
5. Classify and comprehend the working principle of various data converters.
5. Co-PO / PSO Mapping

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 P10 PO11 PO12 PSO1 PSO2

CO1 3 3 3 3

CO2 3 3 3 3 3

CO3 3 3 3 3

CO4 3 3 3 3

CO5 3 3 3 3
6. LESSON PLAN
LECTUR REFERENC
WEEK TOPICS TO BE COVERED
E ES
1 1 Introduction to 555 timer T1

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 2 Functional diagram of 555 Timer T1, R1

3 Monostable Operation of 555 Timer T1, R1

4 Astable operation of 555 Timer T1, R1

5 555 Timer Applications T1, R2

6 555 Timer as Schmitt Trigger T1, R1

2
7 Phase locked Loop T1, R1

8 Individual blocks of PLL T1, R1

9 Various DAC Techniques T1, R1

3
10 Analog to Digital Converters T1, R1

7. ACTIVITY BASED LEARNING

1. Seminars on Important Topics
2. Technical Quiz
8. LECTURE NOTES
8.1 INTRODUCTION
The 555 timer IC is an integrated circuit (chip) used in a variety of timer, pulse
generation, and oscillator applications. The 555 can be used to provide time
delays, as an oscillator, and as a flip-flop element. The 555 timer IC was first
introduced around 1971 by the Signetics Corporation as the SE555/NE555 and
was called "The IC Time Machine" and was also the very first and only
commercial timer IC available.
8.1.1 Features of 555 Timer
 The 555 is a monolithic timer device which can be used to produce accurate and highly
stable time delays or oscillation. It can be used to produce time delays ranging from few
microseconds to several hours
 It has two basic operating modes: monostable and astable.
 It is available in three packages: 8-pin metal can, 8-pin mini DIP or a 14-pin. A 14-
pin package is IC 556 which consists of two 555 times.
 The NE 555 (signetics) can operate with a supply voltage in the range of 4.5v to 18v and
output currents of 200mA.
 It has a very high temperature stability, as it is designed to operate in the temperature
range of -55⁰c to 1250 c.
 Its output is compatible with TTL, CMOS and Op-Amp circuits

8.1.2. Pin Diagram of 555 Timer

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 The Pin diagram of 555 timer is shown in Figure 1.1

Fig. 1.1 Pin Diagram of 555 Timer

Pin 1. – Ground, The the 555 timer to the negative (0v) supply rail.
Pin 2. – Trigger, The negative input to comparator No 1. A negative pulse
on this pin “sets” the internal Flip-flop when the voltage drops
below 1/3Vcc causing the output to switch from a “LOW” to a
“HIGH” state.
Pin 3. – Output, The output pin can drive any TTL circuit and is capable of
sourcing or sinking up to 200mA of current at an output voltage
equal to approximately Vcc – 1.5V so small speakers, LEDs or
motors can be connected directly to the output.
Pin 4.  – Reset, This pin is used to “reset” the internal Flip-flop controlling the
state of the output, pin 3. This is an active-low input and is generally
connected to a logic “1” level when not used to prevent any
unwanted resetting of the output.
Pin 5. – Control Voltage, This pin controls the timing of the 555 by overriding
the 2/3Vcc level of the voltage divider network. By applying a
voltage to this pin the width of the output signal can be varied
independently of the RC timing network. When not used it is
connected to ground via a 10nF capacitor to eliminate any noise.
Pin 6.  – Threshold, The positive input to comparator No 2. This pin is used to
reset the Flip-flop when the voltage applied to it exceeds 2/3Vcc
causing the output to switch from “HIGH” to “LOW” state. This pin
connects directly to the RC timing circuit.
Pin 7.  – Discharge, The discharge pin is connected directly to the Collector
of an internal NPN transistor which is used to “discharge” the timing
capacitor to ground when the output at pin 3 switches “LOW”.
Pin 8.  – Supply +Vcc, This is the power supply pin and for general purpose TTL
555 timers is between 4.5V and 15V.
8.2. Functional Block Diagram of 555 Timer

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 The block diagram of a 555 timer is shown in the Fig. 1.2. A 555 timer
has two comparators, which are basically 2 op-amps), an R-S flip-flop, two
transistors and a resistive network.
 Resistive network consists of three equal resistors and acts as a voltage
divider.
 Comparator 1 compares threshold voltage with a reference voltage + 2/3
VCC volts.
 Comparator 2 compares the trigger voltage with a reference voltage + 1/3
VCC volts. Output of both the comparators is supplied to the flip-flop. Flip-
flop assumes its state according to the output of the two comparators.
One of the two transistors is a discharge transistor of which collector is
connected to pin 7. This transistor saturates or cuts-off according to the
output state of the flip-flop. The saturated transistor provides a discharge
path to a capacitor connected externally. Base of another transistor is
connected to a reset terminal. A pulse applied to this terminal resets the
whole timer irrespective of any input. The voltage across the capacitor is
represented in equation (1.1).

Fig. 1.2 Block Diagram of 555 Timer

1.1

 The internal resistors act as a voltage divider network, providing (2/3) Vcc at the non-inverting
terminal of the upper comparator and (1/3) Vcc at the inverting terminal of the lower comparator.
 In most applications, the control input is not used, so that the control voltage equals +(2/3) VCC.
Upper comparator has a threshold input (pin 6) and a control input (pin 5). Output of the upper
comparator is applied to Reset (R) input of the flip-flop. Whenever the threshold voltage exceeds the

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 control voltage, the upper comparator will reset the flip-flop and its output (Q) is low. Inverting
terminal (QI) high output from the flip-flop when given to the base of the discharge transistor
saturates it and thus discharges the transistor that is connected externally to the discharge pin 7.
 The complementary signal out of the flip-flop goes to pin 3, the output. The output available at pin 3
is low. These conditions will prevail until lower comparator triggers the flip-flop. Even if the voltage
at the threshold input falls below (2/3) VCC, that is upper comparator cannot cause the flip-flop to
change again. It means that the upper comparator can only force the flip-flop’s output high. To
change the output of flip-flop to low, the voltage at the trigger input must fall below + (1/3) Vcc.
When this occurs, lower comparator triggers the flip-flop, forcing its output low. The low output
from the flip-flop turns the discharge transistor off and forces the power amplifier to output a high.
These conditions will continue independent of the voltage on the trigger input.
 Lower comparator can only cause the flip-flop to output low. From the above discussion it is
concluded that for the having low output from the timer 555, the voltage on the threshold input must
exceed the control voltage or + (2/3) VCC. This also turns the discharge transistor on.
 To force the output from the timer high, the voltage on the trigger input must drop below +(1/3)
VCC. This turns the discharge transistor off. A voltage may be applied to the control input to change
the levels at which the switching occurs. When not in use, a 0.01 nano Farad capacitor should be
connected between pin 5 and ground to prevent noise coupled onto this pin from causing false
triggering.
 Connecting the reset (pin 4) to a logic low will place a high on the output of flipflop. The discharge
transistor will go on and the power amplifier will output a low. This condition will continue until
reset is taken high. This allows synchronization or resetting of the circuit’s operation. When not in
use, reset should be tied to +VCC.

8.2.1. Applications of 555 Timer

 Astable Multivibrator
 Monostable Multivibrator
 Missing Pulse Detector
 Linear Ramp Generator
 Frequency Divider
 Pulse Width Modulation
 FSK Generator
 Pulse Position Modulator
 Schmitt Trigger
8.3 555 TIMER AS A MONOSTABLE MULTVIBRATOR
The pin diagram of 555 timer in Monostable form is shown in Figure 1.3. The block diagram of
555 timer in Monostable operation is shown in Figure 1.4. In the stand by state, the flip-flop
holds transistor on, thus clamping external timing capacitor C to ground. The output remains at
ground potential ,i.e Low. As the trigger passes through VCC/3 ,the flip-flop is set i.e QI=0. This
makes the transistor Q1 OFF and the short circuit across the timing capacitor C is released. As Q I
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 is low, output goes High (=VCC).The timing cycle now begins. since C is unclamped, voltage
across it rises exponentially rises through R towards VCC with a time constant RC .After a time
period T ,the capacitor voltage VC is greater than 2/3 VCC and the upper comparator resets the
FF, that is R=1,S=0(assuming very small trigger pulse width). This makes Q I =1, transistor Q1
goes on (Saturates), thereby discharging the capacitor C rapidly to ground potential. The output
returns to ground potential.

Fig 1.3 : Monostable Multivibrator

Figure 1.4: Timer in monostable operation with functional diagram

It is noted that once triggered, the output remains in the HIGH
state until time T elapses, which depends only upon R and C. Any additional
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 trigger pulse will not change the output state. However if a negative going
trigger pulse is applied on reset terminal (Pin 4) during the timing cycle,
transistor Q 2 goes OFF, Q1 becomes ON and the external timing capacitor C is
immediately discharged. The output will be shown in Figure 1.5. It may be seen
that the output of Q 2 is connected directly to the input of Q1 so as to turn on Q1
immediately and thereby avoid the propagation delay through the FF. Now,
even if the RESET is released, the output will still remain LOW until a negative
going trigger pulse is applied at pin 2. The voltage across the capacitor is
represented in equation (1.2)

1.2

At t=T, 1.3

1.4
1.5
1.6
The time period for a monostable multivibrator is shown in equation (1.6)

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 Figure 1.5: Timing pulses

8.4 555 TIMER- Astable operation

 The device with pin Diagram for astable operation is shown in Fig. 1.6. The complete diagram
of astable multivibrator with detailed internal diagram of 555 is shown in Fig. 1.7
 In astable operation, timing resistor is now split into two sections RA and RB.

Figure 1.6: Astable Multivibrator using 555 Timer

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 Figure 1.7: Functional Diagram of astable multivibrator using 555 Timer

 Pin 7 of discharging transistor Q1 is connected to the junction of RA and RB.

 When the power supply VCC is connected, the external timing capacitor C charges towards
VCC, with a time constant (RA+RB)C
 During this time, output (pin 3) is High (=VCC) as Reset R=0,set S=1 and this combination
makes QI=0 which has unclamped the timing capacitor C.
 When the capacitor voltage is greater than 2/3 VCC (VC>2/3 VCC),the upper comparator triggers
the control FLIP-FLOP(FF), so that QI=1.This in turn makes transistor Q1 ON and capacitor C
starts discharging towards ground through RB and transistor Q1 with a time constant RBC.
current also flows into transistor Q1 through RA.
 Resistors RA and RB must be large enough to limit the current and prevent damage to transistor
Q1(RA=VCC/0.2)
 During the discharge of timing capacitor C, as it reaches just less than 1/3 V CC, the lower
comparator is triggered and at this stage S=1,R=0,which turns QI=0.
 Now QI=0 unclamps the external timing capacitor C.
 Therefore the capacitor periodically charged and discharged between 2/3 VCC and 1/3 VCC
respectively.
 Figure 1.8 shows the timing sequence and capacitor voltage waveform.

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 Figure 1.8: Timing sequence of astable multivibrator

 The length of the time that the output remains HIGH is the time for the capacitor to charge
from 1/3 VCC to 2/3 VCC. It is calculated as follows
 The capacitor voltage for a low pass RC circuit for a step input of VCC volts is given by

1.7

 The time t1 taken by the circuit to charge from 0 to (2/3) VCC is

1.8

By solving above equation

 The time t2 to charge from 0 to 1/3 VCC is

1.9

1.10

 The time to charge from 1/3 VCC to 2/3 VCC is

1.11

 For the given circuit,

1.12

 The output is low while the capacitor discharges form 2/3 VCC to 1/3 VCC and the voltage
across the capacitor is given by

1.13

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  Solving =
 Both RA and RB are in charging path and RB is in discharging path
 Therefore total Time

1.14

1.15

1.16

 The Duty cycle (D) of a circuit is defined as ratio of ON time to the total time period T. In the
circuit, when the transistor Q1 is On, the output goes low. Therefore

1.17

8.5. 555 Timer as Schmitt Trigger

 The two internal comparators are connected together through resistors R 1 and R2 with a
supply voltage of VCC/2. The upper comparator will trip at voltage of 2/3 V CC and lower
comparator will trip at 1/3 VCC. 555 Timer in Schmitt Trif=gger mode is shown in Figure 1.9.
 When a sine wave of sufficient amplitude(>
 The input and output waveforms of Schmitt trigger is shown in Figure 1.10
 In Schmitt trigger, frequency of square wave is equal to input signal frequency

Figure 1.9 : 555 Timer as a Schmitt Trigger

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 Figure 1.10: Input and output waveforms
8.6 Phase Locked Loop (PLL)
The Phase Locked loop (PLL) is an important building block of linear systems. PLLs are
available ass inexpensive monolithic ICs. Electronic frequency control is used today in satellite
communications systems, air borne navigation systems, FM communication systems, Computers
etc.

8.6.1 Block Schematic of PLL

 The PLL consists of i) Phase detector ii) Low Pass Filter (LPF) iii) Error Amplifier iv)
Voltage Controlled Oscillator (VCO).
 The VCO is a free running multivibrator generates a frequency free running Frequency
(f0). This frequency is determined by external timing resistor and capacitor.
 The free running frequency can be shifted to either side by applying a dc controlled
voltage vc, hence it is called as Voltage Controlled Oscillator.
 If input signal vs of frequency fs is applied to the PLL, the phase detector compares the
phase and frequency of the incoming signal to that of the output v0 of the VCO. If the
two signals differ in frequency or phase, an error voltage v e is generated. The block
schematic of PLL is shown in Figure 1.11.

Figure 1.11 : Block Schematic of PLL

 The phase detector is basically a multiplier and produces the sum (fs + fo) and difference
(fs - fo) components at its output. The high frequency component (fs + fo) is removed by
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 the low pass filter and the difference frequency component is amplified then applied as
control voltage vc to VCO.
 The signal vc shifts the VCO frequency in a direction to reduce the frequency difference
between fs and fo. Once this action starts, we say that the signal is in the capture range.
 The VCO continues to change frequency till its output frequency is exactly the same as
the input signal frequency. The circuit is then said to be locked. Once locked, the output
frequency fo of VCO is identical to fs except for a finite phase difference φ. This phase
difference φ generates a corrective control voltage vc to shift the VCO frequency from f0
to fs and thereby maintain the lock. Once locked, PLL tracks the frequency changes of
the input signal.
 Thus, a PLL goes through three stages
(i) free running,
(ii) capture and
(iii) locked or tracking.
 The output frequency of VCO is directly proportional to the dc level. The VCO
frequency is compared with input frequency and adjusted until it is equal to the input
frequencies.
 Before the input is applied, the PLL is in free running state. Once the input frequency is
applied the VCO frequency starts to change and PLL is said to be in the capture mode.
The VCO frequency continuous to change until it equals the input frequency and the
PLL is in phase lock mode.
 When Phase locked, the loop tracks any change in the input frequency through its
repetitive action. If an input signal vs of frequency fs is applied to the PLL, the phase
detector compares the phase and frequency of the incoming signal to that of the output
vo of the VCO.
Capture range: the range of frequencies over which the PLL can acquire lock with an
input signal is called the capture range. This parameter is also expressed as percentage of
fo.
Pull-in time: the total time taken by the PLL to establish lock is called pull-in time. This
depends on the initial phase and frequency difference between the two signals as well as
on the overall loop gain and loop filter characteristics.
8.7 Individual Blocks of PLL
PLL consists of Phase Detector, Low Pass Filter and voltage controlled oscillator.
a) Phase Detector:
 Phase detector compares the input frequency and VCO frequency and generates DC
voltage i.e., proportional to the phase difference between the two frequencies.
Depending on whether the analog/digital phase detector is used, the PLL is called either
an analog/digital type respectively. Even though most monolithic PLL integrated circuits
use analog phase detectors.
 Ex for Analog: Basic Analog Switch, Double-balanced mixer
Analog Phase Detector:
 The principle of analog Phase detector is to use switch type phase Detector. An
electronic switch S is opened and closed by signal coming form VCO (normally a square
wave) as shown in Figure (b).

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 Figure: Basic Analog Switch Phase Detector

Figure : (b) VCO output waveform, Input and output waveforms of phase Detector (C) =0 (d)
=90 (e) =180
 Figure (c) shows the input signal vs assumed to be in phase (=00) with VCO output
v0.Since the switch S is closed only when the VCO output is positive, the output
waveform will be half sinusoids(shown hatched ). Similarly the output waveform for
(=900and =1800) is shown in Figures d and e. This type of phase detector is called
Half wave detector . it may be seen that error voltage is zero when the phase shift
between the two inputs is 900. So for perfect lock, the VCO output should be 90 0 out of
phase with respect to input signal.
 Ex for Digital: Ex-OR, Edge trigger, monolithic Phase detector.
Digital Phase Detector:
 The below figure shows Digital type X-OR(Exclusive OR) phase detector.

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 Figure; Exclusive OR phase detector

Figure: Input and output waveforms

 It uses CMOS type 4070 Quad 2-input XOR gate. The output of the XOR gate is High
when only one of the input signals fs or f0 is High. This type of detecot is used when both
the input signals are square waves. The input and output waveforms are shown in Figure
(b) where fs is leading f0 by  degrees. The variation of dc output voltage with phase
difference  is shown in Figure C, where the maximum dc output voltafe occurs when
the phase difference is 1800.
 Edge Triggered Phase Detector: Advantages of Edge Triggered Phase Detector over
Ex-OR are
i) The dc output voltage is linear over 2Π radians or 360 degrees, but in Ex-OR it is Π
radians or 180 degrees.
 ii) Better Capture, tracking & locking characteristics.
 Edge triggered type of phase detector using RS Flip – Flop. It is formed from a pair of
cross coupled NOR gates. RS FF is triggered, i.e, the output of the detector changes its
logic state on the positive edge of the inputs fIN & Fout

Monolithic Phase detector:

 It consists of 2 digital phase detector, a charge pump and an amplifier.

 Phase detector 1 is used in applications that require zero frequency and phase difference
at lock.

 Phase detector 2, if quadrature lock is desired, when detector 1 is used in the main loop,
detector can also be used to indicate whether the main loop is in lock or out of lock.
(b) Low Pass Filter
 The filter used in PLL may be either passive type as shown in Figure 1.12, 1.13 or active
type shown in Figure 1.14. The function of the LPF is to remove the high frequency
components in the output of the phase detector and to remove the high frequency noise.
LPF controls the dynamic characteristics of the phase locked loop. i.e, capture range,
lock ranges, bandwidth and transient response.

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 Figure 1.12: Low pass Filter

Figure 1.13: Passive Filter

Figure 1.14: Active Filter

 If Filter Bandwidth is reduced, its response time increases. However reduced Bandwidth
reduces the capture range of the PLL. Reduced Bandwidth helps to keep the loop in lock
through momentary losses of signal and also minimizes noise
 Charge on the capacitor filter serves as a short time memory to PLL.
 Thus, even if the signal becomes less than the noise for a few cycles, the dc voltage on
the capacitor continues to shift the frequency of the VCO till it picks up signal again.
This produces a high noise immunity and locking stability.
 Lock Range (Tracking Range)
The lock range is defined as the range of frequencies over which the PLL
system follows the changes in the input frequency fIN.
 Capture Range
Capture range is the frequency range in which the PLL acquire phase lock. Capture
range is always smaller than the lock range.

(C) Voltage Controlled Oscillator

 The third section of PLL is the VCO; it generates an output frequency that is directly
proportional to its input voltage. The maximum output frequency of NE/SE 566 is 500
Khz.
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  A common type of VCO available in IC form is Signetics NE/SE566. The pin
configuration and basic block diagram of 566 VCO are shown in figure 1.15 and pin
diagram is shown in Figure 1.16

Figure 1.15: Voltage Controlled Oscillator

Figure 1.16: Voltage Controlled Oscillator

Figure 1.17: Block Diagram of Voltage Controlled Oscillator

 Referring to the circuit in the above figure 1.17, the capacitor CT is linearly charged or
discharged by a constant current source/sink. The amount of current can be controlled by
changing the voltage vC applied at the modulating input (pin 5) or by changing the
timing resistor RT external to the IC chip.
 The voltage at pin 6 is held at the same voltage as pin 5. Thus, if the modulating voltage
at pin 5 is increased, the voltage at pin 6 also increases, resulting in less voltage across
RT and thereby decreasing the charging current.

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  The voltage across the capacitor CT is applied to the inverting input terminal of Schmitt
trigger via buffer amplifier A1. The output voltage swing of the Schmitt trigger is
designed to Vcc and 0.5Vcc. If Ra = Rb in the positive feedback loop, the voltage at the
non-inverting input terminal of Schmitt trigger A2 swings from 0.5 Vcc to 0.25 Vcc.
 When the voltage on the capacitor c1 exceeds 0.5 Vcc during charging, the output of the
Schmitt trigger goes LOW (0.5 Vcc). The capacitor now discharges and when it is at
0.25 Vcc, the output of Schmitt trigger goes HIGH (Vcc). Since the source and sink
currents are equal, capacitor charges and discharges for the same amount of time. This
gives a triangular voltage waveform across CT which is also available at pin 4.
 The square wave output of the Schmitt trigger is inverted by inverter A3 and at pin 3. The
inverter A3 is basically a current amplifier used to drive the load. The output waveforms
are shown in Figure 1.18.

Figure 1.18: Output waveforms

 The output frequency of the VCO can be calculated as follows

1.18

1.19

1.20

 The time period T of the triangular waveform=2 ∆t. The frequency of the oscillator f0 is
1.21

1.22

 Where vC is the voltage at pin 5. Therefore

1.23

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  The output frequency of the VCO can be changed either by (i) R T, (ii) CT or (iii) the
voltage vc at the modulating input terminal pin 5 . The voltage v c can be varied by
connecting a R1R2 circuit as shown in Figure D.
 The components RT and CT are first selected, so that VCO output frequency lies in the
centre of the operating frequency range.
 Now the modulating input voltage is usually varied from 0.75 V CC to VCC which can
produce frequency variation of about 10 to 1.
 Wit no modulating input voltage, if the voltage at pin 5 is biased at (7/8) V CC. Equation
1.24 gives the VCO output frequency as

1.24
Voltage to Frequency Conversion Factor

 A parameter of importance for VCO is voltage to frequency conversion factor K V and is

defined as

1.25

 Here ∆vc is the modulating voltage required to produce the frequency shift ∆f 0 for a
VCO. if the original frequency is f0 and the new frequency is f1, then
1.26

1.27

 Putting the value of CTRT from equation ()

1.28

1.29

Applications of VCO
A VCO used in converting low frequency signals such as EEG, EKG into an audio frequency
range. These audio signals transmitted over telephone lines or a two way radio communication
system.
Monolithic Phase Locked Loop
 565 is available as 14 pin DIP package and as 10-pin metal can package.
 The pin configuration and the block diagram shown in Figures 1.19 (a and b).

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 Figure 1.19(a): NE/SE 565 PLL Pin Diagram

Figure 1.19 (b): NE/SE 565 PLL Block Diagram

 The output frequency of the VCO( both inputs 2,3 grounded) is represented in equation
(1.30).
1.30

Where RT and CT aare the external resistor and capacitor connected to pin 8 and pin 9.
A value 2 KΩ and 20 KΩ is recommended for RT.
The VCO free running frequency is adjusted with R T and CT to be at the centre of the
input frequency range.
 Phase Locked loop is internally broken between the VCO output and the phase
comparator input.
 A short circuit between pins 4 and 5 connects the VCO output to the phase comparator
so as to compare f0 with input signal fs.
 A capacitor C is connected between pin 7 and pin 10 to make a low pass filter with
internal resistance.
Applications of PLL

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 The output of PLL can be obtained as either voltage signal v c(t) corresponding to the error
voltage in the feedback loop , (or) as frequency signal at VCO output terminal. The output
voltage is used in frequency discriminator applications whereas the frequency output is used in
signal conditioning. The applications of PLL are
1. Frequency Multiplication/Division
2. Frequency Translation
3. AM Detection
4. FM Demodulation
5. Frequency Shift keying modulator
1. Frequency Multiplication/ Division
The below figure shows the block diagram of frequency multiplier using PLL. A divide by N
network is inserted between the VCO output and phase comparator input. In the locked state ,
VCO output frequency f0 is given by
f0=nfs

The multiplication factor is obtained by selecting a proper scaling factor N of

the counter. If the input signal is rich in harmonics eg: square wave then VCO can be directly
locked to the nth harmonic of the input signal. Typically the value of n is kept less than 10. The
circuit is used for division by locking the m-th harmonic of the VCO output with the input signal
fs. The output of VCO i.e f0 is given by
f0=fs/m
2. Frequency Translation
A mixer or (multiplier) and a low pass filter are connected externally to the PLL. The signal f s
which has to be shifted and the output frequency f 0 of the VCO are applied as inputs to the
mixer.

Figure: PLL used as Frequency Translator

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 The output of the mixer contains sum and difference of f s and f0. However the output of LPF
contains only the difference signal (f0-fs). The offset or translation frequency f1(<<fs) is applied to
the phase comparator. When PLL is in locked state,
f0- fs= f1

f0= fs+ f1
3. AM Detection
A PLL is used to demodulate AM signals as shown in figure . The PLL is locked to the carrier
frequency of the incoming AM signal. The output of VCO which has same frequency as the
carrier but unmodulated is sent to the multiplier.

Figure ; PLL used as AM Demodulator

Since the VCO output is always 900 out of phase with the incoming AM signal under the locked
condition, the AM signal is also shifted in phase by 90 0 before sent to the multiplier.. therefore
both signals applied to multiplier are in same phase. The output of multiplier contains both sum
and difference of signals, the demodulated output is obtained after filtering high frequency
components by LPF.
4. FM Demodulation
If PLL is locked to FM signal, the VCO tracks the instantaneous frequency of the input signal.
The filtered error voltage which controls the VCO and maintains lock with the input signal is the
demodulated FM output.
5. Frequency Shift Keying Demodulator
Binary data transmission is transmitted by means of a carrier frequency which is shifted between
two preset frequencies is called Frequency Shift Keying(FSK) Technique. The binary data can
be retrieved using a FSK demodulator at the receiving end. As the signal appears at the input ,
the loop locks to the input frequency and tracks it between the two frequencies with a
corresponding dc shift at the output. A three stage filter removes carrier component and the
output signal is digital data obtained by passing through a comparator.

8.8 BASIC DAC TECHNIQUES

The basic Digital to Analog Converter (DAC) is shown in Figure 1.20 The input
signal is a n-bit binary word D. The input is an n-bit binary word D and is
combined with a reference voltage V R to give an analog output signal. The
output of a DAC can be either a voltage or current.

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 Figure 1.20: Schematic of DAC
For a voltage DAC, the DAC is mathematically described as V 0 given
by,

Where V0=output voltage

VFS=Full scale output voltage
K=scaling factor
d1,d2,d3,-------dn=n-bit fractional word
d1=Most significant bit (MSB) with a weight of VFS/2
dn=Least significant bit(LSB) with a weight of VFS/2n

8.8.1 Weighted Resistor DAC

 The simplest Digital to Analog converter is shown in Figure 1.21.
 It uses a summing amplifier with a binary weighted resistor network
 It has n-electronic switches d1,d2,----dn controlled by input word.
 If the binary input to a specific switch is ‘1’, it connects resistance to a reference voltage
(-VR)
 If the input bit is’0’, the switch connects the resistance to ground. A simple weighted
resistor DAC is shown in Figure .

Figure 1.21: Weighted Resistor DAC

 The output current IO from the op-amp is written as

 The output voltage from weighted resistor DAC is represented in equation

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  The analog output voltage is a positive stair case which is shown in Figure 8.

Figure 1.22: Transfer characteristics of 3-bit DAC

 The accuracy and stability of DAC depends on accuracy of resistors
 The main disadvantage of this weighted resistor DAC is wide range of resistor values are
required. For 8-bit DAC ,it requires 20 R, 21 R,-----27 R. The fabrication of large
resistance in ICS also not practical is number of bits increases.

8.8.2 R-2R Ladder DAC

 Wide range of resistors is avoided by using R-2R ladder type DAC, where only two
values of resistors are required. The typical values of R range from 2.5 KΩ to 10 KΩ.
 Consider a 3-bit DAC shown in Figure (a), where the switch position d 1d2d3 corresponds
to a binary word 100.
 The circuit can be simplified to equivalent figure in (b) and (c)

Figure 1.23(a): R-2R ladder DAC

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 Figure 1.23(b): Equivalent circuit of (a)

Figure 1.23(c): Equivalent Circuit of (b)

 The output voltage for the inverting amplifier is

 Here Rf=2R, R=R and Vi=voltage at node C from the figure . The voltage at node C
with respect to ground is

 The output voltage is V0 =

 Similarly switches corresponding to a binary word 001 (3 bit DAC) is shown in Figure
1.24.

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 Figure 1.24: R-2R ladder DAC for input binary word 001

 The voltages at nodes A,B,C are calculated and the output voltage for an inverting
amplifier with an input voltage of (-1/16) VR is

8.8.3. Inverted R-2R Ladder DAC

 When the input data changes, current flowing in the resistors changes in weighted
resistor DAC and R-2R ladder DAC.
 As the current increases leads to more power dissipation causes heating in the
circuit which in turn creates non-linearity in DAC.
 This problem is eliminated in Inverted R-2R Ladder DAC. 3-bit (100) inverted R-2R
ladder DAC is shown in Figure , where the position of MSB and LSB are interchanged
compared with R-2R ladder DAC.
 Each input binary word connects the corresponding switch either to ground or to the
inverting terminal of op-amp( The inverting terminal also at virtual ground position).
 Since both inverting and non-inverting terminals are at ground potential, current flowing
in the resistance is constant and independent of switch position, i.e independent of input
binary word.

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 Figure 1.25: (a) Inverted R-2R ladder DAC (b) Equivalent Circuit for 100 binary word
 From Figure 1.25(a), When switch d i is at logical ‘0’ i.e to the left, the current through
2R resistor flows to ground and when switch is at logical’1’i.e to the right, the current
through 2R sinks to the virtual ground.
 The equivalent resistance to the left or right of any node is exactly 2R, the current
divides equally at each of the nodes..
 The division of current is shown in Figure 1.25(b).At node ‘A’, 2 mA of current divides
equally to value 1 mA due to equivalent resistor is 2R.
 At node B, 1 mA of current divides into 0.5 mA, similarly at node ‘C’, 0.5 mA of
current divides into 0.25 mA at node C.
 Therefore, irrespective of input binary data, current remains same in each branch of
ladder.
 Due to constant current, ladder node voltage remains constant at VR/20, VR/21, VR/22.
 Inverted R-2R ladder is said to be operate in current mode, since it works on the
principle of summing currents.

 From Figure (a), output voltage is written as

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 Where

, ,

 Advantages of Inverted R-2R Ladder(Current-Mode)

 Since the ladder node voltage remains constant even with changing input binary word,
stray capacitances does not produce slow down effects and will not affect the
performance of the circuit.
8.8.4 Monolithic DAC :1408 DAC
 Monolithic DAC 1408 is an 8-bit DAC consists of R-2R ladder, feedback resistor and
switches. It is compatible with TTL and CMOS logic.
 It consists of 8 data input lines with d 1 as MSB and d8 as LSB bit and Monolithic DAC
for unipolar range is shown in Figure 1.26(a).
 It requires 2 mA reference current for full scale input and with two power supplies +VCC
(+5 V) and -VEE(-5 V to -15 V).
 Resistors R14 and R15 is equal to match the input impedance of the reference source.
 The total reference current is determined by voltage reference V R and resistor R14= VR/
R14=5 V/2.5 KΩ=2 mA.

Figure 1.26(a): 1408 D/A Converter output voltage in unipolar range

 The total output current I0 is calculated as

 For Full scale input (i.e. d1 to d8=1)

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  The output voltage V0 is written as

 In general, the output voltage V0 is given by

 1408 DAC can be used for bipolar range from -5 V to +5 V by adding resistor R B (5 kΩ)
between VR and the output pin 4 as shown in Figure 1.26 (b).

Figure 1.26(b):1408 D/A Converter output voltage in bipolar range

 Since the resistor RB supplies 1 mA of current (V R/RB=5 V/5 kΩ) to the output in the
opposite direction of current generated by input signal. Therefore the output current for
bipolar operation is

 For zero input binary input word=00000000,the output voltage becomes

 For binary input word=10000000, output voltage is written as

 For binary input word=11111111, output V0 becomes

8.9 Analog to Digital Converters (A-D Converters)

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 It accepts analog input voltage V a and produces an output binary word d 1d2----dn with a
function of D shown in Figure 1.27 and the final output is represented in equation 1.31 .Where
d1 is the Most Significant Bit and dn is the least significant Bit.
D=d12-1+ d22-2+-----------+dn2-n (1.31)

Figure 1.27: Functional Diagram of ADC

The ADC has two additional control lines

a) START: This input tells the ADC when to start the conversion
b) EOC: End of conversion – It indicates conversion is complete
ADC’s are classified into two types: Direct type ADC and Integrating type ADC
Direct type ADC compares a given analog signal with the internally generated equivalent signal.
Direct Type ADC include
 Flash ADC(Parallel Comparator ADC)
 Counter type ADC
 Tracking or Servo Converter
 Successive approximation type Converter
Integrating type ADC performs conversion in an indirect manner by first changing the analog
input signal to a linear function of time or frequency then it converts into a digital code. The two
types of integrating ADC are:
 Charge Balancing ADC
 Dual Slope ADC

8.9.1 Parallel Comparator ADC (Flash ADC)

 Parallel comparator is simplest, fastest and expensive converter
 A 3-bit A/D converter is shown in Figure 1.28(a) .The circuit consists of resistive divider
network, 8 op-amp comparators and a 8 line to 3 line encoder. The comparator logic and
truth table is shown in Figures 1.28 (b) and (c)

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 Figure 1.28 (a): Basic circuit of parallel comparator type ADC

Figure 1.28 (b): comparator Logic

Figure 1.28 (C): Truth table of Flash type ADC

 Since all the resistors are of equal value, the voltage levels at the nodes are equally
divided between the reference voltage VR and ground.

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  The purpose of comparator is to compare the analog input voltage V a with each of the
node voltages and produces an output either 1(or)0(or) previous value.
 Conversion time depends on speed of the comparator and priority encoder and
conversion delay can be reduced to 20 ns by using Advanced Micro Devices (AMD)
comparator and T1147 priority encoder.
 The number of comparators required for n-bit ADC is 2n-1,where ‘n’ is the desired
number of bits.
Advantages:
 The speed of analog to digital conversion is high as the conversion takes place
simultaneously rather than sequentially
Disadvantages
 The number of comparators required almost doubles for each added bit
 For 2-bit ADC, 3 comparators are required and for 3-bit ADC, 7 comparators
 Larger the value of ‘n’, more complex is the priority encoder.

8.9.2 Counter Type ADC (Flash ADC)

 Digital to Analog converter (DAC) can be inverted into Analog to Digital converter
(ADC). The main principle is to adjust the DAC’s input code until the DAC output
comes within ±(1/2) LSB to analog input signal Va which is to be converted into digital
form
 Therefore, an additional logic circuit required to perform code search and comparator
required to announce the Final DAC output come within ±(1/2) LSB to Va in addition to
DAC circuit.
 A 3 bit counting type ADC is shown in Figure 1.29.
 The counter is reset to zero. The counter is reset to zero count by the reset pulse. Upon
the release of RESET, the clock pulses will be counted by the binary counter. The pulses
go through the AND gate which is enabled by the comparator high output.

Figure 1.29(a): A counter type A/D converter

 The number of pulses counted increases with time. The binary word representing this
count is used as input of a D/A converter whose output is a stair case shown in Figure
1.29(b).

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 Figure 1.29(b): output staircase waveform

 The analog input Vd of DAC is compared to the analog input Va by the comparator.
 If Va> Vd, the output of the comparator becomes High and the AND gate is enabled to
allow the transmission of the clock pulses to the counter.
 When Va< Vd, the output of the comparator becomes low and the AND gate is disabled.
This stops the counting at the time when V a< =Vd and the digital output of the counter
represents the analog input voltage Va.
 For a new value of analog input Va, a second reset pulse is applied to clear the counter.
 Upon the end of the RESET, the counting begins again as shown in Figure 1.29(b).
 The counter frequency must be low enough to give sufficient time for the DAC to settle
and for the comparator to respond.
Drawback
 Low sped is the most serious drawback
 The conversion time can be as long as (2 n-1) clock periods depending upon the
magnitude of input voltage Va.
Note:
 If the analog input voltage varies with time, the input signal is sampled, using a sample
and hold circuit before it is applied to the comparator.
 If the maximum value of analog voltage is represented by n-pulses and if the clock
period is T seconds, the minimum interval between the samples is nT seconds.

8.9.3 Successive Approximation ADC

 This ADC uses a very efficient code search strategy to complete n-bit conversion in just
n-clock periods.
 An eight bit converter would require eight clock pulses to obtain a digital output.
 The circuit uses a Successive Approximation Register (SAR) to find the required value
of each bit by trial and error. The circuit operates as follows.

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 Figure 1.30(a): Block Diagram of Successive approximation ADC
 Figure 1.30 shows an 8-bit converter. The circuit uses a Successive Approximation
Register (SAR) to find the required value of each bit by trial and error. The conversion
sequence is shown in Figure 1.30(b). The associated waveforms shown in Figure 1.30(c).

Figure 1.30(b): Successive approximation conversion sequence for input

 With the arrival of START command, the SAR sets the MSB d1=1 with all other bits to
zero so that the trial code is 10000000.
 The output Vd of the DAC is now compared with analog input Va.
 If Va is greater than the DAC output V d then 10000000 is less than the correct digital
representation.
 The MSB is left at ‘1’ and the next LSB is made ‘1’ and further tested.
 However, if Va is less than the DAC output, then 10000000 is greater than the correct
digital representation. So, reset MSB to ‘0’ and go on to the next LSB. This procedure is
repeated for all subsequent bits, one at a time, until all bit positions have been tested.
 Whenever the DAC output crosses V a, the comparator changes state and this can be
taken as the end of conversion (EOC) command.
 It can be seen that the D/A output voltage becomes successively closer to the actual
analog input voltage.

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  It requires 8 pulses to establish the accurate output regardless of the value of analog
input.
 However, one additional clock pulse is used to load the output register and reinitialize
the circuit.

Figure 1.30(c): D/A output voltage closer to actual analog input voltage

8.3.4 Dual Slope ADC

 The figure 1.31shows the functional diagram of the dual slope or dual ramp converter.
 The analog part of the circuit consists of a high input impedance buffer A1, precision
integrator A2 and a voltage comparator.
 The converter first integrates the analog input signal Va for a fixed duration of 2n clocks
as shown in fig 1.31. then it integrates an internal reference voltage VR of opposite
polarity until the integrator output is zero. The number N of clock cycles required to
return the integrator to zero is proportional to the value of Va averaged over the
integration period.

Figure 1.31 (a): Functional Diagram of Dual slope ADC

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 Figure 1.31(b): Integrated output waveform of Dual slope ADC

 Hence N represents the desired output code.

 Before the START command arrives, the switch SW1 is connected to ground and SW2
is closed.
 Any offset voltage present in the A1, A2, comparator loop after integration, appears
across the capacitor CAZ till the threshold of the comparator is achieved.
 The capacitor CAZ thus provides automatic compensation for the input offset voltages of
all the three amplifiers.
 Later, when SW2 opens, CAZ acts as a memory to hold the voltage required to keep the
offset nulled.
 At the arrival of the START command at t=t1, the control logic opens SW2 and connects
SW1 to Va and enables the counter starting from zero.
 The circuit uses an n-stage ripple counter and therefore the counter
resets to zero after counting 2n pulses. The analog voltage Va is integrated for a fixed
number 2n counts of clock pulses after which the counter resets to zero.
 If the clock period is T, the integration takes place for a time T1= 2n.T and the output is a
ramp going downwards as shown in fig. 1.31.
 The counter resets itself to zero at the end of the interval T1 and the switch SW1 is
connected to the reference voltage (-VR).
 The output voltage V0 will now have a positive slope. As long as V0 is negative, the
output of comparator is positive and the control logic allows the clock pulse to be
counted.
 However, when V0 becomes just zero at time t=t3, the control logic issues an end of
conversion (EOC) command and no further clock pulses enter the counter.
 It can be shown that the reading of counter at t3 is proportional to the analog input
voltage Va.
 From Figure (b)

and
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 For an integrator,

The voltage v0 will be equal to v1 at the instant time t2 and can be written as

The voltage v1 is given by

So,
Putting the values of and ,we get

The following important observations can be made:

 Since VR and n are constant, the analog voltage Va is proportional to the count reading
N and is independent of R, C and T.
 The dual slope ADC integrates the input signal for a fixed time, hence it provides
excellent noise rejection of ac signals whose periods are integral multiples of the
integration time T1.Thus ac noise superimposed on the input signal such as 50Hz power
line pick-up will be averaged during the input integration time. So choose clock period
T, so that 2nT is an exact integral multiple of the line period (1/50) second =20ms.
 The main disadvantage of the dual slope ADC is the long conversion time. For instance,
if 2n –T= 1/50 is used to reject line pick-up, the conversion time will be 20ms
Applications
 Dual slope converters are particularly suitable for accurate measurement of slowly
varying signals, such as thermocouples and weighing scales.
 Dual slope ADCs also form the basis of digital panel meters and multimeters.

1.10 DAC and ADC Specifications

Both DAC and ADC are avaialbe with various range of specifications. The important
specifications of converters analyzed by the manufacturers are:

1.10.1 Resolution
 The resolution of a converter is the smallest change in voltage which may be produced at
the output (or input) of the converter. For example 8-bit D/A converter has 2 8-1 =255
equal intervals.

Resolution= =1 LSB increment

 Similarly, the resolution for A to D converter is defined as smallest change in analog
input for a one bit change at the output.
1.10.2 Linearity

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  It is a measure of data converter accuracy which tells how close the converter output is
to its ideal transfer characteristics.
 Linearity error is the maximum deviation in step size from the ideal step size.

1.10.3 Monotonicity
 A monotonic DAC is the one whose analog output increases for an increase in digital
input.
 A monotonic characteristic is essential in control applications. Otherwise it may lead to
oscillations.
 If a DAC has to be monotonic, the error should be less than ± (1/2) LSB at each output
level.

1.10.4 Settling Time

 It is one of the important dynamic parameter.
 It represents the time it takes for the output to settle within a specified band ± (1/2) LSB
of its final value following a code change at the input (Usually a full-scale change).

1.10.5 Stability
 It is one of the important dynamic parameter.
 The ability of a DAC to produce a stable output all the time is called as Stability.
 The performance of a converter changes with drift in temperature, aging and power
supply variations.
 So, all the parameters such as offset, gain, linearity error & monotonicity may change
from the values specified in the datasheet. Temperature sensitivity defines the stability of
a D/A converter.
1.10.6 Conversion Time
 It is the time taken for the D/A converter to produce the analog output for the given
binary input signal.
 It depends on the response time of switches and the output of the Amplifier.
 D/A converters speed can be defined by this parameter.
Dynamic Range
 This is a measurement of the difference between the largest and smallest signals the
DAC can reproduce.
 It is expressed in decibels.

9. Practice Quiz

1. Which of the following is the specification of A/D converters?

a) Resolution
b) rectification
c) Conversion capacity
d) conversion ratio
2 The linearity error of DAC should be within

a) ±1/2 LSB

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 b) ±1/2 MSB
c) ± LSB
d) ± MSB
3. A low-speed ADC is ?
a) Successive-approximation
b) parallel comparator
c) dual-slope converter
d) change-balancing type
4. The main drawback of dual-slope ADC converters is
e) Long conversion time
f) high cost
g) Comparator and DAC are needed
h) Integrator and differentiator needed
5. The following is the disadvantage in binary weighted DAC.
a) Wide range of capacitors are require
b)design is complicated
c) Wide range of resistors are required
d) special type of op-amp is required
6. Which In R-2R ladder DAC, the typical values of resistor ’R’ ranges from

a) 2.5Ω to 10 Ω
b)2.5kΩ to 10k Ω
c) 25kΩ to 10k Ω
d)25Ω to 10 Ω
7. The fastest and expensive A/D converter is
a) Counter type
b)successive approximation
c) Flash type
d)servo converter
8. Which of the following is not a linear/digital IC?
a) Phase Locked Loop
b)Voltage Controlled Oscillator
c) Passive Filter
d)Comparator
9. The following is not the direct type ADC ?
a) Counter type
b)Dual slope
c) flash type
d)servo converter
10. The following is the integrating type ADC?
a) Counter type
b)Dual slope
c) flash type
d)servo converter
10.Assignments
S.No Question BL CO
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 Draw the internal schematic of IC 555. Configure it for astable operation and
1 2 1
explain the working.
2 Explain any three applications of 555 timer 2 1
Draw and explain the circuit diagram of R-2R ladder DAC and inverted R-2R
3 2 1
ladder DAC.
Explain the block schematic of PLL and explain about voltage controlled
4 2 1
oscillator in detail.
(I).What output voltage will be produced by a D/A converter whose output
range is 0 to 10 V and whose input binary number is:
(i) 10 (for 2-bit DAC)
5 (ii) 0110 (for 4-bit DAC) 3 1
(iii) 10111100 (for 8-bit DAC).
(II) Calculate the values of the LSB, MSB and full scale output for an 8-bit DAC for
the 0 to 10V.
6 Draw and explain the circuit diagram of Counter type ADC 3 1

11. Part A- Question & Answers

S.No Question & Answers BL CO

1 Define resolution of a converter
Ans. The resolution of a converter is the smallest change in
voltage which may be produced at the output or input
of the converter. Resolution (in volts)= VFS/2n-1=1 LSB 1 1
increment. The resolution of an ADC is defined as the
smallest change in analog input for a one bit change at
the output.
2 Define lock in range and capture range of PLL
Ans. The lock range is defined as the range of frequencies over
which the PLL system follows the changes in the input
1 1
frequency f IN.Capture range is the frequency range in
which the PLL acquire phase lock. Capture range is
always smaller than the lock range.
3 What are the advantages and disadvantages of Flash type ADC?
Ans. Advantages:
The speed of analog to digital conversion is high as the
conversion takes place simultaneously rather than
sequentially
1 1
Disadvantages
The number of comparators required almost doubles for
each added bit.For 2-bit ADC, 3 comparators are required
and for 3-bit ADC, 7 comparators. Larger the value of ‘n’,
more complex is the priority encoder.
4 Define Duty cycle?
Ans. The Duty cycle (D) of a circuit is defined as ratio of ON time 1 1
to the total time period T.
5 List out some applications of 555 Timer
Ans. Astable Multivibrator, Monostable Multivibrator, Missing
Pulse Detector, Linear Ramp Generator, Frequency 1 1
Divider,Pulse Width Modulation,FSK Generator, Pulse
Position Modulator, Schmitt Trigger

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 6 Which is the fastest ADC and why?
Ans.Flash or parallel comparator type ADC is the fastest because the speed
of analog to digital conversion is high as the conversion takes place 1 1
simultaneously rather than
sequentially
7 What are the types of ADC?
Ans. ADC’s are classified into two types: Direct type ADC and
Integrating type ADC
Direct type ADC compares a given analog signal withthe internally
generated equivalent signal. Direct Type ADC include
 Flash ADC(Parallel Comparator ADC)
 Counter type ADC
 Tracking or Servo Converter 1 1
 Successive approximation type Converter
Integrating type ADC performs conversion in an indirect manner
by first changing the analog input signal to a linear function of time
or frequency then it converts into a digital code. The two types of
integrating ADC are:
 Charge Balancing ADC
 Dual Slope ADC
8 What is settling time?
Ans. It is one of the important dynamic parameter. It represents
the time it takes for the output to settle within a specified 1 1
band ± (1/2) LSB of its final value following a code change
at the input (Usually a full-scale change).
9 What is a Voltage Controlled Oscillator?
Ans. The third section of PLL is the VCO; it generates an output
2 1
frequency that is directly proportional to its input voltage.
The maximum output frequency of NE/SE 566 is 500 Khz.
10 Define Conversion Time?
Ans. It is the time taken for the D/A converter to produce the
analog output for the given binary input signal. It depends 2 1
on the response time of switches and the output of the
Amplifier.

12. Part B- Questions

S.No Question BL CO
1 Explain working of weighted resistor DAC and draw transfer characteristics 1 5
of 3 bit DAC
2 Explain working of R- 2R ladder DAC 2 5

3 What output voltage will be produced by a D/A converter whose output 2 5

range is 0 to 10 V and whose input binary number is:
(i) 10 (for 2-bit DAC)
(ii) 0110 (for 4-bit DAC)
(iii) 10111100 (for 8-bit DAC).
4 Derive lock-in range and capture range of PLL with its neat block diagram 2 4
and its explanation
5 Draw the internal schematic of IC 555. Configure it for astable operation and 2 2
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 explain the working
6 Calculate the values of the LSB, MSB and full scale output for an 8-bit DAC 2 5
for the 0 to 10V.
7 List the applications of PLL and explain them 2 4
8 Explain inverted R-2R ladder. 2 5
9 Draw and explain the circuit diagram of dual slope ADC 2 5
10 With neat block diagram, explain successive approximation type A/D 2 5
converter in detail
11 Draw and explain the circuit diagram of parallel comparator type ADC 2 5
12 With the help of schematic diagram of 555 timer, explain how it can be used 2 2
as monostable multivibrator
13. Supportive Online Certification Courses
1. Integrated Circuits, MOSFETs, OpAmps and their Applications By Prof. Hardik Jeetendra
Pandyay, conducted by IISC Bangalore – 12 weeks
2. Basic Electronics By Prof. M.B.PATIL, , conducted by IIT Bombay – 12 weeks
3. Op-Amp Practical Applications: Design, Simulation And Implementation By Prof. Hardik
Jeetendra Pandyay, conducted by IISC Bangalore – 12 weeks

14. Real Time Applications

S.No Application CO
1 Build a Function Generator 1
To design and build a function generator capable of generating square wave and a
triangular wave of a known frequency using simulation and experiment by TI analog
system lab kit pro
2 DC Motor speed Controller 2
To design and Implement a speed controller of a DC motor using simulation and
experiment
3 4-bit R-2R DAC 5
Digital to Analog conversion for 4-bit data can be done by using R-2R ladder DAC
experimentally
4 2-bit Flash type ADC 5
Analog to Digital conversion done for 2-bit data using Flash type ADC technique
experimentally
15. Contents Beyond the Syllabus
1. Current IC Technology

Condition monitoring of critical machine tool components and machining processes is a key
factor to increase the availability of the machine tool and achieving a more robust machining
process Failures in the machining process and machine tool components may also have negative
effects on the final produced part. Instabilities in machining processes also shortens the life time
of the cutting edges and machine tool
2. Design and Fabrication of IC

A machine tool is a valuable piece of equipment for any small or large business. Cared for
properly, your machine can last for years, but if your machine tool is neglected, it can add up to
a number of costly machine tool repairs. If you want to extend the life of your equipment,
maintenance of Machine tools are very much essential.

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 16. Prescribed Text Books & Reference Books
Text Book
1. Op-Amps and Linear Integrated circuits – Ramakant A Gayakwad, 4th Edition
References:
1. Linear Integrated Circuit 2nd Edition – D. Roy Choudhary
17. Mini Project Suggestion
1. Water Level Indicator
It is a simple, automatic water-level controller for overhead tanks that
switches on/off the pump motor when water in the tank goes below/above the
minimum/maximum level. The water level is sensed by two floats to operate the
switches for controlling the pump motor. Each sensors float is suspended from
above using an aluminium rod. This arrangement is encased in a PVC pipe and
fixed vertically on the inside wall of the water tank. Such sensors are more
reliable than induction-type sensors. Sensor 1 senses the minimum water level,
while sensor 2 senses the maximum water level (see the figure).
2. DC Motor Speed Controller
DC Motor Speed Controller is a simple DC electric motor variable speed controller circuit that
can be configured to control the sweep rate of automobiles’ windscreen wipers. The circuit
comprises a timer NE555 (IC1), medium-power motor driver transistor BD239 (T1), high-power
switching transistor BD249 (T2) and a few other discrete components. It is configured for
automobile usage with the negative terminal of the power supply connected to the ground.

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