Pulse Width Modulation

Pulse width modulation (PWM) provides a way of controlling certain analog quan-
tities, by varying the pulse width of a fixed frequency rectangular waveform.

From: Fast and Effective Embedded Systems Design, 2012

Related terms:

Photovoltaics, Signal Modulation, Switching Frequency, Duty Cycle, Space Vector,

Waveform, Electric Potential, Inverter

View all Topics

Advanced PIC32 Projects

Dogan Ibrahim, in Designing Embedded Systems with 32-Bit PIC Microcontrollers
and MikroC, 2014

8.2 Project 8.2—Generating Pulse-Width Modulation Wave-

form

8.2.1 Project Description

Pulse-width modulation (PWM) is a powerful technique for controlling analog cir-
cuits with a microcontroller's digital outputs. PWM is used in many applications,
ranging from communications to power control and conversion. For example, the
PWM is commonly used to control the speed of electric motors, the brightness of
lights, in ultrasonic cleaning applications, and many more.

A PWM is basically a digital unipolar square wave signal where the duration of the
ON time can be adjusted (or modulated) as desired. This way the power delivered to
the load can be controlled from a microcontroller.

Figure 8.7 shows a typical PWM signal. The ON and the OFF times are sometimes
referred to as the MARK (or M) and SPACE (or S) times of the signal, respectively.
Here, we are interested in three parameters: signal amplitude, signal frequency (or
period), and the signal duty cycle.
Figure 8.7. A typical PWM signal.

The amplitude is usually fixed by the logic 1 level of the microcontroller output which
depends on the power supply voltage. In some applications, it may be necessary to
use external circuitry to increase the amplitude. In this project, we will be using the
output logic 1 level of the microcontroller which is +3.3 V.

The frequency depends on the application. In this project, we will generate a PWM
signal with a frequency of 40 kHz. This is the frequency commonly used in most
ultrasonic applications, such as distance measurement, ultrasonic cleaning, and so
on.

The duty cycle, denoted by D, is the ratio of the ON time to the period of the signal,
i.e. D = M/T. D can range from 0 to 1 and is sometimes expressed as a percentage,
i.e. from 0% to 100%. The power supplied to the load is controlled by varying the
duty cycle. Figure 8.8 shows signals with different duty cycles.

Figure 8.8. PWM signals with different duty cycles.

Many electronic circuits such as electric motors, solenoids, LEDs and so on average
the applied ON–OFF signal in their operation. The average voltage used by these
circuits can be expressed as follows:

 Vavg = D Von

where Von is the logic voltage level during the ON time. With a 3.3 V supply voltage,
the average voltage becomes

 Vavg = 3.3 × D

Thus, the average voltage supplied to the load is directly proportional to the duty
cycle of the PWM signal output by the microcontroller.
In this project, the duty cycle of the PWM waveform is configured to be 50%.

The block diagram of the project is shown in Figure 8.9.

Figure 8.9. Block diagram of the project.

8.2.2 Project Hardware

The circuit diagram of the project is shown in Figure 8.10. The PIC32MX460F512L
microcontroller has five pins named OC1, OC2, OC3, OC4 and OC5 that can be used
to generate PWM signal in hardware and independent of the CPU operations. Thus
the CPU can perform other tasks while the PWM signal has output continuously
from the microcontroller.
Figure 8.10. Circuit diagram of the project.

In this project, the 40 kHz PW1 signal is output from pin OC1 (or RD0, pin 72) of
the microcontroller.

If you are using the LV-32MX V6 development board, then the following jumper
must be set as follows:

 DIP switch SW20, jumper 8, set to ON

8.2.3 Project PDL

Before developing the PDL for this project, it is important to understand how the
project works.

The PWM module inside the PIC32 microcontroller uses a timer to control the signal
frequency and duty cycle. The period of the generated PWM signal is given by the
following:

 PWM Period = [(PR + 1) × TPB × (Timer prescaler value)]

where PR is the value loaded into the period register, and TPB is the clock period of the
peripheral clock. Assuming a peripheral clock frequency of 80 MHz, the peripheral
clock period is given by the following:

 TPB = 1/(80 × 10−6) = 0.0125 × 10−6 s
We are normally interested in finding the value to be loaded into the period register.
Assuming that we are using Timer 2 (Timer 1 cannot be used in PWM mode), the
value loaded into this register is calculated as follows:

Also,

 PWM frequency = 1/[PWM Period]

The PWM duty cycle is specified by writing to the OCxRS register. The maximum
PWM duty cycle resolution is calculated using the following formula:

where, FPB is the peripheral clock frequency, and FPWM is the clock frequency of the
PWM signal to be generated.

The specifications of this project are summarized below:

• Frequency of the PWM signal = 40 MHz (or, period = 0.025 × 10−3 s)

• Peripheral bus clock frequency = 80 MHz (or 0.0125 × 10−6 s)

• Timer to be used = Timer 2

• Timer 2 prescaler value = 1

• Duty cycle = 50%.

The value to be loaded into period register PR2 is calculated as follows:

The maximum PWM resolution is calculated as follows:

The steps for configuring the PWM module for the above specifications are given
below (notice that since we are using output pin OC1, the register OCxCON is the
register OC1CON):

• Calculate the PWM period (0.025 × 10−3)

• Calculate the PWM duty cycle (50%)

• Use Timer 2 in 16-bit mode

• Clear register OC1CON, bit 5 (OC32) for 16-bit operation

• Load PR2 with decimal 1999

• Load OC1RS low 16-bits with duty cycle (50% duty cycle corresponds to 1999/2
= decimal 1000)
• No interrupts required

• Set OCM bits of OC1CON to six to enable PWM mode of operation

• Select Timer 2 as the timer source

• Clear TCKPS bits of T2CON to set Timer 2 prescaler to 1

• Set bit ON of T2CON to enable Timer 2

• Set bit ON of OC1CON to enable OC1CON.

Figure 8.11 shows the PDL of this project.

Figure 8.11. PDL of the project.

8.2.4 Project Program

Figure 8.12 shows the program listing (called PWM.C). At the beginning of the
program pin OC1 (RD0) of the microcontroller is configured as an output pin. Then,
function CONFIGURE_PWM_MODULE is called to configure the OC1CON and the
TIMER 2 registers to generate the 40 kHz PWM wave with the 50% duty cycle. The
following code shows how the configuration is done:
 Figure 8.12. Program listing of the project.

void Configure_PWM_Module(void)

  T2CONbits.T32 = 0;               // Timer 2 in 16 bit mode

  OC1CONbits.OC32 = 0;             // 16 bit operation

  PR2 = 1999;                      // Load PR2

  OC1RS = 1000;                    // Load duty cycle

  OC1CONbits.OCM = 6;              // Enable PWM module

  OC1CONbits.OCTSEL = 0;           // TIMER 2 is the source

  T2CONbits.TCKPS = 0;             // Set Timer 2 prescaler = 1

  T2CONbits.ON = 1;                // Enable Timer 2

  OC1CONbits.ON = 1;               // Enable OC1CON

The rest of the main program consists of an endless loop where the PWM module
runs in the background.

Figure 8.13 shows the PWM waveform generated in this project.

Figure 8.13. The generated PWM waveform.

> Read full chapter

Power and Telemetry

Robert D. Christ, Robert L. WernliSr., in The ROV Manual (Second Edition), 2014

7.2.2.3 PWM control

Pulse width modulation (PWM) is a modulation technique that generates vari-
able-width pulses to represent the amplitude of an analog input signal. The output
switching transistor is on more of the time for a high-amplitude signal and off more
of the time for a low-amplitude signal. The digital nature (fully on or off ) of the PWM
circuit is less costly to fabricate than an analog circuit that does not drift over time.

PWM is widely used in ROV applications to control the speed of a DC motor and/or
the brightness of a lightbulb. For example, if the line were closed for 1 μs, opened for
1 μs, and continuously repeated, the target would receive an average of 50% of the
voltage and run at half speed or the bulb at half brightness. If the line were closed
for 1 μs and open for 3 μs, the target would receive an average of 25%.
There are other methods by which analog signals are modulated for motor control,
but OCROV and MSROV systems predominate with the PWM mode due to cost and
simplicity of design.

> Read full chapter

Direct power control of three-phase

PWM-rectifier with backstepping con-
trol
Arezki Fekik, ... Sundarapandian Vaidyanathan, in Backstepping Control of Nonlin-
ear Dynamical Systems, 2021

Abstract
Pulse Width Modulation (PWM) rectifiers belong to the best solutions to improve the
quality of electrical energy transfer from a source to a receiver. In fact, this chapter
proposes a method for regulating the three-phase PWM rectifier and ensuring
the elimination of total harmonic distortion to obtain a non-contaminated system
operating within a unity power factor. This regulation method is contracted via
analogy to the direct torque control (DTC) of an electrical machine. In place of the
torque and stator flux, active and reactive power are the corrected variables. That
work suggests the study of a direct power control (DPC) of a three-phase PWM
rectifier by deploying a backstepping for the correction of the DC bus voltage.
The assessment of the validity and dynamic performance of the control methods
was checked by simulation using MATLAB / SIMULINK environment under various
conditions, such as the variation of the reference voltage and the load. The results
of the simulation showed the robustness of direct power control based on the
backstepping control technique.

> Read full chapter

LEDs for large displays

Linas Svilainis, in Nitride Semiconductor Light-Emitting Diodes (LEDs) (Second
Edition), 2018

21.4.3 Driving the LED: pixel control

LED driving requirements significantly differ from other applications: (1) intensity
has to be regulated in very wide range to account the nonlinearity of the human
vision; (2) radiation stability has to be maintained over wide range of operation con-
ditions; (3) driving circuits must provide a luminance adjustment for white balance,
dot correction, tile correction, nighttime dimming purposes120; (4) spectral stability
has to be maintained; (5) control has to be accomplished in a cost-efficient way
and (6) energy efficiency is demanded.

The output stage structure divides the drivers into four categories: (1) switch output
with external current limiting resistors; (2) constant current output; (3) constant
current plus PWM output (programmable) and (4) complex drivers (using DC/DC
converter plus current feedback and PWM).

LED light is produced by the luminescence in a solid-state p-n junction diode when
forward bias voltage is applied.7,8 Fig. 21.40 represents a typical voltage-current
relationship of the LEDs used in LED video displays.

Figure 21.40. Voltage-current relationship of the JUNDUOLI SJ-E54DxR24VU-S

LEDs.

Forward current is small before forward voltage VF exceeds the internal barrier
voltage of LED. Increasing the forward voltage further, curve follows the shape of
a knee and rises rapidly at a linear rate. Forward voltage and other parameters are
specified at IF 20 mA; it is usually a nominal current for low-power diodes. Exceeding
the maximum specification of the manufacturer can seriously reduce useful life of
the LED. Forward current can be increased up to 100–200 mA if LED is operated in
pulsed mode. Few essential drawbacks can be seen from this graph: (1) LED forward
voltage is different for red (1.9–2.1 V depending on technology) and green and blue
(3.4–3.6 V); (2) power delivery to LED is highly nonlinear at low currents. Higher drive
currents (350 mA–1 A) are needed if power LEDs are used. Further problems can be
seen by analyzing the luminous intensity variation with forward current (Fig. 21.41).
Figure 21.41. Luminous intensity variation with forward current of the same LEDs.

LED light output is proportional to a forward current, but it is not exactly linear. If
a forward current is not controlled appropriately, it can result in an unacceptable
variation of light output.111 A challenge in designing the LED driver is to create a
stable, programmable, constant current source possessing high efficiency.110,121

Unfortunately, LED pixel intensity cannot be controlled using forward current be-
cause of several reasons: (1) color shift with forward current for green and blue; (2)
nonlinearity of human vision; (3) instability of LED emission and driver feedback
problems at very low currents; and (4) driving every LED by the analog source is
complicated.

Forward current affects the emission wavelength, influencing the chromaticity co-
ordinates of the display gamut.8 This is especially valid for InGaN, which is used in
blue and green LED production. Note the color triangle shift in Fig. 21.42 when LED
forward current is changed from 1 to 100 mA. Data was taken from Refs. 122–124.
Data for red uses the temperature effects in −30 to 85°C range.
Figure 21.42. Color gamut shift when LED current is changed from 1 to 100 mA.

It can be seen that green has the largest variation, while red is stable with current
and temperature. If current is varied only slightly, gamut can be considered stable.
Constant current adjustment can be used to provide a luminance adjustment, white
balance, dot correction or even to compensate for temperature effects.

Light output has to be varied over a very wide dynamic range. Nonlinearity of the
human sense of light43 requires gamma correction to decompress the image color
coding. 16-bit LED intensity coding (more than 80 dB) is required to avoid image
banding after gamma correction. LED output with current is nonlinear, as it can
be seen from Fig. 21.41. Furthermore, LED emission is not stable at low currents.
It is very complicated for the driver to provide the wide range of constant current.
Electromagnetic interference from neighboring LEDs driven at high current will
distort this very low current even if two aforementioned problems can be solved.
Driving the LED by the Pulse Width Modulation (PWM) of constant current solves
these problems: the linearity of LED output modulation can be maintained.117,119
Average power of the PWM is linearly proportional to the duration of the pulse (refer
to Fig. 21.43). Just the amount of the available duration steps limits the dimming
resolution. PWM is easy to implement with digital circuits; a steady drive over a
wide range of intensities can be ensured. Display image has to be blinking anyway
to avoid the flickering when motion picture is rendered on screen,94 so periodicity
of PWM is in synergy with this requirement.
Figure 21.43. PWM dimming time diagram.

The PWM drive has its own shortcomings:

1. The number of available steps is limited by the switching speed of the LED or
driver electronics and the required refresh frequency;
2. Constant current PWM has to be supplied to every individual LED on screen.
This both complicates the design and increases the cost of the display;
3. The time required to deliver this data to LED driver output limits the minimal
PWM pulse duration;
4. There is a moment when all LEDs are switched on (Fig. 21.42: the start of the
period) no matter what pixel intensities are; this will produce a large current
spike, rising an EMI issue;
5. Refresh rate has to be synchronized with the frame data, otherwise different
frame fragments will be displayed on screen when refresh cycle changes; a
good test for this phenomenon is the movie with interlaced black-and-white
frames;
6. Color shift occurs even in case of PWM drive125 due to temperature rise.

A range of PWM methods have been suggested for LED control (Fig. 21.44). Pulse
frequency modulation (PFM), Bit-angle modulation (BAM),126 binary PWM (BPWM),
gated PWM (GPWM),114 pulse frequency modulation, and pulse amplitude mod-
ulation,67,111 probability-based PWM127 and scrambled PWM (S-PWM)116 are just
a few candidates. PFM is basically same PWM, only in case of PWM the refresh
period is fixed and the pulse duration is varied; while PFM is the opposite: pulse
duration is fixed but refresh period is varied. PFM is rarely used in video displays
because image blinking at stable period is required to maintain the smooth motion
on screen. Binary-weighted PWM (BPWM), discrete PWM,119 or BAM126 dimming
technique uses different weight for the pulses in a period to form the required duty.
Refer Fig. 21.43 for conventional PWM and BPWM comparison. In BPWM, width
of each separate pulse is proportional to the weight of the bit in the corresponding
binary code, but the total pulse width is the same as for conventional PWM. Data
delivery to LED driver is serial (Fig. 21.34): the amount of the communication lines
is reduced18,113,114; every display controller can control large amount of LEDs5;
complexity and price of control electronics is reduced. Data is serially shifted out
of the controller in order to reach the LED. BPWM driving further simplifies the
system and reduces the amount of data upload cycles thanks to bitplanes (Fig. 21.44)
decoding (binary code of pixel grayscale can be used directly).

Figure 21.44. Transferring the image bitplanes to driver is direct with BPWM dim-
ming.

It is essential that BPWM also reduces the data flow: every time tick (1,2,3,4, and so
on), indicated in Fig. 21.45 requires an upload of new data for PWM driver; while
GPWM requires an upload of corresponding bitplanes, that is, on time tick 1,2,4,8,
and so on. BPWM (BAM) dimming will also reduce EMI by spreading current surge
spikes in time (compare PWM and BPWM waveforms in Fig. 21.45).

Figure 21.45. Waveforms of the most common PWM dimming techniques. PWM,

Pulse Width Modulation.
Unfortunately, both PWM and BPWM have the same limitation: the number of the
achievable grayscale levels, the refresh frequency, and number of serially controlled
LEDs are interrelated and limit each other. The problem lies in limited speed of
shift registers of LED drivers: clock speed is limited by technology and currently is
about 25–30 MHz. PWM refresh cycles can be subdivided into subframes (ticks). This
subframe data (“1” or “0”) shall be delivered to every LED driver by shifting serial
data through driver registers. The subframe loading time load required to shift-load
NREG channels of the LED driver at shifting clock frequency fCLK can be calculated as:

(21.19)

For instance, the shortest subframe duration will be 1280 ns for the 32-channel LED
driver, 3840 ns for the 96-channel LED driver, etc. Subframe loading time and a
required number of ticks in PWM period limits the minimum attainable period of
the PWM signal TPWM. Flicker occurs when changes in the display luminance occur
at the frequency below the integrating capability of the eye. For professional LED
screen application, 1000–400 Hz refresh frequency9 is used in order to match the
camera exposure time as it was indicated before. Then the number of the available
levels nPWM is defined by required PWM, image refresh period:

(21.20)

Data in Table 21.2 lists the attainable grayscale resolution in bits versus the number
of LEDs driven serially and PWM or image refresh frequency.

Table 21.2. Attainable PWM grayscale resolution versus the refresh frequency of the
frame and serially controlled LEDs in case of 30 MHz serial data clock frequency

PWM/image refresh frequency, Hz

50 100 240 400 1000
LEDs Grayscale resolution, bits
1 19 18 17 16 15
8 16 15 14 13 12
16 15 14 13 12 11
32 14 13 12 11 10
96 13 12 10 10 8
256 11 10 9 8 7

It must be noted that modern LED drivers have the OE signal which can be used for
output blanking. And the switching speed of the LED driver output is comparable to
the shifting speed: duration of the OE signal can be considerably shorter than the
duration required for loading the entire subframe data. GPWM technique proposed
in Ref. 114, explores this fact to significantly increase the number of gray levels and
image refresh frequency. Resolution is achieved without compromising the number
of serially controlled LED drivers. In GPWM LED is lit on just for a short duration
min (note the GPWM pulse duration in Fig. 21.45 and 21.46) during the data loading

operation instead of the shortest PWM duration defined by the frame data load time
load. This would correspond to replacing load used Eq. (21.20) by min. This way,

almost unlimited number of PWM levels can be achieved. Further performance gain
is achieved when bitplane loading as per BPWM is used.

Figure 21.46. Time diagrams of the GPWM dimming technique. GPWM, gated

binary-weighted PWM.

Actually there is a limit in GPWM speed. It is related to the shortest achievable LED
flash duration, which depends on LED response time and LED driver used. As noted
in Table 21.1, the best propagation delay for high and low level is 100 ns. Then
200 ns should be used as the minimum GPWM duration min. Studies in Refs. 9117
illustrated that the LEDs commonly used for video screens have response time below
100 ns. The amount of available bits NG,thanks to additional gating, is:

(21.21)

Remaining number of bits NM corresponds to what would be attainable if PWM or

BPWM techniques are used:

(21.22)

The total available bits are the sum of NG and NM. The attainable grayscale res-
olution of GPWM versus the number of LEDs driven serially and image refresh
frequency is presented in Table 21.3.

Table 21.3. Attainable GPWM grayscale resolution versus the refresh frequency and
serially controlled LEDs in case of 30 MHz serial data clock frequency

PWM/image refresh frequency, Hz

50 100 240 400 1000
LEDs Grayscale resolution, bits
1 19 18 17 16 15
8 17 16 15 14 13
16 17 16 15 14 13
32 17 16 15 14 13
96 17 16 15 14 13
256 17 16 15 14 13
4096 17 16 14 13 10

GPWM not only offers significant speed performance improvement as can be seen
by comparing Tables 21.2 and 21.3, but also has more flexibility in rounding of PWM
period, since better resolution of PWM cycle allows for two options. Because of
additional gating in GPWM the maximum available LED brightness is reduced. This
effect becomes significant only at high numbers: at 1000 Hz refresh frequency and
256 serially driven LEDs; 5% reduction in brightness is expected. Another GPWM
disadvantage is related to the fact that more on/off transitions of the LED are
implemented with GPWM (as well as with BPWM); therefore LED pulse driving skew
will affect it stronger than conventional PWM as indicated in Ref. 117.

It is worth reminding here that despite PWM drive, LED has to be driven by constant
current during on cycle. The simplest way of setting a current is to use a resistor in
series (Fig. 21.47).

Figure 21.47. Series resistor application for LED current control.

Current is set by Rset value and depends on supply voltage VDC and LED forward
voltage VF:

(21.23)

Circuit is simple, low cost, and produces no noise. LED can be turned on and off if
switch is added in the series. A switch driver is the simplest type: an output stage
usually is a saturated switch (typically, an open drain) connecting the output to the
ground. One external resistor per LED is added in order to set the LED current. Refer
to Fig. 21.48 for a simplified topology drawing.
Figure 21.48. Switch output driver topology.

High LED current can be used because switch operates in saturated mode. This
topology is quite old; application of a saturated switch does not allow for fast
switching times. It does not offer current accuracy and efficiency. Forward voltage
varies from LED to LED: −0.3 to +0.5 V for red; and −0.4 + 0.6 V for green and
blue, resulting in −20% to +10% current variation in case VDC is 5 V and −38%
to +23% current variation in case of 3.3 V power supply for red. Accuracy is low if
resistor voltage drop is low. Variation decreases if power supply voltage is larger, but
then large portion of energy is wasted as a heat on resistor Rset. More than 60%
of energy is dissipated on Rset for red and 30% for green and blue in case of 5 V
power supply. Closer examination of Fig. 21.40 can reveal that forward voltage VF is
changing with current. In addition to that, it also varies with temperature. Due to
the large amount9,128 of the LEDs powered, a power supply voltage will fluctuate as
well. Furthermore, the LED forward current is a function of temperature Tj, diode
forward voltage VF, and power supply voltage VDC.

A constant current (usually a current sink) output driver (Fig. 21.49) offers more
advantages.

Figure 21.49. LED current control using a constant current sink.

Constant current output driver (Fig. 21.50) topology is the most popular in LED
displays.129–133 The constant current is provided by individual regulated current
sinks. It allows for faster switching times as the output switch is not saturated.

Figure 21.50. Constant current output driver topology uses current mirror to set the
current. CLK, clock, LTD, latch signal, OE, output enable strobe, SDI, serial data in,
SDO, serial data out

The output current is usually set by a single external resistor for all outputs simul-
taneously. The resistor is connected to the driver's internal reference voltage source
(usually 1.2 V). Value of this resistor defines the reference current flowing from this
reference voltage source. This current is copied by a current mirror and multiplied
by a certain coefficient (usually 16), setting the driver's output current.

The major advantage of this driver type is that only 0.2–0.7 V driver dropout voltage
(depending on technology used) is usually sufficient. The required driver voltage
drop-out relation to the operating current of the LED driver IC can be rectified by
analyzing Fig. 21.51. Data was taken from MBI5045 datasheet (Macroblock Inc.).129

Figure 21.51. Driver output current versus drop-out voltage for MBI5045 from
Macroblock.

It can be seen that 0.2 V dropout voltage is sufficient for stable constant current
sink operation for 20 mA and below output currents, while higher currents might
need 0.4 V output voltage. This means that 2.7 V power supply is sufficient for red
LED (2 + 0.5 V VF) resulting in 75% LED drive efficiency. Best AC/DC power supply
efficiency for such low output voltage is about 75%,134 resulting in 56% wall-plug
drive efficiency. Efficiency would have been 48% in case of 3.3 V (79.5% for
AC/DC and 61% for LED drive).

LED drivers with internal PWM in addition to constant current drive (Fig. 21.52)
represents a new generation of intelligent drivers used to address the problem of
data delivery bottleneck. This type of driver combines the constant current output
with the individual PWM generators for every channel.135–140 PWM can be complex
type, like enhanced-spectrum PWM (ES-PWM)135 or S-PWM.116
Figure 21.52. Programmable LED constant current driver with the internal PWM.
PWM, Pulse Width Modulation.

Driver is quite efficient since usually 0.4–0.7 V output dropout voltage is sufficient
to maintain the sink current at the programmed level. The output current is set by
a single external resistor but the gain of the current mirror can be programmed
using same serial interface. This type of driver allows for significant reduction of
the data flow over driver IC. The current PWM dimming code can be loaded only
once per video frame. Internal PWM generator of the IC takes care of the refresh,
dimming, multiplexing (if any) functions. Larger number of internal registers is used
here different from previously discussed drivers. Internal registers are not only used
to store the PWM value but also to do the current correction, to adjust the tile
brightness to neighboring tiles, or to dim the whole display during the nighttime or
to provide the dot correction. Staggered delay of PWM output, scrambled PWM116
can be implemented to address the problem of large current pulse at the beginning
of the PWM cycle.

Even application of the low output voltage constant current output and internal
PWM does not solve the driving efficiency problem. LED display consumes
significant amounts of power. It is essential that LED is a low voltage device: the
forward voltage is 2 or 3.6 V depending on color and technology. Moderate 640 × 480
resolution and three LEDs per pixel display with a 20 mA current per LED requires
20 kA of total current. A macroblock of 64 × 48 pixels will need 180 A. Losses in power
distribution wires will occur when such currents have to be distributed. Furthermore,
efficiency of the AC/DC power supply decreases if the output voltage is low due
to rectification losses (0.5–1.5 V forward voltage drop of the rectifier). Synchronous
rectification reduces the problem but low efficiency for lower output voltage SMPS
remains.134 Higher LED driver power supply voltage would ease the problems.

Several solutions for power LED driving have already been proposed in lighting.141,142
Some automotive ICs dedicated are close to the required solution.142,143 Up to
eight channels buck is offered by Linear Technology.144 However, these drivers are
dedicated for high power LEDs, require external PWM source, require the external
analog voltage source for the LED current setting, and are complex and expensive.
Interesting LED driver solution (Fig. 21.53) was proposed in Ref. 9.

Figure 21.53. LED driver incorporating serial digital communication, local PWM

controller, and buck converter.9 PWM, Pulse Width Modulation.

It was proposed to incorporate floating point dimming in the driver using local
PWM controller with required gamma correction already be stored on the chip. The
majority of PWM control codes are thrown away in order to get an appropriate
gamma correction curve. Floating point coding would exploit the coding space
better. Incorporated buck converters solve the current stability problem thanks to
the current feedback. The cost of converter switches should be low thanks to low
output current. Such a driver could preserve the same serial control interface for
backward compatibility with older generation drivers. It is interesting to point out
that current delivery trace from the driver to LED is usually long and exhibits some
inductance. Usually this inductance creates unwanted oscillations. Floating buck
converter topology can incorporate this inductance into energy storage inductor
path. Efficiency is further increased if synchronous rectification and smart current
sensing technologies are used. Proposed topology also eases problem with large
current distribution: higher voltage can be used in distribution (in case of afore-
mentioned 180 A at 5 V distributed current can go down to 18 A at 50 V). Higher
efficiency mains input AC/DC converter can be used.

Color rendering quality depends on white balance: red, green, and blue luminance
ratios have to be 3:6:1.78 Chromaticity coordinates of white and RGB primaries define
the actual percentage. LED intensity binning can be used, but better idea is to match
the RGB intensities approximately and then adjust the driving current. Current
adjustment is not possible if limiting resistors are used for setting LED current, but
use of the internal reference voltage and current mirror in constant current output
driver allows current regulation. Refer Fig. 21.54 for possible topologies for current
adjustment.
Figure 21.54. Output current regulation using external resistor (left) or external
voltage (right).

The constant reference current is usually set by a single external resistor. The resistor
is connected to the driver's internal reference voltage source (usually 1.2 V). Value
of this resistor defines amount of the current flowing from this reference voltage
source (Fig. 21.54). The flowing current is copied by a current mirror and multiplied
by a certain coefficient K. This amplified current is used to set the driver's output
current. It must be pointed out that current is regulated in inverse proportion to
RREF value so RREF and Iout relation is nonlinear.

Problems occur when total output current adjustment145–149 of all the drivers located
on the tile PCB is required (Fig. 21.55). Usually, the tile incorporates 16 to 128
drivers. Drivers are grouped into groups for red, green, and blue LED. It is more
convenient when such R, G, or B group of 4–64 drivers has a common output current
adjustment. Reference resistors RREF can be grounded through a single additional
potentiometer, or they should be grounded into a regulated voltage source. In case
of a common resistor (Fig. 21.55), the reference current can be varied by regulating
the common resistor value.145,147,148

Figure 21.55. Common resistor application for simultaneous drivers' current adjust-

ment.

This method is low-priced, easily operated by an unskilled operator, but not suitable
for remote control by module controller. Reference current regulation149 by varying
the voltage difference between the internal reference and external regulated source is
suitable for remote control. DAC (Fig. 21.56) or filtered PWM output can serve as the
external regulated voltage source. Additional control circuit increases the complexity;
nonlinearity and current mismatch between drivers are growing when voltage levels
of external source is close to internal reference voltage.
Figure 21.56. External voltage source application for simultaneous drivers' current
adjustment.

Though more advanced techniques of internal current gain compensation have been
enrolling,136,150 simple LED display manufacturers still prefer to use the common
resistor method. Such simple control is not free of induction of errors that have
been reported in Ref. 114. The LED tile with 16 × 32 LEDs was examined for the
LED current errors induced by unaccounted currents on the PCB. Usually the tile
has a single potentiometer for red, green, and blue LEDs’ intensity adjustment. It
was found that placement of the common resistors involves the additional voltage
drop along the ground traces of the PCB. This influences LED forward current
set for driver. It was demonstrated that distance from the driver to the common
control potentiometer and current errors are correlated, the normalized cross-cor-
relation of 0.94 was obtained for red LED drivers, 0.96 and 0.7 for green and blue
correspondingly. Errors are relatively small: maximum 4.7% current deviation was
found. Programmable LED drivers116,136,150 have the ability to adjust the gain of the
reference current, so a software-adjustable driver is more immune to such type of
errors.

> Read full chapter

Multiphase Converters
Atif Iqbal, ... Kishore N. Mude, in Power Electronics Handbook (Fourth Edition), 2018

15.4.2.5 Space Vector Pulse Width Modulation

Space-vector pulse-width modulation has become one of the most popular PWM
techniques because of its easier digital implementation and higher DC bus utiliza-
tion, when compared with the sinusoidal PWM method. The principle of SVPWM
lies in the switching of inverter in a special way to apply a set of space vector for
specific time. There is a lot of flexibility available in choosing the proper space-vector
combination for an effective control of multiphase VSIs because of the large num-
bers of space vectors available in multiphase power converters.
Advantages of space vector PWM:
i. SVPWM increases fundamental output without distorting line-to-line wave-
form.
ii. The fundamental output of SVPWM is 94.02% that is 15.47% greater than
sinusoidal PWM of 78.55% fundamental.
iii. SVPWM compares a single modulating wave with a carrier instead of using
three waves.
iv. When the neutral of the load is connected to a DC supply voltage, SVPWM
considers interaction among phases, whereas other PWM method does not.
v. Designing of heat sinks is an important factor for power dissipation. Power
dissipation includes conduction and switching loss. Switching losses in sine
PWM is difficult to compute that depend on modulation index, while
computation is easier in space-vector PWM.
vi. SVPWM implementation is completely digital.

vii. Vector control implementation is completely digital, and thus, it is easy to

implement SVPWM-based vector control scheme.
viii. Over modulation can easily be implemented.

ix. For high modulation index, the harmonics of current and torque of space-vec-
tor PWM will be much less than sine PWM.

In the case of a five-phase VSI, there are a total of 25 = 32 space vectors available,
of which 30 are active state vectors and two are zero state vectors forming three
concentric decagons. For the implementation of space-vector PWM in linear range,
two different approaches can be adopted. One approach is the simple extension of
method used in a three-phase inverter (use of two adjacent large length vectors) and
second approach where four adjacent vectors are used (two large and two medium
lengths). The first approach gives higher output voltage; however, the output volt-
ages contain lower-order harmonics, more specifically, the third and seventh. The
second approach offers sinusoidal output voltage; however, the magnitude is lower.

The first approach used only 10 outer large length vectors to implement the sym-
metrical SVPWM. Two neighboring active space vectors and two zero space vectors
are utilized in one switching period to synthesize the input reference voltage. In total,
20 switchings take place in one switching period, so that the state of each switch is
changed twice. The switching is done in such a way that, in the first switching half
period, the first zero vector is applied, followed by two active state vectors and then
by the second zero state vector. The second switching half period is the mirror image
of the first one. The symmetrical SVPWM is achieved in this way. This method is the
simplest extension of space-vector modulation of three-phase VSIs.
An ideal SVPWM of a five-phase inverter should satisfy a number of requirements.
Firstly, in order to keep the switching frequency constant, each switch can change
state only twice in the switching period (once “on” to “off ” and once “off ” to “on” or
vice versa). Secondly, the rms value of the fundamental phase voltage of the output
must be equal to the rms of the reference space vector. Thirdly, the scheme must
provide full utilization of the available DC bus voltage. Finally, since the inverter
is aimed at supplying the load with sinusoidal voltages, the low-order harmonic
content needs to be minimized (this especially applies to the third and seventh
harmonic). These criteria are used in assessing the merits and demerits of various
SVPWM.

> Read full chapter

Parallel operation of power converters

and their filters
Ghanshyamsinh Gohil, in Control of Power Electronic Converters and Systems, 2021

14.5.2.2 Impact of the modulation scheme

The PWM scheme has a strong influence on the core losses. Therefore, the design
of the CI, especially the thermal design, is strongly impacted by the selection of the
PWM scheme. The impact of the PWM scheme on the core losses of the CI for two
parallel VSCs has been analyzed. By neglecting the leakage flux, the flux linkage in
the CI is given as

(14.72)

The differential voltage that appears across the CI () determines the flux linkage,
which entirely depends on the PWM scheme. The flux density in the CI can be
obtained as

(14.73)

where is the number of turns in a coil, and is the core cross-sectional area.

The variation in the peak flux linkage with the modulation index for different PWM
schemes is plotted in Fig. 14.23 [29]. The maximum value of the peak flux linkage
is the same in all PWM schemes. However, the flux linkage pattern is different. As
a result, the core losses would be different in each of the schemes, which is an
important factor in determining the size and efficiency of the CI. The impact
of the modulation schemes on the CI core losses is shown in Fig. 14.24. The core
losses are obtained using the improved generalized Steinmetz equation. The core
losses are normalized with respect to the core losses in the case of the SVM. When
compared to the SVM, all the discontinuous PWM schemes lead to lower core losses
at low modulation indices. For high modulation indices, the use of DPWM1 leads
to the highest losses, followed by DPWM2. The core losses in the case of DPWM3
are lowest in the entire modulation index range.

Figure 14.23. Variation of the maximum peak flux linkage with the modulation
index. The flux linkage is normalized with respect to the .

Figure 14.24. The core losses in the coupled inductor for different PWM schemes.
The core losses are normalized with respect to that of the SVM. The carrier frequency
is taken to be the same in all cases.

> Read full chapter

Reactive Power Plant and FACTS Con-

trollers
A Gavrilović OBE, ... DJ Young BA, in Electrical Engineer's Reference Book (Sixteenth
Edition), 2003

41.5.6.5 Pulse width modulation

Pulse width modulation (PWM) is an alternative method of harmonic control. The
power electronic switches are repetitively turned on and blocked several times during
each half cycle. The sequential switching instants are selected in a co-ordinated man-
ner, to satisfy simultaneous requirements, i.e. to develop the desired fundamental
voltage and to eliminate selected low order harmonics. Figure 41.21 illustrates how
two poles of a converter (such as that shown in Figure 41.17) can be controlled, each
with 5 on/off actions per cycle, to eliminate both 5th and 7th harmonics together.
Extra, correctly timed, switchings can eliminate additional higher harmonic compo-
nents. IGBTs and IGCTs require much lower switching energy than GTOs and are
better suited to applications that use PWM techniques. Multi-module arrangements
are necessary to obtain high ratings.

Figure 41.21. Pulse-width-modulated (PWM) converter voltage waveforms

> Read full chapter

Devices
Larry D. Pyeatt, William Ughetta, in ARM 64-Bit Assembly Language, 2020

11.3.2 Pulse width modulation

In pulse width modulation, the frequency of the pulses remains fixed, but the
duration of the positive pulse (the pulse width) is modulated. When using PWM
devices, the programmer typically sets the device cycle time in a register, then uses
another register to specify the number of base clock cycles, d, for which the output
should be high. The percentage is typically referred to as the duty cycle and d must be
chosen such that . For instance, if , then the device cycle time is 1024 times the cycle
time of the clock that drives the device. If , then the device will output a high signal
for 512 clock cycles, then output a low signal for 512 clock cycles. It will continue to
repeat this pattern of pulses until d is changed.

Fig. 11.6 shows a signal that is being sent using pulse width modulation. The pulses
are also shown. Each pulse transfers some energy to the device. The width of each
pulse determines how much energy is transferred. When the pulses arrive at the
device, they are effectively filtered using a low pass filter. The resulting received
signal is shown by the dashed line. As with PDM, the received signal has a delay,
or phase shift, caused by the low-pass filtering.

Figure 11.6. Pulse Width Modulation.

One advantage of PWM over PDM is that the digital circuit is not as complex.
Another advantage of PWM over PDM is that the frequency of the pulses does not
vary, so it is easier for the programmer to set the base frequency high enough that the
individual pulses cannot be detected by human senses. Also, when driving motors
it is usually necessary to match the pulse frequency to the size and type of motor.
Mismatching the frequency can cause loss of efficiency, as well as overheating of
the motor and drive electronics. In severe cases, this can cause premature failure of
the motor and/or drive electronics. With PWM, it is easier for the programmer to
control the base frequency, and thereby avoid those problems.

> Read full chapter

PWM or Switched Mode Rectifiers

Stefanos N. Manias, in Power Electronics and Motor Drive Systems, 2017

9.4 Multilevel Regenerative Pulse Width Modulation Rectifiers

The PWM multilevel rectifiers have drawn significant attention in high-power
applications such as motor drive systems, FACTS, and RES generation systems. The
major advantages of multilevel rectifiers are:

• High voltage and power capability.

• Lower voltage stresses across each semiconductor device in both modes of

operation as a rectifier or as an inverter.
• Low harmonic content without increasing the switching frequency.

• Reduced switching losses.

• Increased efficiency.

• Good electromagnetic compatibility.

The input or the so-called reflected voltage of multilevel PWM rectifier is synthesized
from a number of voltage levels which are generated by the division of the output
dc source using a number of capacitors connected in series. By increasing the
number of the input reflected voltage dc levels the value of the reflected input voltage
fundamental component is increased and at the same time the quality of the input
current and voltage waveforms of the multilevel rectifier regenerative rectifier are
improved. When the regenerative rectifier is operating in the rectification mode its
input current exhibits low THDi% factor without the application of a large input
filter. Moreover, when the regenerative rectifier is operating in the inversion mode
transferring power from the load to the utility grid its input voltage exhibits low
THDi% factor without the application of a large input filter.

Fig. 9.26 presents the power circuit of the single-phase m-level neutral-point

diode-clamped multilevel regenerative PWM rectifier (NPDCMR). As can be seen
from Fig. 9.26, this power circuit is the same as the power circuit of neutral-point
diode-clamped multilevel inverter with the only difference that the interchange of
the input and output ports. Therefore, for the design of an NPDCMR rectifier, the
following equations can be used:

Figure 9.26. Single-phase m-level neutral-point diode-clamped multilevel regener-

ative PWM rectifier.

(9.44)
(9.45)

(9.46)

(9.47)

where m = number of the input reflected voltage levels;  = dc output voltage.

The active and reactive power of the regenerative rectifier as it was mentioned before
is controlled according to the following two equations:

(9.48)

(9.49)

where  = phase difference between input voltage source, vi, and the rectifier
reflected input voltage fundamental component, vao,1.

Fig. 9.27 presents a single-phase five-level NPDCMR regenerative PWM rectifier.

Moreover, Fig. 9.28 presents the 10 possible modes of operation of the single-phase
five-level NPDCMR regenerative PWM rectifier.
Figure 9.27. Single-phase five-level neutral-point diode-clamped multilevel regen-
erative PWM rectifier.(a) Power circuit; (b) input reflected voltage waveforms.
Figure 9.28. The 10 possible modes of operation of the single-phase five-level
neutral-point diode-clamped multilevel regenerative PWM rectifier.

Table 9.1 summarizes the conduction paths presented in Fig. 9.28.

Table 9.1. The 10 possible conduction paths and respective input reflected voltage
levels of the five-level neutral-point diode-clamped multilevel regenerative pulse
width modulation rectifier

Input reflected voltage vao level ii > 0 ii < 0

Conducting semiconductor devices Conducting semiconductor devices
Sa1, Sa2, Sa3, Sa4 Da1, Da2, Da3, Da4
Dca1, Sa2, Sa3, Sa4 , Dca2
0 Dca3, Sa3, Sa4 , , Dca4
Dca5, Sa4 , , , Dca6
,,, ,,,

Fig. 9.29 presents the power circuit of the three-phase five-level neutral-point

diode-clamped multilevel regenerative pulse width modulation rectifier.
Figure 9.29. Three-phase phase five-level neutral-point diode-clamped multilevel
regenerative PWM rectifier.

Fig. 9.30 presents the power circuit of the single-phase m-level flying capacitor
multilevel regenerative PWM rectifier (FCMR). As can be seen from Fig. 9.30, this
power circuit is the same as that of flying capacitor multilevel inverter (FCMI) with
the only difference that the input and output ports are interchanged. Therefore,
for the design of an FCMR rectifier the equations of FCMI inverter can be used.
Fig. 9.31 presents the power circuit of a single-phase five-level FCMR rectifier.
The implementation of one phase leg of an FCMR requires m − 1 output dc bus
capacitors, (2m − 2) semiconductor switches with their internal freewheeling diodes,
and (m − 1)(m − 2)/2 flying capacitors.

Figure 9.30. Single-phase m-level flying capacitor multilevel regenerative PWM

rectifier.
Figure 9.31. Single-phase five-level flying capacitor multilevel regenerative PWM
rectifier.

Fig. 9.32 presents the power circuit of the single-phase m-level cascaded h-bridge
multilevel regenerative PWM rectifier (CHBMR). As can be seen from Fig. 9.32 and
9.33, this power circuit is the same as that of cascaded H-bridge multilevel inverter
(CHBMI) with the only difference that the input and output ports are interchanged.
Therefore, in order to design an FCMR rectifier the equations of the FCMI inverter
given in Chapter 6 can be used. The number of the input reflected voltage levels is
m = 2s + 1 where s is the number of the output dc bus capacitors which is also the
number of H-bridge units per phase.
Figure 9.32. Single-phase m-level cascaded h-bridge multilevel regenerative PWM
rectifier.

Figure 9.33. Single-phase five-level cascaded H-bridge multilevel regenerative PWM

rectifier with two equal dc output buses of value.(a) Power circuit; (b) input total
reflected voltage waveform of the rectifier and the two H-bridge units input reflected
voltage waveforms.

Except from the staircase square-wave waveform with selected harmonic elimina-
tion, the following multicarrier SPWM ( CSPWM) modulation techniques can be
used also in multilevel regenerative PWM rectifier applications:

1) Phase disposition

2) Alternative phase opposition disposition

3) Phase opposition disposition

4) Phase shift carrier

> Read full chapter

Off-grid solar photovoltaic systems

Rabindra Satpathy, Venkateswarlu Pamuru, in Solar PV Power, 2021

7.2.2.1 Solar charge controller—PWM type

PWM has less-expensive solar charge controller topology. Solar PV modules/arrays
as well as batteries are connected directly to the solar charge controller for operation;
it is mostly used for solar home light or home power systems.

The solar PV module/array is connected continuously to the battery and the higher
solar PV array voltage is brought down to the level of battery terminal voltage. While
charging the battery with the solar PV array, the battery voltage increases and the
charge controller ensures that the solar array output voltage is higher than the
battery voltage.

A solar PV module known as a 12 V nominal voltage is suitably designed to give an

output of around 18 V (considering the solar PV module output voltage variation
due to temperature rise, cable voltage drop), which can charge the battery to 14.4 V
(max charge for a flooded lead-acid battery). As may be understood, if the solar PV
module and battery are of the same voltage, then charging the battery by a solar PV
module would not be possible. Hence, it is required to design the solar PV module
at a higher voltage than the battery.

For charging a 24 V battery bank, we need to connect two solar PV modules (with
Vmp of 18 V each) and similarly for charging of a 48 V battery bank, it would need
four solar PV modules (Vmp = 18 V).

If one uses two solar PV modules (Vmp = 18 V) in series to charge a 12 V battery,
one would be wasting half of the solar PV module capacity, which is not an optimal
use of solar PV module capacity. In a similar manner, if it is intended to charge a
24 V battery bank by a single solar PV module (Vmp = 18 V), one would not be able
to charge the battery and will end up in discharging the battery. Figs. 7.4 and 7.5
explain the loss of energy with the connection of a 12 V module with a 12 V battery
and a 24 V module connected with a 12 V battery.
 Fig. 7.4. Loss of energy with connection of a 12 V module with a 12 V battery with
PWM charge controller.

Fig. 7.5. Loss of energy with connection of a 24 V module with 12 V battery with
PWM charge controller.

PWM solar charge controllers are constant voltage controllers with two-stage regu-
lation. In the first stage, the controller will charge the battery with a higher voltage
so that the battery can be 100% charged. In the second stage, after the battery is
fully charged, it will lower the voltage from the solar array to trickle charge the
battery, so that the battery is kept charged at a 100% charge level. This type of
charging maintains a 100% charge level of the battery while minimizing water loss
and overcharging of the battery.

> Read full chapter

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