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Improvement in the performance of an InGaZnO thin-film transistor by controlling interface

trap densities between the insulator and active layer

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2011 Semicond. Sci. Technol. 26 085012

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IOP PUBLISHING SEMICONDUCTOR SCIENCE AND TECHNOLOGY
Semicond. Sci. Technol. 26 (2011) 085012 (8pp) doi:10.1088/0268-1242/26/8/085012

Improvement in the performance of an

InGaZnO thin-film transistor by
controlling interface trap densities
between the insulator and active layer
Thanh Thuy Trinh1 , Van Duy Nguyen1 , Kyungyul Ryu1 , Kyungsoo Jang1 ,
Wonbeak Lee1 , Seungshin Baek1 , Jayapal Raja1 and Junsin Yi1,2
1
Information and Communication Device Laboratory, School of Information and Communication
Engineering, Sungkyunkwan University, Korea
2
Department of Energy Science, Sungkyunkwan University, Korea
E-mail: yi@yurim.skku.ac.kr

Received 6 January 2011, in final form 15 April 2011

Published 10 May 2011
Online at stacks.iop.org/SST/26/085012

Abstract
An amorphous InGaZnO film fabricated by radio frequency magnetron sputtering in only an
Ar-reactive gas shows high conductivity, and a thin-film transistors (TFTs)-based IGZO active
layer expresses a poor on/off current ratio with a high off current and high subthreshold swing
(SS). This paper presents the post-annealing effects on IGZO thin films to compensate the
oxygen deficiencies in films as well as on TFT devices to reduce the densities of the interface
trap between the active layer and insulator. The ratio of oxygen vacancies over total of oxygen
(O2 /Otot ) in IGZO estimated by the XPS measurement shows that they significantly diminish
from 24.75 to 17.68% when increasing the temperature treatment to 350 ◦ C, which is related
to the enhancement in resistivity of IGZO. The TFT characteristics of IGZO treated in air at
350 ◦ C show a high ION /IOFF ratio of ∼1.1 × 107 , a high field-effect mobility of
7.48 cm2 V−1 s−1 , and a low SS of 0.41 V dec−1 . The objective of this paper is to achieve a
successful reduction in the interface trap density, Dit , which has been reduced about 3.1 ×
1012 cm−2 eV−1 and 2.0 × 1012 cm−2 eV−1 for the 350 and 200 ◦ C treatment samples
compared with the as-deposited one. The resistivity of the IGZO films can be adjusted to the
appropriate value that can be used for TFT applications by controlling the treatment
temperature.
(Some figures in this article are in colour only in the electronic version)

1. Introduction whose minima in a-IGZO are composed of spatially spread

Transparent oxide-based thin-film transistors (TFTs) have
attracted much attention due to their excellent electrical and
optical characteristics. In particular, amorphous indium
gallium zinc oxide (a-IGZO) TFTs have shown a better
threshold voltage (VTH ) and field-effect mobility (μFE ) due
to the lack of grain boundaries, making this type of transistor
a very promising alternative to an amorphous silicon TFT
(a-Si TFT) [1]. The high mobility in a-IGZO material is
attributed to the electron transport by the conduction band,
nanosecond orbitals of post-transition cations (In, Ga, and
Zn) without directionality, in addition to the fact that their
spherical symmetry makes the issue of structural disordering
in the amorphous state non-critical [2].
In fabricating the a-IGZO-based TFTs, IGZO is deposited
widely using magnetron sputtering. This technique generally
provides such benefits as high deposition rates and has low
processing temperatures [3]. Therefore, IGZO has great
potential to replace the existing silicon-based semiconductors
and organic-based semiconductors that are employed as an

0268-1242/11/085012+08$33.00 1 © 2011 IOP Publishing Ltd Printed in the UK & the USA
Semicond. Sci. Technol. 26 (2011) 085012
Figure 1. Schematic cross section of the a-IGZO-based TFT
bottom-gate structure with SiNx /SiO2 gate dielectric on silicon
substrates.
active layer of the TFT backplane in the flat panel display
[4]. However, despite these merits, magnetron sputtering
occasionally results in lower TFT performances due to the
increase in surface morphology roughness [5]. The interface
charge trapping, scattering, and a rough surfacing result in
a decrease in the saturation mobility (μsat ) of TFTs [6],
on/off current ratio (ION /IOFF ) [7], and on drain current [8],
as well as increasing VTH . Moreover, the IGZO-sputtered
films, especially the only-Ar-reactive gas sample, show the
high conductivity caused by the excess of oxygen deficiency,
which degrade the TFT performance. Thermal annealing
is a very useful technique to overcome these problems [9].
Annealing in an appropriate environment, such as O2 or air,
could supply the oxygen component needed to compensate
for the oxygen vacancies (VO ) in the films [10]. Although
some studies [11] have already reported the effect of thermal
annealing on the electrical properties of IGZO thin films, the
effective mechanism was seldom clearly presented for this
phenomenon.
In this work, the correlation between resistivity in
terms of the number of oxygen vacancies and the treatment
temperature was conducted. a-IGZO TFTs were prepared on
a SiNx /SiO2 /p-Si substrate and the rapid thermal annealing
(RTA) process is performed on these structures. Two different
types of devices are compared: as-deposited a-IGZO TFT and
RTA-treated a-IGZO TFT at 200 and 350 ◦ C, respectively.
In this paper, we propose that the decrease in interface trap
density originates from the rearrangement of particles in
films after treatment and the mechanism by which treatment
can influence the TFT characteristic. Superior performance
compared to that of other reports [12, 13] was achieved.
2. Experimental details
Figure 1 presents a schematic cross-sectional view of the TFT
structure. This was fabricated using the p-type silicon wafer
with very low resistivity (ρ∼0.001  cm) as the gate electrode.
The ICP CVD technique was adopted to deposit a 150 nm
layer of SiO2 and SiNx on the Si substrate at a temperature of
160 ◦ C, radio frequency (rf) power of 140 W, and working
2
T T Trinh et al
Intensity (arb. units)
o
Annealed at 350 C
o
Annealed at 200 C
As deposited
20 30 40 50 60
2θ (deg.)
Figure 2. (a) XRD patterns of IGZO films at different annealing
temperatures and (b) SEM images of IGZO films annealed at 350 ◦ C.
pressure of 50 mTorr. These substrates were then cleaned
by acetone, iso-propyl-alcohol, and de-ionized water in an
ultrasonic bath. a-IGZO thin film of 100 nm is deposited as the
active layer using rf magnetron sputtering at room temperature.
The initial vacuum level is lower than 5 × 10−5 Torr, while
the working pressure and rf power are maintained at 5 mTorr
and 140 W, respectively, during sputtering. Pre-sputtering is
performed to remove any contamination on the target surface
for 10 min prior to the active layer deposition. The active
layer is patterned according to the conventional mask process.
The post-annealing process is performed in an air atmosphere
using RTA equipment at temperatures of 200 and 350 ◦ C.
Then, as the source/drain (S/D) electrodes, Ag of 100 nm
was deposited via thermal evaporation at a base pressure of
5 × 10−5 Torr. In this paper, the TFT channel width and
length ratio (W /L) was fixed at 40.
The electrical characteristics of IGZO films and TFT
devices were measured by a semiconductor parameter analyzer
(EL 420C). Structural and surface analyses were performed
using a scanning electron microscope (SEM) and x-ray
diffraction (XRD). The chemical compositions and oxygen
vacancies in IGZO films were analyzed by x-ray photoelectron
spectroscopy (XPS) with an x-ray Al-Ka source.
3. Results and discussions
3.1. Thin films’ characterization
Figure 2(a) shows the XRD patterns of the as-deposited and
annealed a-IGZO films (at 200 and 350 ◦ C) deposited on a Si
wafer. As shown in the figure, no sharp peaks corresponding
to a crystalline phase (such as InGaZnO4 , Ga2 O3 , In2 O3 or
ZnO) were observed for all three samples that agree with other
reports [14]. In this study, the Si wafer peak was not observed
in the range of 15–60◦ , but at 32◦ , as in some reports [15];
however, this is still consistent with other research [16, 17]
because it is not obligatorarily detected. As is widely known,
the amorphous structure of the a-IGZO films is stable up to
∼500 ◦ C [18]. This feature guarantees that the structural
characteristics of the films remain unchanged during a follow-
up heating procedure and work at relatively high temperatures.
Semicond. Sci. Technol. 26 (2011) 085012
O-stabilized on surface
10
5
O2 IGZO bulk Oxygen vacancy:
O
acted as the non-
radiative center
Resistivity (Ω-cm)
4 O2
10 O
O2
O more oxygen bonded with metal ions in the IGZO surface and
3
10
10
2 (O1 ) at 529.96 eV is related to the O2− ion in the lattice
As-deposited 200
o
Annealed temperature ( C)
Figure 3. Electrical properties of films at different annealing
temperatures.
It is known that the amorphous films have the advantage of
large-area uniformity, low interface state density and low
electronic-defect domain [19]. From this result, one can
conclude that the films that annealed at 350 ◦ C still have an
amorphous structure and can be used appropriately as an active
layer in the TFTs’ field. The inset of figure 2 presents the SEM
image which shows the surface morphology of 350 ◦ C IGZO-
annealed film. In the case of an a-IGZO-sputtered thin film,
thermal energy is required to rearrange the atoms on the local
sites. That is, the annealing temperature is attributed to the
internal modifications in the semiconductor structure, resulting
in an improved local atomic rearrangement. The SEM image
shows a clear and uniform surface morphology. There were
no grains or grain boundaries due to its amorphous nature.
This reveals that quite a uniform film can be prepared in this
manner.
The resistivity of IGZO films at different annealing
temperatures was estimated by current–voltage measurement
using the Ag/IGZO/glass structure. In this measurement, we
established the current–voltage measurement and estimated
the resistivity of the single layer of IGZO using the following
equation:
V W
ρ= × × t, (1)
I L
where W , L are the width and the length of the electrodes, t is
the IGZO thickness, and V and I are the input voltage and the
output current, respectively.
As is shown in figure 3, while the as-deposited samples
show a low resistivity of 9.71 × 101  cm, the samples
annealed at 200 and 350 ◦ C achieved the high resistivities
of 7.7 × 102 and 2.9 × 104  cm, respectively. The annealing
temperature dependence on resistivity can be explained based
on oxygen composition, as well as the oxygen vacancies in
the IGZO films that are the main factor for the conduction
mechanism in oxide-based semiconductors.
XPS measurements were performed to determine the
quantitative and qualitative chemical properties of the IGZO
films. Figure 4 shows the representative XPS spectra of IGZO
T T Trinh et al
thin films for all samples at different annealing temperatures.
The In 3d, Ga 2p, Zn 2p and O 1s peaks can be easily
observed. The In 3d, Ga 2p, Zn 2p and O 1s signals are
shown in figures 4(a), (b), (c) and (d), respectively. The In
3d5/2 peak at 444.4 eV, the Ga 2p3/2 peak at 1116.6 eV, and
the Zn 2p3/2 peak at 1020.8 eV indicate In-O, Ga-O, and Zn-
O bonds, respectively. The intensities of these peaks seem to
increase with increasing treatment temperature, implying that
bulk. The O 1s peak can be fitted by three nearly Gaussian
distributions, respectively, centered at 529.96 ± 0.1, 531.55 ±
0.1, and 532.7 ± 0.1 eV [20]. The low binding energy peak
surrounded by the Zn, Ga and In atoms in the IGZO compound
system [21]. That is, the intensity of this component is a
350
measure of the amount of oxygen atoms in a fully oxidized
stoichiometric atmosphere. The binding energy component
(O2 ) at 531.55 eV is associated with O2− ions that are in oxygen
deficient regions within the matrix of IGZO [21]. Therefore,
the change in the intensity of this component may be connected
to variation in the concentration of oxygen vacancies. The
high binding energy component (O3 ) located at 532.7 eV is
usually attributed to the presence of loosely bound oxygen
on the surface of a film termed the specific chemisorbed
oxygen, such as −CO3 or adsorbed O2 [21]. Generally, O2 -
related oxygen vacancies supply free-electron carriers in the
IGZO film resulting in the increase of electron concentration
[22]. The decrease in the O2 peak (in figure 4(f )) with
increasing temperature was attributed to the reduction in
oxygen vacancies, where the surface was compensated with
O atoms. The ratio of oxygen vacancies over total oxygen
(O2 /Otot ) in IGZO significantly diminishes from 24.75% for
the as-deposited sample to 20.62% and 17.68% for the samples
annealed at 200 and 350 ◦ C, respectively. The reduction
in oxygen vacancies leads to the resistivity of IGZO being
enhanced. It is well known that the conductivity mechanism
of ZnO-based material, such as IGZO, is due to the oxygen
vacancy [23]. As described in the inset of figure 3, oxygen
vacancy could be the origin of the carrier and non-radiative
center [24] in ZnO-based materials. During annealing under
O2 or air ambient, O is supplied through the O-stabilized
surface and diffuses into the layer of IGZO to an inactivate
oxygen vacancy state. To conclude, thermal treatment will be
an easy method to improve the properties of IGZO for active
layer application in the TFT field. We note that the contact
resistance and contact type should affect the resistivity of films.
More studies are needed to arrive at a specific conclusion.
3.2. IGZO thin-film transistors
The TFT-bottom gate devices at various annealing temperature
have been fabricated with double layers of the insulator
SiNx /SiO2 . The use of the double insulators SiNx /SiO2 in
this study is to achieve both stability properties of SiNx [25]
and high breakdown voltage properties of SiO2 [26] insulators.
Figure 5 shows all the transfer characteristics of three TFTs
at different annealing temperatures. The drain current (IDS )
was measured in a dark box as the gate voltage (VGS ) swept
3
Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

In 3d As deposited Ga 2p As deposited
In 3d5/2 o Ga 2p3/2 o
Annealed at 200 C Annealed at 200 C
o o
Annealed at 350 C Annealed at 350 C

Intensity (a.u.)

Intensity (a.u.)
Zn 2p1/2
Ga 2p1/2

(b)
(a)

440 445 450 455 1110 1120 1130 1140 1150

Binding energy (eV) Binding energy (eV)

Zn 2p As deposited O 1s As deposited
o O 1s o
Annealed at 200 C
Zn 2p3/2 Annealed at 200 C
o o
Annealed at 350 C Annealed at 350 C
Intensity (a.u.)

Intensity (a.u.)
Zn 2p1/2

(c) (d )

1020 1030 1040 1050 526 528 530 532 534 536
Binding energy (eV) Binding energy (eV)
o O1
O 1s O 1s Sample annealed at 350 C
O 1s As deposited
o
O1 Annealed at 200 C
o
Annealed at 350 C
Intensity (a.u.)

Intensity (a.u.)

O2
O2

O3 (e) (f)

526 528 530 532 534 536 526 528 530 532 534 536
Binding energy (eV) Binding energy (eV)
Figure 4. XPS spectra of IGZO thin films: (a) in 3d (b) Ga 2p (c) Zn 2p (d) O 1s at different annealing temperature and (e) O 1s core-level
XPS spectra of IGZO films annealed at 350 ◦ C. (f ) The O1 and O2 fitting spectra extracted from the O 1s of samples annealed at different
thermal treatment conditions (as-deposited, 200, 350 ◦ C). O 1s XPS spectra show an increase in the intensity with increasing the treatment
temperature.

from −5 to 20 V, with the drain voltage (VDS ) fixed at Table 1. TFT characteristics of IGZO-based device with different
1 V. It is clearly found that the best electrical characteristic annealing temperatures.
is obtained corresponding to the device annealed at 350 ◦ C TFT parameters As-deposited 200 ◦ C 350 ◦ C
with the smallest off current and highest on current. The
as-deposited device expresses the opposite aspects with the μFE (cm2 V−1 s−1 ) 8.55 6.1 7.48
VTH (V) 4.63 9.34 7.9
highest on current and the highest off current. The annealed
SS (V dec−1 ) 2.64 1.28 0.41
samples at 200 ◦ C achieve a result at the average of the two Dit (cm−2 eV−1 ) 0 −2 × 1012 −3.1 × 1012
previous devices. VON (V) – −0.31 2.44
Table 1 lists the key parameters of TFTs. VTH was ION /IOFF 3.7 × 104 2.6 × 106 1.1 × 107
estimated by linearly fitting the IDS versus VGS curve in the
linear region. Under these conditions, the field-effect mobility where Co denotes the insulator capacitance, W /L denotes the
(μFE ) was calculated using the following equation (2) [27]:
aspect ratio of the device, and gm denotes the transconductance
L gm (gm = ∂IDS /∂VGS ). From table 1, the largest ION /IOFF
μFE = , (2)
W Co VDS indicated by 350 ◦ C – treated TFT is about 4.2 times and

4
Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

3.5

)
V D = 1V

-1
-4
10

Subthreshold swing (V.dec

3.0
-5
10 2.5 As deposited
o
Annealed at 200 C
10
-6 2.0 o
Drain current (A)

Annealed at 350 C
-7
1.5
10
1.0
-8
10
0.5
-9
10 0.0 0 1 2 3 4
10 10 10 10 10
-10
10 Stress time (s)
As deposited (a)
-11 o
10 Annealed at 200 C 10
o
Annealed at 350 C As deposited
-12
10 8 o
Annealed at 200 C
-5 0 5 10 15 20 o
Annealed at 350 C

(V)
Gate voltage (V) 6

TH
Figure 5. Transfer characteristics logID -VG at VD = 1 V of

ΔV
IGZO-TFTs with different annealing temperatures. 4

3 × 102 times as high as 200 ◦ C annealed and as-deposited
devices, respectively. Other TFT parameters, such as SS and
VTH , also prove the predominance of the high-temperature-
annealed process. The VTH increases from 4.63 to 9.34 V
compared to the as-deposited and 200 ◦ C annealed sample.
A higher annealing temperature leads to a slight reduction in
VTH , as we can see from the 350 ◦ C sample with VTH = 7.9 V.
The SS is reduced linearly, whereas VON increased with an
increase in the annealing temperature. The best SS value of
0.41 V dec−1 was obtained for the sample annealed in 350 ◦ C.
This was related to the reduction in the interface trap density at
the interface between the active layer and insulator. We have
known that all TFT parameters depend strongly on the defect
density at the insulator/semiconductor interface and inside the
gate insulator. As discussed above, the passivation effect of
a sample annealed at 350 ◦ C greatly improves the electrical
characteristics of TFT. The TFT characteristics are not as good
as those achieved at a higher temperature for the device only
using the 200 ◦ C treatment process.
The improvement in the electrical properties of the sample
annealed at 350 ◦ C can be explained based on the change
in both the carrier concentration of IGZO active layers and
interface trap density that exists between the active layer and
insulator. First, the as-deposited sample shows the highest on
and off currents related to the high conductivity of the channel
layer, leading to a high flow of electrons to pass through
the source and drain. It is known that the off current is a
function of the conductivity of the channel layer, according to
the following equation [28]:
σW
IDS,off =
tCH VDS (3)
L investigate the stability properties of TFT devices at different
where σ denotes the electrical conductivity of the channel
layer, tCH represents the thickness of the active layer, W and L
are the width and the length of the channel layer, respectively.
It is apparent from equation (3) that the channel resistance
2
0
0 1 2 3 4
10 10 10 10 10
Stress time (s)
(b)
Figure 6. Threshold voltage shift and subthreshold swing of
samples with different annealing temperatures.
plays a major role in increasing the off current. The sample
annealed at 350 ◦ C with the highest resistivity (as shown in
figure 3) shows the lowest off current of 3.7 × 10−12 A and
vice versa.
Besides the improvement in ION /IOFF , the sample
annealed at 350 ◦ C also showed the best in SS (as presented
in table 1) compared to other samples that implied an evident
reduction in interface trap density. The changes in interface
trap density values, Dit , presented in table 1 for all samples,
were calculated as [29]
Cox
Dit = (SSafter − SSbefore ). (4)
ln(10)qkT
The results show that the 350 ◦ C annealed sample achieved
the highest Dit . This meant that the interface trap density
could be reduced the most compared to the other samples. This
may be due to the diffusion effects between the insulator layer
and the active layer that occur during the thermal process. This
helps to decrease the number of dangling bonds at the interface
between the insulator layer and the active layer. More studies
are needed to confirm this conclusion.
Gate voltage stress measurements were performed to
annealing conditions. Figure 6 shows the SS and VTH
compared to three devices at different stress times under
condition of VG = +20 V. As shown in figure 6(a), the SS values
of samples annealed at 200 and 350 ◦ C are almost unchanged,

5
Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

while the as-deposited sample shows a large increase with the

stress time. The SS of the as-deposited sample was initially 10
-4

about 2.64 and rose rapidly to 3.35 V dec−1 at a stress time

of 103 s. When the stress time increased to 104 s, the SS was -5
10
observed to shrink. Besides, VTH tends to decrease with
increasing annealing temperatures, as shown in figure 6(b). ΔV TH =1.14 V
-6
The sample at 350 ◦ C treatment also achieves the lowest 10

Drain current (A)

value. The VTH values obtained at 104 s for as-deposited, Forward
200 and 350 ◦ C annealed samples were 8.97, 4.98 and 1.11 V,
-7
10
respectively.
While the parallel shift in VTH without a significant -8
10
change in the SS value during the stress time is attributed
to simple charge trapping in the gate insulator and/or at -9 Reverse
10
the channel/insulator interface, the positive shift in VTH
accompanying the change in SS is due to both charge trapping -10
and creation of defects within the oxide semiconductor channel 10
material [30]. Change in the as-deposited device at both high -11 A nnealed at 200 o C
SS and VTH with the stress time implied high defect creation 10
and charge trapping inside the IGZO active channel. During -5 0 5 10 15 20 25
bias stress at 103 s the SS increased significantly. This denotes Gate voltage (V)
the braking of the bonding at the interface between IGZO and (a)
SiNx such as Si–N created in the interface trap. These defects
-4
formed the traps to disrupt the flow of electrons, and they 10
are able to collect the electrons. In contrast, the sample with
350 ◦ C treatment shows both low SS and VTH shift, compared 10
-5
Δ V T H = 0.48 V
to other samples, insinuating the reduction in defects inside the
Drain current (A)

IGZO active layer. By using thermal treatment, these bonding 10

-6 F orw ard
at the interface can be reinforced. This results in the decrease
in both SS value and the change in SS with the bias stress -7
10
time. The samples annealed at 350 ◦ C denote the stability
with almost no change in the SS value. -8
The shift in VTH with the bias stress refers to the 10
R everse
effect of the deep trap of insulators on the electrical transfer
-9
characteristic of TFT devices. The deep trap source in our TFT 10
devices is the interface trap at the SiNx /SiO2 interface. The
-10
decrease in the VTH shift with increasing treatment temperature 10
may be attributed to the improvement of Si–N or Si–O bonding
A n n ealed at 350 o C
inside the double-layer insulators and inside the IGZO active 10
-11

layer. Thus, the deep trap in the insulators is significantly -5 0 5 10 15 20 25

reduced under treatment at 350 ◦ C.
Figure 7 presents the hysteresis characteristic of the
samples annealed at 200 and 350 ◦ C. Both samples show that
VTH shifted to a more positive voltage for the hysteresis loop
during the return sweep. The positive VTH shift suggests that
negative charge carriers were trapped at the channel/dielectric
interface or injected into the dielectric from the a-IGZO
channel layer. As clearly shown in the figure, the VTH shift
of the sample annealed at 350 ◦ C was very small compared to
the 200 ◦ C annealed sample. The VTH of samples annealed
at 200 and 350 ◦ C are 1.14 and 0.48 V, respectively.
For forward sweeping, the interface states discharge the
initially trapped carriers and then begin to trap the carriers,
while the gate bias sweeps into the subthreshold region [31].
Hence, an inferior SS of 1.28 V dec−1 is obtained for the 200 ◦ C
sample, as shown in figure 7(a). These unfilled interface
states will also degrade the effective mobility. Conversely, for
reverse sweeping, the interface states were filled with carriers
and become non-influential in the subthreshold region [31],
Gate voltage (V)
Figure 7. Transfer characteristics ID -VG at VD = 1 V for IGZO
TFTs with annealing at (a) 200 ◦ C and (b) 350 ◦ C for both in the
forward and reverse VG sweeps.
so SS increased to 1.32 V dec−1 . Moreover, the carrier
trapping/de-trapping will cause the hysteresis phenomenon.
Compared to the devices treated at 200 ◦ C, the devices treated
at 350 ◦ C a-IGZO TFTs exhibit superior electrical properties,
such as slight VTH = 0.48 V, and lower SS (from 0.42 to
0.41 V dec−1 , for forward sweep). These are shown in
figure 7(b). TFTs annealed at 200 ◦ C have a relatively large
clockwise hysteresis in the transfer characteristics VTH =
1.14 V, which is explained by trap filling by the accumulated
electrons. These indicate that the electron traps are reduced
by thermal annealing. The improvement in the transfer
characteristic indicates the termination of defects at the a-
IGZO/dielectric interface and in the a-IGZO bulk. This can be

6
Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

Turn-on voltage (V) Threshold voltage (V)

12

16

Field effect mobility

5

(cm2V-1s-1)
12

0
8

-5
4

8
10 Subthreshold swing 15

6
10
(V.dec-1)
Ion/Ioff

10

4
10 5

2
10
0
o o o o
As deposited 200 C 350 C As deposited 200 C 350 C
Annealing condition Annealing condition
Figure 8. TFT performances of IGZO-TFT at different treatment conditions in statically analysis.

ascribed to the reduction in oxygen vacancy by air annealing.
The best SS of 0.41 V dec−1 reveals that only a few interface
states remained.
In summary, the electrical parameters of the four devices
representative of each annealing treatment were determined
for statistical analysis. Figure 8 shows the statistical analysis
results. It is clear from the figure that the thermal treatment
process at different temperatures can easily improve IGZO-
TFT performance. VON of devices annealed at 200 and
350 ◦ C have almost the same value ranges, while VTH of
samples treated at 350 ◦ C significantly decrease, resulting in
the improvement of SS. The most significant influence of the
annealing condition is to increase the ION /IOFF and μFE . Note
that the samples annealed at 350 ◦ C with high resistivity still
have the same μFE value compared to the as-deposited samples,
implying the upgrading in the TFT structure after annealing
and the contact between IGZO and Ag contact. More studies
should be done to draw a conclusion.
4. Conclusions
In this study, the influence of thermal treatment on electrical
properties of IGZO thin films has been carried out. The oxygen
vacancies in the bulk, compensated during the annealing
process, raise the resistivity. The electrical characteristics
of two types of TFT, with and without thermal treatments,
are compared by plotting the transfer characteristics. The
post-annealed TFT is found to be more suitable to be used
for switching devices, and has better performance, such as
the higher μFE , larger current, and ION /IOFF , as well as lower
VTH , than others do. The interface trap density is controlled
to achieve the optimum value of TFT transfer and output
characteristics. The mechanism to reduce the interface trap
density by thermal treatment is explained by the decrease in
carrier concentration due to the decrease in oxygen vacancies
in the IGZO films. Consequently, the annealing effect on a-
IGZO TFT’s electrical characteristics has been presented. This
work is expected to be useful to further advance oxide-based
TFT technology for future devices.
Acknowledgments
This research was supported by the WCU (World Class
University) programme through the National Research
Foundation of Korea funded by the Ministry of Education,
Science and Technology (R31-2008-000-10029-0).

7
Semicond. Sci. Technol. 26 (2011) 085012
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