Serial Communication

Unit IV Syllabus
• Interrupts: Interrupt structure of 8085A microprocessor, processing of vectored and non-vectored
interrupts, Handling multiple interrupts, and programming.
• Programmable Interrupt Controller: Intel 8259, Block diagram, Interrupt operation, programming.
• Serial I/O Concepts, SID and SOD, Intel 8251A programmable communication Interface, pin
configuration, internal block diagram, programming.
ASCII Code
• 7 bit code
• 128 combinations
• 30H to 39H represents 0-9
• 41H to 5AH represents A-Z
• 21H to 2FH represents symbols
• 00H to 1FH represent machine commands such as CR
Synchronous vs Asynchronous Format
Format of Asynchronous Serial Tansmission
Data Communication over Telephone lines
Serial Data Transmission using s/w control
Serial Data Reception using s/w control
8085-SID & SOD Lines
• SOD
• Instruction SIM is used
MVI A,80H
RAR
SIM
• First Serial output line is enabled SDE=1 and then the carry bit is
output
SID
• RIM is used

USE OF SID and SOD

• Eliminate the need for an input and output ort
• SID is 1-bit input port
• SOD is 1-bit output port
• RIM is 1-bit IN instruction
• SIM is 1-bit OUT instruction
8251 USART
Control Registers
Transmitter Section
Receiver Section
Initializing the 8251A
• Control Words
• Mode word specifies baud, parity, number of stop bits
• Command word enables data transmission, reception
• Status Word
• Register status and transmission errors
• Sequence of Programming:
• After a Reset (System Reset or Instruction) first write Mode word
• Then Command Word
• Any Control Word written after Mode Word is interpreted as Command word
• Prior to writing new Mode word reset using Internal Reset bit.
8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Baud Rate

Stop bits Parity enable
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length 11: x64 clock
11: 2 bits
00: 5 bits
01: 6 bits
Parity 10: 7 bits
0: odd 11: 8 bits
1: even
8251 command register

EH IR RTS ER SBRK RxE DTR TxE

TxE: transmit enable

DTR: data terminal ready
RxE: receiver enable
SBPRK: send break character
ER: error reset
RTS: request to send
IR: internal reset
EH: enter hunt mode (Sync Mode)
8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY

TxRDY: transmit ready

RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready
 Lets Try This!
• Identify the port address of the Control Register, Data Register
and Status Register.
• Specify the initialization instns and the status word to transmit
characters if TxC=153.6kHz.
Baud rate=9600 baud
Character length= 7 bits
2 Stop bits
No parity
• Write instns to initialize 8251, to read the status and set up a
loop until TxRDY is ready.