Some features of I2C

Drakshi B
Ponnaiya V

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 INDEX

• 10 bit addressing.
• Standard mode
• fast-mode
• high-speed mode

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7-bit format 10-bit address

1) START
1) START
2) ADDR[6:0]
2) 1st byte (11110xx)
3) Address ACK
3) R/W’
4) R/W’
5) WDATA[7:0] / RDATA[7:0] 4) ACK1 (by multiple devices)

6) Data ACK 5) 2nd byte(xxxx_xxxx)

7) STOP or Repeated START Condition 6) ACK2(by selected slave)
7) WDATA[7:0] / RDATA[7:0]
8) Data ACK
9) STOP or Repeated START Condition

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 10 bit addressing
• 10-bit addressing expands the number of possible addresses.
• Devices with 7-bit and 10-bit addresses can be connected to the same I2C-bus, and both 7-bit and
10-bit addressing can be used in all bus speed modes.
• Currently, 10-bit addressing is not being widely used.
• After START condition or a repeated START condition, 10 bit slave address is given using 2 bytes (as
i2c supports byte format).
• 1111xxx and 0000xxx is not allowed in 1st byte as they are reserved for some other purpose.
(11110xx is the one that is allowed)

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Write operation using 10 bit addressing

• Master-transmitter transmits to slave-receiver with a 10-bit slave address. The transfer

direction is not changed .
• When a 10-bit address follows a START condition, each slave compares the first seven bits
of the first byte of the slave address (1111 0XX) with its own address and tests if the
eighth bit (R/W’ direction bit) is 0.
• It is possible that more than one device finds a match and generate an acknowledge (A1).
All slaves that found a match compare the eight bits of the second byte of the slave
address (XXXX XXXX) with their own addresses, but only one slave finds a match and
generates an acknowledge (A2).
• The matching slave remains addressed by the master until it receives a STOP condition or
a repeated START condition followed by a different slave address.

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 Read operation using 10 bit addressing
• After the repeated START condition (Sr), a matching slave remembers that it was addressed before.
• This slave then checks if the first seven bits of the first byte of the slave address following Sr are the
same as they were after the START condition (S), and tests if the eighth (R/W) bit is 1. If there is a
match, the slave considers that it has been addressed as a transmitter and generates acknowledge
A3.
• The slave-transmitter remains addressed until it receives a STOP condition or until it receives another
repeated START condition (Sr) followed by a different slave address.
• After a repeated START condition (Sr), all the other slave devices will also compare the first seven bits
of the first byte of the slave address (1111 0XX) with their own addresses and test the eighth (R/W)
bit. However, none of them will be addressed because R/W = 1 (for 10-bit devices), or the 1111 0XX
slave address (for 7-bit devices) does not match.

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 Standard mode

• Bit rate is 100kbits/Serial 8bit(byte format).

• Follows arbitration(Wired AND) only on Multi master.
• Clock generation is done by master, including 9th clock cycle ACK.
• Data transferred with MSB first.
• Two master can transfer at same time without giving error, if the transmission are
identical.

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 Fast mode (bit rate-400 k bit/sec)

• Fast mode can operate in standard mode but standard mode cannot operate in fast
mode.
• Timing of the serial data (SDA) and serial clock (SCL) signals has been adapted.
• The inputs of Fast-mode devices includes spike suppression and a Schmitt trigger at the
SDA and SCL inputs.
• The output buffers of Fast-mode devices includes slope control of the falling edges of
the SDA and SCL signals.
• If the power supply to a Fast-mode device is switched off, the SDA and SCL I/O pins must
be floating so that they do not obstruct the bus lines.
• The external pull-up devices connected to the bus lines must be adapted to
accommodate the shorter maximum permissible rise time for the Fast-mode I2C-bus.

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 High speed (hs) mode –( bit rate 3.4 Mbit/sec)

• Abritration and clk synchronisation is not allowed but during the Hs-mode transfer, the
same serial bus protocol and data format is maintained as with the F/S-mode system.
• Hs-mode master devices have an open-drain output buffer for the SDAH signal and a
combination of an open-drain pull-down and current-source pull-up circuit on the SCLH
output. This current-source circuit shortens the rise time of the SCLH signal. Only the
current-source of one master is enabled at any one time, and only during Hs-mode.
• Hs-mode master devices generate a serial clock signal with a HIGH to LOW ratio of 1 to 2.
This relieves the timing requirements for set-up and hold times.
• Optional pull-down transistors on the SCLH pin can be used to stretch the LOW level of
the SCLH signal, although this is only allowed after the acknowledge bit in Hs-mode
transfers.
• Before ACK, the rise time of the SCLH clock pulses in Hs-mode transfers is shortened by
the internal current-source pull-up circuit of the active master.
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Data format for HS mode: .

1) START
2) 8-bit master code (0000 1XXX) Represents fast mode
3) Not-acknowledge bit (A’)
4) REPEATED START
5) SLV ADDR [6:0]
6) R/W’
7) ADDR ACK Represents HS mode
8) RDATA[7:0] /WDATA[7:0]
9) DATA ACK
10) REPEATED START
11) STOP After this Back to fast mode

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 .

• The master code has two main functions:

1) It allows arbitration and synchronization between competing masters at F/S-mode
speeds, resulting in one winning master.
2) It indicates the beginning of an Hs-mode transfer.
• Hs-mode master codes are reserved 8-bit codes, which are not used for slave addressing or
other purposes.
• Each master has its own unique master code, up to eight Hs-mode masters can be present
on the one I2C-bus system.
• The master code indicates to other devices that an Hs-mode transfer is to begin and the
connected devices must meet the Hs-mode specification. As no device is allowed to
acknowledge the master code, the master code is followed by a not-acknowledge (A’).

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Thank You
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