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  • Interview Qtns

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    1am17ec014 ashnal ahmed
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    This document discusses various topics related to digital circuit design and layout including floorplanning guidelines, endcap cells, setup and hold times, channel length calculations, congestion issues, ECO strategies, power planning, cell types, via placement, and delay modeling. It asks questions about optimally placing standard cells and routing signals while meeting timing constraints and managing power, area, and congestion across multiple abstraction levels of the design process.

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    This document discusses various topics related to digital circuit design and layout including floorplanning guidelines, endcap cells, setup and hold times, channel length calculations, congestion issues, ECO strategies, power planning, cell types, via placement, and delay modeling. It asks questions about optimally placing standard cells and routing signals while meeting timing constraints and managing power, area, and congestion across multiple abstraction levels of the design process.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    8 views1 page

    Interview Qtns

    Uploaded by

    1am17ec014 ashnal ahmed
    This document discusses various topics related to digital circuit design and layout including floorplanning guidelines, endcap cells, setup and hold times, channel length calculations, congestion issues, ECO strategies, power planning, cell types, via placement, and delay modeling. It asks questions about optimally placing standard cells and routing signals while meeting timing constraints and managing power, area, and congestion across multiple abstraction levels of the design process.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    1. Floorplan guide lines ?

    2. Well tap cells at on/off domain ?


    3. What is endcap cell? Where will you place? What happen if don’t place?
    4. Setup time and hold time
    5. Channel length calculation and soft blockage and hard blockage?
    6. What is congestion? Where did you see congestion in your block?
    7. DRV fixing techniques?
    8. Cloning algorithm?
    9. suppose if our block have Clock Tran, data Tran, set up, hold, noise violations from these violations
    fixing order in ECO stage?
    10. Power plan for on off domains?
    11. What is power switches working?
    12. What is the difference bet ween HVT ,LVT and svt cell?
    13. Can we place HVT and LVT side by side?(if cell have 4X size we can place)
    14. What are the reasons for via not placing? How do you place via?
    15. Suppose two different nets has 100 u length and 1u width and 2u width, how is delay between two
    nets, and what is the dominating factor?
    16.What is site ?

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