International Conference on Communication and Signal Processing, July 28 - 30, 2020, India Moore and Mealy Negative Edge detector A VHDL Example for Finite State Machine Pradeep Garapati and Sarada Musala Abstract—tn modern societies we are more dependent on computerized tools, they help us to cope with recent modern lives, The automatic machines perform a variety of operations by adapting the changes in the physical environment. Here in this ‘two varieties FSM, Moore and Mealy, are mentioned. Moore and. Mealy machine state diagram are designed and implemented by ing a negative edge detector circuit. The designed state ‘machines are implemented in VHDL. For both state machines comparison is also made. SM, VHDL, Xilins Index Terms—1 Edge Detector , Moore, Mealy, Negative I Inrropuction 'SM is which changes from one state to another state due to applied external inputs. The change from one state to another slate is called a transition, An FSM is defined by a list ofits state, it has its initial state, and final stae for each input (1-6). Fig. 1 illustrates the working of a FSM model. Usually it has bubble and arrow in the diagram (7,8). The bubble indicates the state and an arrow indicates the direction from state to state [9]. The state machine has present state and next state when the clock sigeal is applied {10-12}, inj Losi © ouput Fig 1. The genta FSM mode FSM is classified into two types they named as Moore and Mealy machines which are widely used for the automata and control applications [13-15]. There are other types of FSM called deterministic FSM and Non-deterministic FSM [16]. The deterministic FSM are whieh for each input symbol, one can determine the next state of the machine and it has a finite umber of states where as in non-delerministic FSM one cannot determine the next state of the machine [17-20] Pradeep Garapai, Sarada Mussla are with Eleewonies and Communication Enpnoeting Vignas Foundation fr Seience, Technology & Recah Vadlamadh (emit pradcenprapti2a¥aiilcom, snide marasv@igml com) 978-1-7281-4988-2/20/$31.00 ©2020 IEEE 1159 1. Moore Machines ‘A Finite state machine is said to be Moore machine if its output depends only on the present slate and i€ has no relation with input [21,22]. For generating the outputs it considers the clack as shown in ig. 2 Fig. 2 Moore Machine general Block Diagram 2. Mealy Machines A Finite state machine is said to be Mealy machine if its output depends only on the present state and present input as shown in Fig. 3. For applied input, it can generate a variety of different output pattems in the same state. Iti determined as a function of both input and clock signal [23-26] Fig. 3. Mealy Machin general Block diagram ‘The remainder of the paper is well organized as below: ection TI describes about the illustrating example. Section TIT concludes the paper withthe conclusion, UL ILLUSTRATING EXAMPLE The FSM working process is explained by designing the negative edge detector circuit. The designed FSM can be used in the automata applications like vending machines. This circuit generates one pulse for each clock eyele which is tick, when the Input changes to logic low from high. IEEE donne ayThis functionality is high-to-low transition of a slow time-varying input signal The designed circuit is implemented by using both Moore and Mealy state machines. Both designed machines are also compared. The state diggram indicates the falling edge detector based on Moore state machine is shown in Fig. 4 tei 7 ;equently employed to indicate the VS Fig. Faling ee dct sat diag bad on Moore state machine Here zero, edge and one are the states. The level is given as input where level = “I” and level The tick is specified as an output, When the input is low in the state one, then falling edge oceurs and output ticks becomes one and FSM state changes to edge. Following state diagram indicates the falling edge detector based on a Mealy state machine is shown in Fig. 5. The FSM changes to state zero and output tick becomes one in this state. These two Moore and Mealy state machine-based designs, are carried out in VHDL, using Xilinx software, Below is shown Fig. 6 and Fig, 7 are Register Transfer Level (RTL) schematic of a falling edge detector based on Moore and Mealy finite slate machine. Fig. 6 RTL schematic of filing edge detector based on Moor machine sna poh np OF) ne say. zh sate .0 We have designed state diagrams for Moore and Mealy machines and the stale machines functionality is verified in Xilinx. Fig. 8 and Fig. 9 represent the timing diagrams obtained for designing negative edge detectors based on Moore and Mealy state machine, Fig. &. Falling edge detetor Timing Digram based on Moore machine Fig. 5. Falling edge dtetr state diagram based on a Mealy state machine. Fig. 9, Fling og detector Timing Digna basod on Mealy machine 1160Fig. 8 and Fig. 9 show both Moore and Mealy machine- based designs, generates output tick at the falling edge of the applied input signel. Still, there are some differences in both state machines, The Mealy machine-based design responds quickly than Moore state machine design because it requires lesser states and does not wait for the clock for generating the output For asynchronous system implementations Mealy machines are not suitable as Moore machines, because the small change in the input corresponds to change in output independent of the clock it may lead to instability ofthe system, II. Coxcuuston In modem times, we are more depending on the computerized ‘machines. In this FSM (Finite State Machine) like Moore and Mealy machines based negative edge detector state diagrams ‘are designed and implemented using XILINX the timing diagrams are verified and RTL schematics are also generated using it. Here the comparison is made between the Mealy and ‘Moore FSM based on the timing diagram of the state machines. On the other hand by using Moore machine one can design both ‘asynchronous and. synchronous systems whereas Mealy machines is suitable for implementing synchronous systems nly. Moore and Mealy based machine designs are used to implement in real time applications like vending machines, ‘uafiie light system, elevators. [REFERENCES Sultana Alsi, S.M, Qasr, W, Alalsbi “A VHD Based Moore and “Mealy FSM Example for Education "IEEE 2nd Intemational Coafercace ‘on Sigal an image Processing2017. E.G: Hfeachor and BW Jervis, Digital signal procesing practical ‘approach Pearson Fusion 2002 Ingle, Vingy K, and Jobo G, Pooks. Digital Sigal Processing Using MATLAB: A Problem Solving Companion. Cengage eaming, 2016 Smith, Steven, Digtal signal processing «pasts guide for enginoses td siete. Newaee, 2013, For, Blair, et al "Automating the design of processoacecirtor tmbeded ystems with legup high-level synthesis” Embedded and Ubiquitous CompasingEUC).2" IEEE Iematina] Conference oa. TERE, 2014 M.S. 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