A Novel Fast, Low-Power and High-Performance
XOR-XNOR Cell
Majid Amini Valashani and Sattar Mirzakuchaki
Department of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran
Email: amini.m.v@gmail.com, m_kuchaki@iust.ac.ir
Abstract—Many existing XOR-XNOR cells suffer from
nonfull-swing outputs, high power consumption and low speed
issues. In this paper, a new fast, full-swing and low-power XOR-
XNOR cell, is presented. Simulation results in 90-nm CMOS
technology show that the proposed circuit has rail to rail outputs
Also, we have gained 11%-51%, 2%-19% and 18%-52%
improvement in delay, power consumption and power-delay
product (PDP), respectively. In order to do a comparison
between the previously reported XOR-XNOR cells and our
proposed circuit, they are embedded in a 4---2 compressor circuit
and simulation results prove energy efficiency of ours in more
complicated structures.
Keywords — exclusive-OR (XOR); exclusive-NOR (XNOR);
full-swing; high-speed; low-power
I. INTRODUCTION
The XOR-XNOR cells play a vital role in numerous circuits
such as adders, compressors, comparators, parity checkers and
so on. Therefore, their behavior can affect the circuit
performance greatly. Since the minimum feature size of
MOSFET devices is scaling down into only a few nanometers,
the supply voltage should be reduced to prevent hot-carrier
effects in CMOS circuits [1]. So, the importance of enhanced
designs for circuits to reduce power consumption, speed up
the operation and also to avoid any reduction in the output
signal levels, is not negligible. Also, XOR-XNOR cells and
multiplexers are the vital part of practical circuits such as
compressors and full adders. To drive selection lines of
multiplexers in these circuits, the combined XOR-XNOR cell
is used. Therefore another key feature for designing these
circuits is to generate outputs at the same time rather than
using an inverter to generate one output from the other one.
The main contribution of this paper is the design of a XOR-
XNOR cell which is fast, low-power and provides full-swing
outputs. The rest of this paper is organized as follows. Section
II gives a background and discusses the related works. In
section III, the new XOR-XNOR cell based on two new
structures for XOR and XNOR gates is presented and section
IV gives the simulation results. Finally section V concludes
this work.
II. PREVIOUS WORKS
A variety of topologies have been proposed in the
literature to realize the XOR and XNOR cells using different
978-1-4799-5341-7/16/$31.00 ©2016 IEEE 694
logic styles [2-5]. One way is implementing XOR output, then
turning it to XNOR output using an inverter. Two different
designs that use this method are shown in Figs. 1(a) [2] and
1(b) [3]. Fig. 1(a) shows a circuit which uses low power XOR
gate (LP-XOR) presented in [2] to implement XOR function
and a static CMOS inverter to implement XNOR function.
This circuit is characterized by its low power consumption and
uses only six transistors, but it has nonfull-swing outputs. In
the case of input signals AB=00, both PMOS transistors before
the inverter will be ON and a poor low signal will appear at
the XOR output, i.e. PMOS threshold voltage ( VTP ). This
weak signal can still drive the inverter and produce strong ‘1’
at the XNOR output. In the other input combinations, the
output signals will be complete.
The other structure that uses an inverter to implement
XNOR output from XOR output is illustrated in Fig. 1(b) [3].
This circuit uses two transmission gates and three inverters.
Although the mentioned problem is fixed in this design, but
the main drawbacks are high average power consumption and
low speed due to presence of three inverters. It is worth
mentioning that delays of XOR and XNOR outputs of designs
in Figs. 1(a) and (b) are different due to presence of an
inverter for producing the XNOR output.
Another way to realize XOR-XNOR functions is to
generate them simultaneously as depicted in Figs. 1(c) [3], (d)
[4] and (e) [5]. The circuit in Fig. 1(c) is a low power design
which is made of eight transistors and uses low power XOR
and XNOR gates reported in [2] to produce its both outputs
simultaneously. This design does not provide full-swing
outputs. When both inputs A and B are low, the XOR output
has weak logic level (a little higher than 0, i.e. VTP ), and when
both are high, the XNOR output has weak logic level (a little
lower than VDD, i.e. VDD – VTN). Therefore, the mentioned
drawback of design in Fig. 1(a) exists as well. This problem
will be more critical in submicron technologies and low
supply voltages.
Two previously reported XOR-XNOR cells which produce
both outputs simultaneously and provide good output levels in
all possible input combinations are shown in Figs. 1(d) [4],
1(e) [5]. To guarantee full-swing operation cross-coupled
PMOS transistors are used in both circuits. Design in Fig. 1(e)
is very similar to design in Fig. 1(d), except it uses only one
inverter. The total transistor count of circuits in Fig. 1(d) and
 (a) (b)
Fig. 2. New designs for XOR and XNOR gates. (a) XOR gate, (b) XNOR gate.

TABLE I. OUTPUT VOLTAGE LEVELS OF XOR AND XNOR CIRCUITS SHOWN

IN FIG.2 FOR ALL INPUT COMBINATIONS.

(a) (b) (c) Input combination Fig. 2 (a) Fig. 2(b)

A B (XOR output) (XNOR output)
0 0 Bad 0a Good 1
0 1 Good 1 Good 0
1 0 Good 1 Good 0
1 1 Good 0 Bad 1b
a. VTP
b. VDD - VTN

(d) (e) III. SIMULATION RESULTS AND DISCUSSION

Fig. 1. Five different designs of XOR-XNOR circuit. (a)Wang’s circuit [2],
(b) and (c)Shams’s circuit [3], (d) Aguirre’s circuit[4] and (e) Goel’s circuit [5] A. Simulation Setup
In order to evaluate the performance of our proposed
circuit under realistic conditions, the simulation setup in Fig. 5
(e) is ten and eigth respectively. These circuits suffer from
[6] is used. The two inputs, A and B are loaded from the input
high power consumption, low speed and low Power-Delay
buffers before they are fed to the cell. The two outputs, XOR
Product (PDP). Proposed Circuit
and XNOR, are also loaded to the buffers. The transistor sizes
In this section we propose the design of a new XOR-XNOR
of the buffers are chosen such that there is adequate signal
cell that provides full-swing outputs simultaneously in all
input combinations. But before going through the design degradation as expected in a real circuit [5]. The total number
procedure, we start with two new circuits for implementing of possible transitions for an XOR-XNOR cell is 16, but by
XOR and XNOR gates separately as shown in Fig. 2. These eliminating redundant transitions, where the input combination
circuits use one static CMOS inverter for implementing their does not change, 12 transitions are remained. (By starting with
function and both use only five transistors. Their most the input combination, AB=00 and changing it to 01, back to
important drawback is the arrival of a bad logic level for one 00, from 00 to 10, back to 00 and so on, 12 transitions are
input combination at output nodes, as shown in Table I. In Fig. achieved). All these 12 transitions from an input pattern to
2(a) when AB=00, transistor MN will be OFF, and both another have been considered in evaluating functionality and
transistors, MP1 and MP2 will be ON. Because of passing low computing delay, power consumption and PDP of circuits.
logic value through PMOS transistors, threshold voltage of a
PMOS transistor ( VTP ) will be produced at the XOR output. B. Functionality and Important Parameters
In the case of AB=11, for the circuit depicted in Fig. 2(b), The simulations are done using HSPICE in 90-nm
transistor MP will be OFF and both NMOS transistors will be Predictive Technology Model (PTM) CMOS technology, 1v
ON. Therefore high logic level passes through NMOS supply voltage and 250-MHz input frequency. Input and
transistors and yields weak ‘1’ at XNOR output.
output waveforms of our new circuit and circuits in Figs. 1(a)
By combining circuits in Fig. 2(a) and (b), we can achieve a
and 1(c) are shown in Fig. 5 for comparison. According to Fig.
topology that produces both XOR and XNOR outputs
5, our proposed design provide full-swing outputs for all
simultaneously as shown in Fig. 3. To overcome the problem
possible input combinations and also due to shorter glitches in
of nonfull-swing outputs of designs shown in Fig. 2(a) and (b),
our circuit outputs as compared with the outputs of Figs. 1(a)
a feedback loop consisting of one PMOS and one NMOS
and 1(c), the average power consumption can be saved.
transistor is used. In the case of AB=00, first, weak ‘0’ appears
at XOR output (see Table I), but it is still capable to turning
the PMOS transistor in feedback loop (MPF) ON. Then VDD
passing through this PMOS turns the NMOS transistor in
feedback l (MNF) ON and produces strong ‘0’ at XOR output.
When both inputs are high, weak ‘1’ appears at XNOR output
In this case, MNF will be ON, passing ‘0’ to XOR output, MPF
will turn on and produces strong ‘1’ at XNOR output. In the
other input combinations, both outputs have full-swing
voltages.
Fig. 3. The proposed XOR-XNOR cell.

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Fig. 4. Simulation setup.
In order to have a fair comparison, we optimized all the
four structures (our design and the previous ones introduced in
Figs. 1(b), 1(d) and 1(e)) with the same sizing algorithm
described in [8] to achieve minimum PDP. The ratio W/L is
written near each transistor in Figs. 1, 2 and 3. Channel length
(L) of all transistors is fixed at 90-nm. All circuits have been
simulated under realistic conditions as depicted in Fig. 5. In
each transition, the times between inputs reaching 50% of the
voltage supply level and outputs reaching the same voltage
level are measured. The worst case is considered as the
outputs delay. The delay is calculated from the output of the
input buffers to the cell outputs. Due to different switching
activities which is caused by different input patterns, power
consumption changes. To be fair, all input patterns should be
considered and the average power consumption of all cases
should be set as the average power dissipation. PDP that is
related to the energy efficiency of a logic circuit is calculated
as well. The results are tabulated in Table II.
Simulation results show that our proposed XOR-XNOR
circuit is the fastest one among its counterparts, 32%, 11%,
51% faster than circuits in Figs. 1(b), 1(d) and 1(e),
respectively. In the case of power consumption, our suggested
circuit is the most power efficient one among all the discussed
XOR-XNOR cells. It also has the best PDP, 18% less than the
best existing PDP (circuit in Fig. 1(d)). Also the layout view
of the proposed XOR-XNOR cell is shown in Fig. 6, which
shows the symmetric and regular structure of our design.
In order to assess our design performance under supply
voltage changes from 0.6v to 1.2v, we measured the values of
delay, power consumption and PDP within this range of
variation for supply voltage. Fig. 7 shows that all the
considered circuits have reasonable characteristics while
reducing supply voltage. Although design in Fig.1 (d) acts
better than ours in term of delay for lower 0.8 supply voltages,
Figs. 7(b) and (c) show that the power consumption and PDP
of the presented circuit remain the best even in low supply
voltages.
C. Simulation Results for a 4-2 Compressor
XOR-XNOR circuits are widely used in large structures
such as compressors and adders. To compare the performance
of our new design in a real application, XOR-XNOR circuits
with multiplexers are used to build a 4-2 compressor as shown
in Fig. 8(a) [9]. It is mainly built of six modules, two XOR-
XNOR cells and four 2-1 MUX modules. Fig. 8(b) [10] shows
the static CMOS 2-1 multiplexer used in the 4-2 compressor.
It is robust against both voltage scaling and transistor sizing
and delivers sufficient drive to its succeeding blocks through
the output inverter [11]. Therefore, it is a good candidate to be
used in the 4-2 compressor.
The two control signals of MUX module, select and select
bar, should arrive the multiplexer at the same time to avoid
glitches and also to decrease the power which is consumed by
these unwanted glitches [10]. Worst-case delay, average
power consumption and PDP of 4-2 compressors by using
XOR-XNOR circuits in Figs. 1(b), 1(d), 1(e) and our proposed
scheme are calculated and shown in Table III. To be fair, the
MUX that is shown in Fig. 8(b) is used in all four 4-2
compressors. According to Table III, the delay, power
consumption and PDP features of our proposed circuit are
better than the other compared designs.

Fig. 5. Input and output waveforms of different XOR-XNOR cells.

TABLE II. SIMULATION RESULTS FOR DIFFERENT XOR-XNOR CIRCUITS IN

90-NM PTM CMOS TECHNOLOGYAT F= 250MHZ AND VDD = 1V.
Circuit Delay-XOR Delay-XNOR Power PDP
(ps) (ps) (uw) (1e-16)
Fig. 1(b) 31 50 1.04 0.52
Fig. 1(d) 35 38 1.13 0.43
Fig. 1(e) 65 69 0.94 0.65
Proposed 34 32 0.92 0.31
Fig. 6. Layout of the proposed XOR-XNOR cell.

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 Delay .Vs Supply Voltage TABLE III. SIMULATION RESULTS FOR 4-2 COMPRESSORS IN 90-NM PTM
200 CMOS TECHNOLOGY AT F = 250 MHZ AND VDD = 1V.
Fig. 1(b)
180
Fig. 1(d) Architecture Worst-Case Power PDP
160 Fig. 1(e) using Delay (ps) (uw) (1e -16)
Proposed
140 Fig. 1(b) 180 5.82 10.47
Fig. 1(d) 175 5.81 10.17
Delay(ps)
120

100 Fig. 1(e) 193 5.73 11.06

80 Proposed 159 5.60 8.90
60

40

20 IV. CONCOLUSION
In this paper a new XOR-XNOR cell is designed and
0
0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3
Supply Voltage(VDD) compared with previous works. Simulation results show that
our proposed design has good functionality in 90-nm CMOS
Average Power Consumption .Vs Supply Voltage technology. A comprehensive comparison has been done with
1.8
Fig. 1(b)
some of the existing designs and there were almost 11%, 2%
Average Power Consumption(uw)

1.6
Fig. 1(d) and 18% reduction in terms of delay, power consumption and
1.4
Fig. 1(e) PDP, respectively, when compared to the best counterpart
Proposed
1.2
designs. Also by using the proposed cell in a 4-2 compressor,
we concluded that it can work efficiently in larger circuits.
1

0.8

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