Date: 2/08/2020

Advanced VLSI Design Lab (EC17203)

Experiment No. 2
Aim: To design and simulate XOR gate using Symica DE tool.

Tool & Apparatus Used: Symica DE3.1.0.0209

Theory:

XOR gate is a digital logic gate that gives a true (1 or HIGH) output when the number of true
inputs is odd. An XOR gate implements an exclusive or; that is, a true output results if one, and
only one, of the inputs to the gate is true. If both inputs are false (0 or LOW) or both are true, a
false output results. XOR represents the inequality function, i.e., the output is true if the inputs
are not alike otherwise the output is false.

Fig.2.1 Circuit diagram of XOR gate using CMOS

A B Y= A ⊕ B
0 0 0
0 1 1
1 0 1
1 1 0
Table 2.1 Truth Table of CMOS Inverter
Design and Simulation:

Figure 2.2 Schematic of connections of CMOS XOR-gate.

Figure 2.3 implementation of cmos XOR gate.

 Parameters Values
CMOS Technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V
Input signal (Pulse) V1=1.8V, V2=0, Time
Period=100ns, Pulse Width=50ns
Table 2.2 Design specifications of CMOS Inverter

Observation:
INPUT SIGNAL PULSE-
V1= 1.8 V, V2= 0V
Period= 100nsec, Pulse Width=50nsec

Transient Analysis:
Delay Time Calculated: 5.03111e-009

Figure 2.4 Transient result of CMOS Inverter output

Result:

• XOR-gate circuit has been successfully designed using SymicaDE tool.

• Transient and DC analysis performed also delay time is also calculated.