Date: 30/09/2020

AdvancedVLSIDesignLab(EC17203)
EXPERIMENT NO. 6

Aim: To design and Simulate 6-T SRAM using SymicaDETool .

Tool & Apparatus Used: SymicaDE

Theory: The structure of a 6 transistor SRAM cell, storing one bit of information, can be seen in
Figure 6.1 below. The core of the cell is formed by two CMOS inverters, where the output
potential of each inverter is fed as input into the other. . This feedback loop stabilizes the
inverters to their respective state.

CMOS devices have been scaled down in order to achieve higher speed, performance and lower
power consumption. SRAM means Static Random Access Memory. The SRAM cell that we
considered in this paper was 6T SRAM cell which consists of two crossly coupled inverters and
access transistors to read and write the data. In case of the SRAM cell the memory built is being
stored around the two cross coupled inverters. If we consider that, the input to the first inverter is
logic 1 then the output of this inverter will be logic 0. So, after one cycle the output of second
inverter will be logic 1.

Fig.6.1 Circuit diagram of 6T SRAM standard cell

Design and Simulation:

Fig.6.2 Schematic of 6T SRAM standard cell (for READ cycles)

Fig.6.3 Schematic of 6T SRAM standard cell (for WRITE cycles)

 Parameters Values
CMOS Technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V

Table 6.1 Design specifications used in the design

Observation:

Fig. 6.4 Transient simulation result of 6T SRAM standard cell (for READ cycles)
 Fig. 6.5 Transient simulation result of 6T SRAM standard cell (for WRITE cycles)

Result:

• The 6T (having 6 transistors per bit) SRAM standard cell (1 bit) has been successfully
designed using SymicaDE tool.
• Its transient simulation has been performed and the corresponding waveforms have been
obtained using SymSpice tool and SymProbe tool.