DESIGN AND ANALYSIS OF SOFT ERROR ROBUST AND

LOW LEAKAGE CURRENT NOVEL 13T SRAM

A DISSERTATION PRESENTATION

Supervised By: Presented By:

Dr. Navaid Z.Rizvi Isha Choudhary
13/IEC/015
 CONTENTS
• Stepwise Implementation Procedure
• Problem Identification
• Methodology of work
• Results and analysis
• Conclusion
 STEPWISE IMPLEMENTATION PROCEDURE

LEVEL 1
• Designing of 6T SRAM schematic
operating at 3V and then at 500mV
supply voltage.

LEVEL 2
• Designing of 13T SRAM using two
techniques: Dual-driven Feedback
and Stack Approach at 500mV

LEVEL 3
• Compare power, delay, SNM,
leakage current for best trade-off
SRAM Architecture
 PROBLEM IDENTIFICATION

• Transistor Scaling introduces Stability issues for Read Ability and

Write Ability.

• Voltage Scaling introduces Soft errors andRadiation Hardening.

• Working in sub-threshold region introduce sub-threshold leakage

current.
LEVEL 1: Analysis of 6T SRAM
 SRAM STABILITY
• Main purpose of SRAM is holding one bit of data. If SRAM satisfies the
stability criteria of data stability.
• To measure the data stability of SRAM cell well known method is Static
Noise Margin.
• SNM is defined as amount of allowable DC noise that can be applied to
the cell
 Butterfly curve

Fig 1: SNM butterfly graph for measuring stability

 Soft error in SRAM
• Voltage Scaling introduces Soft errors and Radiation Hardening.

• A Single Event Upset (SEU) in SRAM cell take place when a heavy charged
particle strikes a sensitive node and changes the state of the SRAM cell
causing a soft error.

• But for designs fabricated at deep sub micron technology, soft errors are
more persistent due to the alpha particles generated by unstable
isotopes which are found in the packaging materials of a chip
Schematic for Conventional 6T SRAM at 3V

Fig 2: Schematic representation of 6T SRAM

Mechanism of 6T SRAM Circuit
 Analysis of 6T SRAM at 3V

Fig 3: Transient analysis of 6T SRAM at 3V Fig 4: SNM of 6T SRAM operated at 3V

Schematic of 6T SRAM at 500mV

Fig 5: Schematic of 6T SRAM at 500mV

 Analysis for 6T SRAM at 500mV

Fig 6: Transient Analysis of 6T SRAM (READ) at 500mV Fig 7: SNM of 6T SRAM (READ) at 500mV
Layout of 6T SRAM Bit Cell

Fig 8: Layout of 6T SRAM bit cell

LEVEL 2: Analysis of 13T SRAM(Dual Driven Feedback)
Conventional 13 T SRAM Schematic at 500mV

Fig 9: 13 T SRAM(dual-driven feedback) Schematic at 500mV

Mechanism of Dual-driven Feedback technique

Fig 10: Storage mechanism for 1 and 0 state

 Analysis of 13T SRAM (dual-driven feedback)

Fig 11: Transient Response of 13T SRAM at 500mV Fig 12: Half-select functionality for both, storing 1 (cell 1) and storing 0 (cell 2)
 13T SRAM RESULTS FOR TOLERANCE TOWARDS
DAMAGE

Fig 13: 0 to 1 upset at Q Fig 14: 1 to 0 upset at Q Fig 15: 0 to 1 upset at QB1
13T SRAM RESULTS FOR TOLERANCE TOWARDS
DAMAGE

Fig 16: 0 to 1 upset at B Fig 17: 0 to 1 upset at A

 13T SRAM Circuit with dual-driven feedback

Fig 18: SNM of 13T SRAM(READ) Fig 19: Layout of 13T SRAM dual driven feedback circuit
LEVEL 3: Analysis of 13T SRAM(Stack Approach)
 Stacking Effect
• Sub threshold leakage current that is flowing through a stack of series
connected transistors decreases when more than one transistor in the
stack is turned off. This Effect is known as stacking effect or self-reverse
bias.
Schematic of Stack approach in 13T SRAM

Fig 19: Schematic of 13T SRAM using Stack Approach

Analysis of 13T SRAM using Stack Approach

Fig 20: Transient Analysis of 13T SRAM Fig 21: SNM of 13T SRAM stack approach circuit
Layout of 13T stack approach circuit

Fig 22: Layout of 13T stack approach circuit

TABLE 1: COMPARISON OF PERFORMANCE
ASPECTS OF SRAM

SRAM CELL AVG. POWER DELAY SNM LEAKAGE

CURRENT

6T SRAM 18.15µW 20.5ps 10mV 27.89nA

13T SRAM 0.901µW 30.4ps 50mV 1.20µA

EXISTING

13T SRAM 3.65nW 4.5ps 110mV 12.57nA

PROPOSED