LITERATURE SURVEY

CHAPTER 2

LITERATURE SURVEY

In the literature various architectures have been proposed. The literature review on
SRAM is analyzed and studied for the successful completion of work.

Shibata (1999) presented a high-speed and low-power SRAM, which was operated by a
single battery cell of around 1V. Its memory cells were made up of high threshold-
voltage (high-Vth) MOSFET’s in order to suppress the power dissipation due to large sub
threshold leakage currents. Low-Vth MOSFET’s were assigned for the critical paths of
memory-cell access. The leakage current in each logic gate was reduced by high-Vth
MOSFET’s, which were cut off during standby. The high-Vth MOSFET in one logic gate
can be shared with another logic gate in order to enlarge effective channel width.

Chen (2000) described, essential of voltage scaling in SRAM to reduce energy

consumption. However, commercial SRAM was prone to functional failures when Vdd
was scaled. Several SRAM designs scale Vdd to 200-300mV to minimize energy per
access, but these designs do not consider SRAM robustness, limiting them to small arrays
and sensor type applications. Here the effects on area and energy for a differential 6T,
single-ended 6T with power rail collapsing and an 8T bit cell as scaled Vdd and the bit
cells were sized appropriately to maintain robustness. SRAM robustness was examined
using importance sampling to reduce simulation runtime.

Murakami (2002) analyzed a single-bit-line cross-point cell activation (SCPA)

architecture, which has been developed to reduce active power consumption and to avoid
increase in the size of high-density SRAM chips, such as 16-Mb SRAM's and beyond. A
new PMOS precharging boost circuit, introduced to realize the single-bit-line structure,
was also discussed. This circuit was suitable for operation under low-voltage power
supply conditions. The SCPA architecture with the new word-line boost circuit was
demonstrated with the experimental device, which was fabricated by a 0.4-µm CMOS
wafer process technology.

Flautner et al. (2002) presented on-chip caches, a sizable fraction of the total power
consumption of microprocessors. Although large caches can significantly improve

23
 LITERATURE SURVEY

performance, they have the potential to increase power consumption. As feature sizes
shrink, the dominant component of this power loss will be leakage. However, during a
fixed period of time the activity in a cache is only centered on a small subset of the lines.
This behavior can be exploited to cut the leakage power of large caches by putting the
cold cache lines into a state preserving, low-power drowsy mode. About 80%-90% of the
cache lines can be maintained in a drowsy state without affecting performance by more
than 1%. According to our projections, in a 0.07um CMOS process, drowsy caches will
be able to reduce the total energy (static and dynamic) consumed in the caches.

Elakkumanan et al. (2003) presented a novel N-Controlled SRAM (NC-SRAM) design

for reducing the leakage in cache. It described combine the use of high Vt transistors in
the leakage path and gating the supply voltage to reduce leakage in unused SRAM cells.
This circuit-level technique overcomes the potential limitations in the existing techniques
for reducing leakage in memory circuits. In this design, the data stored in the cell was
retained even when the memory was put in the stand-by mode, with no additional
complexity. Simulation results indicate that NC-SRAM has better leakage savings with
very minimal impact on performance and area, as compared to a conventional 6T-SRAM.

Azizi et al. (2003) reported a novel family of asymmetric dual static random access
memory cell designs that reduce leakage power in caches while maintaining low access
latency. The designs exploit the strong bias toward zero at the bit level exhibited by the
memory value stream of ordinary programs. Compared to conventional symmetric high-
performance cells, proposed cells offer significant leakage reduction. A novel sense
amplifier, in combination with dummy bit lines, allows for read times to be on par with
conventional symmetric cells. With one cell design, leakage was reduced with no
performance degradation, but with a stability degradation of 6%. Another cell design
reduces leakage with no performance or stability loss.

Navid et al. (2003) presented a novel family of asymmetric dual static random access
memory cell designs that reduce leakage power in caches while maintaining low access
latency. Compared to conventional symmetric high-performance cells, our cells offer
significant leakage reduction in the zero state and, in some cases, also in the one state,
albeit to a lesser extent. A novel sense amplifier, in combination with dummy bit lines,
allows for read times to be on par with conventional symmetric cells. With one cell
design, leakage is reduced with no performance degradation, but with a stability

24
 LITERATURE SURVEY

degradation of 6%. Another cell design reduces leakage with no performance or stability
loss.

Kanda (2004) described a low-power write scheme which reduces SRAM power by 90%
by using seven-transistor sense-amplifying memory cells. By reducing the bit line swing
to Vdd/6 and amplifying the voltage swing by a sense-amplifier structure in a memory cell,
the charging and discharging component of the power of the bit/data lines was reduced. A
64-kb test chip has been fabricated and correct read/write operation has been verified. It
was also shown that the scheme can also have the capability of leakage power reduction
with small modifications. Achievable leakage power reduction was estimated to be two
orders of magnitude from SPICE simulation results.

Mazhari (2005) presented the impact of gate leakage on SRAM and two approaches for
reducing gate leakage currents were examined in detail. In one approach, the supply
voltage was reduced while in the other the potential of the ground node was raised. In
both the approaches the effective voltage across SRAM cell was reduced in inactive mode
using a dynamic self controllable switch. Simulation results based on BPTM (Berkeley
Predictive Technology Model) for 45nm channel length device show that the scheme in
which supply voltage level was reduced was more efficient in reducing gate leakage than
the one in which ground node potential was raised. Results obtained show that 96%
reduction in the leakage currents of SRAM can be achieved.

Bhavnagarwala and Kosonocky (2005) described fundamental limitations on scaling

CMOS SRAM cell transistor dimensions and operating voltages were demonstrated by
measuring the local stochastic distributions of Read, Write and Retention DC margins of
65nm PDSOI CMOS SRAM cells. DC measurements show, for the first time, the write
operation to be more fluctuation limited. Measurements also reveal fundamental insights
into terminal voltage dependencies of the fluctuations of cell storage node voltages -
observations that were engaged to increase cell immunity to fluctuations by several orders
of magnitude by biasing the cell terminal voltages appropriately.

Lung (2006) presented a new current-mirror sense amplifier(CMSA) design for high-
speed static random access memory (SRAM) applications .The proposed CMSA can
directly sense the current of memory cell and only needs two transistor stages cascaded
from VDD to GND for achieving the low-voltage operation. Moreover, the sensing speed
of the proposed CMSA was independent of the bit-line capacitances and was only slightly
25
 LITERATURE SURVEY

sensitive to the data-line capacitances. The proposed CMSA can effectively work at 500
MHz–1 GHz with working voltage as low as 1.5V.

Kosonocky et al. (2006) described CMOS technology approaches the limits of scaling,
device dimensions become similar in magnitude to the discrete structures and components
of the device itself. Random process variations quickly were becoming a major limitation
to limiting manufacturing yields. The 6T-SRAM cell has become the first casualty to
these scaling effects, and has increased in size relative to larger logic components in
recent technology nodes. Physical and electrical modifications to the SRAM cell and
peripheral circuits can provide additional tolerance and allow continued scaling into the
foreseeable future. This paper examines this issue and suggests some alternative
structures that have been demonstrated to provide improvements.

Grossar et al. (2006) described SRAM cell read stability and write ability were major
concerns in nanometer CMOS technologies, due to the progressive increase in intra-die
variability and scaling. This paper analyzes the read stability N-curve metrics and
compares them with the commonly used static noise margin (SNM). Additionally, new
write-ability metrics derived from the same N-curve are introduced and compared with
the traditional write-trip point definition. It was demonstrated that the new metrics
provide additional information in terms of current, which allows designing a more robust
and stable cell. Finally, these metrics were used to investigate the impact of the intra-die
variability on the stability of the cell by using a statistically-aware circuit optimization
approach and the results were compared with the worst-case or corner-based design.

Morifuji and Horowitz (2007) analyzed that there was a strong demand for smaller cell
size, higher speed, and lower power in SRAMs. There were many constraints for reliable
read-and-write operations, to understand these tradeoffs clearly and find a power-delay
optimal solution for scaled SRAM; sequential quadratic programming was applied for
optimizing 6-T SRAM for the first time. Results suggest that, for optimal SRAM cell
design, neither the supply voltage (Vdd) nor the gate length scales, due to the need for an
adequate noise margin and relatively low dynamic activity of SRAM. The cell area
continues to scale despite the nonscaling gate length with only a 7% area overhead at the
22-nm technology node as compared to simple scaling. The suppression of gate leakage
helps to reduce the power in ultralow power SRAM.

Iijima and Seto (2007) presented a SRAM memory cells derived from aggressive
26
 LITERATURE SURVEY

technology scaling which has recently been one of the most significant issues. Although a
7T-SRAM cell with an area tolerable separated read port improves read margins even at
sub-1V, it unfortunately results in degradation of write margins. A 7T-SRAM with an
area-tolerable separated read port improves read margins and therefore seems one of the
candidates in deep sub-100 nm, it still has a difficulty of deteriorated write margins. The
proposed memory cell adopted a look-ahead body-bias which dynamically controls the
threshold voltage in order to assist the write operation. Simulation results have shown
improvement in both the write margins and access time.

Liu et al. (2007) described deep submicron technologies, limiting the growing on-chip
power consumption in memories was a major challenge for SoC designers. Accurate
modeling of power, early in the design stage was thus crucial for system level power
estimation. An enhanced cache memory simulator that models leakage reduction
techniques such as the dual-V t, dual- TOX, NC-SRAM, and gated- Vdd techniques which
can be applied to the SRAM cell structure to reduce the overall leakage power. The
power/speed trade-offs associated with each leakage reduction technique, at the system
level using a cycle-accurate processor simulator was also examined. Cache leakage thus
helps in choosing the right memory configurations. Simulation results show a trade-off
between power and low performance overhead.

Tawfik and Kursun (2008) presented four circuit techniques for high data stability and
low leakage power consumption. The techniques that provide the highest data stability,
the lowest leakage power consumption, and the smallest memory cell area were
identified. The first circuit technique employs a dynamic voltage swing word line driver
to control the operation of the standard six-transistor memory cells. The other three circuit
techniques tackle the data stability challenge by modifying the memory cell circuit
structure. A 9T, 8T, and 7T SRAM circuit were considered in this work. The data storage
nodes were isolated from the bitlines with these techniques, thereby significantly
enhancing the read stability as compared to the standard 6T SRAM circuits. Among the
evaluated memory circuits, the 9T and the 8T SRAM cells provide the highest data
stability during a read operation. The read stability of the 9T and the 8T SRAM cells is
80% higher as compared to a standard 6T SRAM cell.

Amelifard (2008) analysed aggressive CMOS scaling in low threshold voltage and thin
oxide thickness. As a result, reducing the sub threshold and tunnelling gate leakage

27
 LITERATURE SURVEY

currents has become one of the most important criteria in the design of VLSI circuits.
This paper presented a method based on dual- and dual- ox assignment to reduce the total
leakage power dissipation of static random access memories (SRAMs) while maintaining
their performance. The proposed method was based on the observation that read and
writes delays of a memory cell in an SRAM block depend on the physical distance of the
cell from the sense amplifier and the decoder. Thus, the idea was to deploy different
configurations of six-transistor SRAM cells. Unlike other techniques for low-leakage
SRAM design, the proposed technique incurs neither area nor delay overhead.

Wang el al. (2008) analyzed write ability for SRAM cells in deeply scaled technologies,
focusing on the relationship between static and dynamic write margin metrics. Reliability
has become a major concern for SRAM designs in modern technologies. Both local
mismatch and scaled VDD degrade read stability and write ability. Several static
approaches, including traditional SNM, BL margin, and the N-curve method, can be used
to measure static write margin. However, static approaches cannot indicate the impact of
dynamic dependencies on cell stability. Dynamic write ability as the critical pulse width
for a write was also defined. By using this dynamic criterion, the existing static write
margins metrics at normal and scaled supply voltages and assess their limitations were
evaluated.

Chiang and Chang (2009) presented a new six-transistor static random access memory
(6T SRAM) cell with significantly reduced power consumption that achieves high read
and write performance. Unlike traditional 6T SRAMs, this study proposes an asymmetric
6T SRAM which uses a single line to implement read or write operations without
reducing performance. This design not only reduces power consumption, but also
improves read and write performance. The proposed SRAM design was implemented
with UMC 90nm, 1.0-V supply voltage CMOS technologies. Compared to conventional
six transistor SRAM cells, the new cell design successfully reduces power consumption
by 40-60%. In addition, the read and write performance has been improved by 13.6% and
41.2%.

Athe and Dasgupta (2009) analyzed that data retention and leakage current reduction
was among the major area of concern in CMOS technology. In this paper 6T, 8T and 9T
SRAM cell have been compared on the basis of read noise margin (RNM), write noise
margin (WNM), read delay, write delay, layout and parasitic capacitance. Both 8T SRAM
cell and 9T SRAM cell provides higher read noise margin (around 4 times increase in
28
 LITERATURE SURVEY

RNM) as compared to 6T SRAM cell. Although the size of 9T SRAM cell is around 1.35
times higher than that of the 8T SRAM cell but it provides higher write stability. The data
retention voltage for 8T SRAM cell was found to be 93.64mV while for 9T SRAM cell it
was 84.5mV and for 6T SRAM cell it was 252.3mV. Read delay for 9T SRAM cell was
98.85ps while for 6T SRAM cell it is 72.82ps and for 8T SRAM cell it was 77.72ps.
Write delay for 9T SRAM cell was found to be 10ps, 45.47ps for 8T SRAM cell and
8.97ps for 6T SRAM cell.

Moradi1 et al. (2009) reported a new technique to increase the write margin of 6T-
SRAM cell. Using this technique the area of sub threshold SRAM cell was reduced and
also the Write cycle was improved significantly with a lower area overhead. In this
technique, PMOS stacked network was used to evaluate the write cycle. Based on
behavior of devices in 65nm for weak inversion operation, this technique was proposed to
decrease area overhead of 6T-SRAM in sub threshold region. PMOS transistors as a pass
transistor and also in write path was much better compared to using NMOS transistors.
Results showed significant improvement in write SNM with a lower area compared to
standard 6T-SRAM cell using proposed circuit the WRITE static noise margin is
improved by around 50% for TT CMOS model.

Dasgupta and Athe (2009) analyzed 6T, 8T and 9T SRAM cell on the basis of read noise
margin (RNM),write noise margin (WNM), read delay, write delay, data retention voltage
(DRV), layout and parasitic capacitance . Statistical simulation of the noise margin has
been carried out to analyze the effect of intrinsic parameter fluctuations. Both 8T SRAM
cell and 9T SRAM cell provides higher read noise margin (around 4 times increase in
RNM) as compared to 6T SRAM cell. Although the size of 9T SRAM cell is around 1.35
times higher than that of the 8T SRAM cell but it provides higher write stability. Write
delay for 9T SRAM cell was found to be 10ps, 45.47 ps for 8T SRAM cell and 8.97ps for
6T SRAM cell. The simulation has been carried out on 90nm CMOS technology.

Tseng el al. (2010) presented conventional SRAMs, namely four-transistor SRAM (4T)
and six-transistor SRAM (6T) which suffered from the external noise, because they have
direct paths through bit-line (BL) to their storage nodes. This paper proposed a seven-
transistor (7T) SRAM which has no direct path through BL to the data storage nodes and
has higher endurance against external noise. The proposed cell was composed of two
separate data access mechanisms; one was for the read operation and another was for the
write one. Based upon our SRAM design, data destruction never occurs in the read
29
 LITERATURE SURVEY

operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the
proposed cell was enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM
cell respectively.

Christiensen D.C. Arandilla el al. (2011) presented the factors that affect the Static Noise
Margin (SNM) of a 6T Static Random Access Memory (SRAM) cell designed in 90-nm
CMOS. In this paper, the SRAM cell is simulated and noise margins are obtained while
varying several parameters that affect SRAM operations. These parameters are
temperature, threshold voltage, supply voltage, cell ratio, pull-up ratio, and process corner
variations. The simulation results were found to be in agreement with the model derived by
Seevinck et al. which is based on the square law device model.

Satyendra Kumar el al. (2013) presented data stability of Static Random Access Memory
(SRAM) cell is a major issue in deep submicron CMOS technology. In this paper, a novel
twelve transistor (12T) SRAM cell is proposed. The proposed cell demonstrates SNM free
read operation and an enhanced static noise margin (SNM) for hold mode of the cell. The
12T SRAM cell is designed such that during the read operation, the switching threshold
voltage (VTRIP ) of the inverter storing logic `1' becomes high enough, which ensures that
the cell does not flip even if a high amount of noise is injected on to the storage node
storing logic `0'. The cell also provides better values for write margin. The simulations
have been carried out on 45nm technology node with process parameter variations.

Anupreet Gupta el al. (2014) suggested the very important factors of merits of Static
random access memory (SRAM) i.e. static noise margin (SNM) and total power
consumption in 6T, 8T and 5T SRAM cells designed at 65nm UMC CMOS technology is
done. The work includes a vivid description of the factors like applied voltage (Vdd) and
different process corners affecting the SNMs and power consumption variations along with
the simulations. The simulations are well in agreement with the expectations based on the
different cell structures and their functionalities.

G. Surekha el al. (2016) presented static noise margin (SNM) of a low threshold voltage
and power of 7T SRAM cell is computed using 90nm CMOS Technology on cadence
Virtuoso Tool. Significant contribution of this work is noise margin and it is obtained for
various SRAM control operations such as write, hold and read operations. The results of
the 7T SRAM Cell are compared with standard 6T SRAM cell in terms of noise margin
and power consumption. The experimental results show improved performance of static
30
 LITERATURE SURVEY

noise margin for 7T SRAM Cell over 6T SRAM Cell at reduced power consumption.

D. S. Chauhan el al. (2017) described electronics industry is facing the major problem of
standby leakage current in most of the electronic devices. As the speed of processor is
increasing, the demand for high-speed cache memory is ever increasing. SRAM being
mainly used for cache memory design, several low-power techniques are being used to
reduce its leakage current. Full CMOS 6T SRAM cell is the most preferred choice for most
of the digital circuits. This paper implements 6T CMOS SRAM cell using MTCMOS
technique and simulation results show significant reduction in leakage during standby
mode. The simulations are done on Cadence Virtuoso Tool using 45 nm technology.

Bhawna Rawat el al. (2018) presented a novel 7T SRAM cell, which has improved static
and dynamic performance matrix at supply voltage as low as 300mV. The proposed bit cell
has single ended write and double ended read operation. The proposed cell improves the
read static noise margin, hold static noise margin and write margin by 20%, 24% and 10%
respectively when compared with conventional 7T bit cell structure. In comparison to 6T
conventional structure the proposed cell has 76% improvement in hold noise margin and
26% improved write margin. The conventional 6T SRAM bit cell fails to perform read
operation below 600 mV, whereas the proposed cell maintains a read static noise margin of
47 mV at 300mV supply voltage. The proposed cell is simulated for 32nm technology node.

31