‫بسمه تعالی‬

‫پروژه پردازشگر های سیستم های الکترونیک دیجیتال‬

SRAM is an important building block in computing systems that

consumes significant fraction of power. Major share of the static power consumption is attributed to the
SRAM as they occupy more than 50%of the chip area [1,2]. In the present scenario, low power
applications like wireless sensor nodes, implantable biomedical devices and other battery operated
portable devices require ultra-low leakage power SRAM cell. One of the popular solutions to reduce
leakage and active power is to operate SRAM in near/sub-threshold region. However, increased
variation in modern scaled technology puts a major challenge in the SRAM design at lower operating
voltages [3]. σVth of devices has increased significantly with continuous scaling of the device
geometry[4]. Consequently, Read/Write failure probability has significantly increased due to the
difficulty in maintaining the Cell-ratio and Pull-upratio in conventional 6T SRAM cell. Many circuit
techniques have been proposed to decouple the read/write path [5–12] to address these issues in
conventional 6T SRAM cell. Decoupling read/write path improvesthe cell stability and also improves
VDD,min that can be exploited to reduce the static leakage power significantly [11,12].

The soft-error is one of the key issues in SRAMs and is more problematic in subthreshold regime due to
the reduction of critical charge, QC [13]. As technology advances, the decreased storage node area
mitigates the chances of single-event upsets (SEUs), which is soft-error per memory bit [14]. However,
with the technology scaling, the effective distance between transistors decreases, which increases the
chances of simultaneous errors in more than one memory cell induced by a single ion strike resulting in
multiple-cell upsets (MCUs). Thus,MCUs in SRAMs due to ion strikes have increased significantly, in spite
of decrease in SEU per bit [14,15]. Fig. 1 shows the increasing trend of ratio of MCUs to SEUs as a
function of technology node [15]. The checkerboard signifies the bit pattern of consecutive 1’s and 0’s.
This poses a serious threat to the functionality of SRAMs since MCUs cannot

be recovered by conventional Error Correction Schemes as they can

detect and correct only single bit errors. Bit-interleaving technique is

used to deal with these errors efficiently. However, use of bitinterleaving architecture results into Half
Select (HS) issue in most of the SRAM cells [16]. While the existing works address the read/write stability
of the selected cell, stability issues in column/row HS cells has not been fully addressed. In most of the
recent work, HS issue is handled by techniques such as write-back [5,17,18], array architecture approach
[19–21], local write wordline [22], and hard-coding [23,24] etc. that incur power and performance
penalties. Recently 12T bit-interleaving cell, BI12T [13] and a power gated 9T cell, PG9T [25] have been
proposed to solve the HS issue without using these techniques. However, BI12T suffers with very precise
WL pulse requirement to mitigate the degradation of floating data at storing nodes Q or QB in column
HS cells during write operation. Similarly, PG9T cell also suffers from floating storage node in row HS
cells. It also suffers with poor write-ability and longer write delay due to stacked transistor and
conflicting charging and discharging of internal node between the access transistors while writing ‘0’.
Therefore, in this work, we present a 12-transistor pseudo differential SRAM cell (PD12T) that is fully
halfselect free thus doing away with the write-back or any other assist techniques and supports a bit-
interleaving architecture to improve MCUs immunity. The proposed cell also improves write-ability
without

using additional peripheral write-assist circuits. Furthermore, the proposed cell requires only
unidirectional current flow through transistors; and hence. it is also suitable for all-TFET
implementation. The rest of this paper is organized as follows. In Section 2, cell structure and
functioning of PD12T is discussed. Section 3 presents the simulation setup, results and comparison of
the SRAM cells considered in

Fig. 2 shows the schematic diagram of the proposed PD12T SRAM

cell. The PD12T cell consists of a cell core (cross coupled inverter along with power cutoff switches
MPL1, MPL2, MPR1 and MPR2), read access path consisting of two transistors (MR1 and MR2) and
write-access path consisting of three transistors (MAL, MAR and MD). The transistor MD, which is
shared in a row, provides discharging path for storage nodes during the write operation. Table 1
illustrates the control signals in different modes of operation of the PD12T SRAM cell.

21

Read operation During read operation, RWL is kept at ‘1’ whereas all other control signals are grounded.
This provides discharging path for prechargedRBL through transistors MR1 and MR2 depending on the
data stored at QB. The column-based RWLB signal is utilized to eliminate bitline leakage in the read path
of the unselected columns, which reduces the overall energy consumption. The disabled WLA, WLB and
WWL signals makes data storage nodes (Q and QB) completely isolated from any disturbing path during
the read access. Therefore, the read static noise margin (RSNM) of the PD12T cell is same as its hold
SNM like that in conventional 8T cell. However, conventional 8T is not HS free.

2.2

Single-ended write [9,23,26,27] reduces the leakage and switching

power while incurs penalty in terms of increased write-access time and degraded write margin (WM). In
fact, it requires some assist techniques such as dual Vth [5], asymmetric write assist [23,26], power-
cutoff [27] for good write-ability. On the other side, differential write cells such as 6T, CONV8T consume
significant Bitline switching power, but improve write performance. In the proposed cell, the write-
ability is as good as of differential write cells, whereas active power is as low as that of single-bitline
cells. The write operation in PD12T cell is, in fact, singleended, but it involves only writing of ‘0’ similar to
differential write. The Write ‘0’ or Write ‘1’ operation are accomplished by writing ‘0’ at node Q or QB
respectively. Fig. 3 illustrates the write ‘0’ operation in the selected cell along with row and column half-
selected cells. The WWL and WLA are kept at ‘1’ whereas WLB is grounded. The left inverter of selected
cell is completely cut-off from power supply and node

Q is easily discharged through transistors MAL and MD. Similarly for

write ‘1’, the WWL and WLB are‘1’ whereas WLA is kept at ‘0’. The

supply is now cut-off for right inverter and node QB is discharged easily through MAR and MD.
Consequently ‘1’ is written at node Q. Since, for either write operation, only one write path is active,
therefore, we call it pseudo differential write operation.

3.1

We use HSPICE and 16 nm CMOS Predictive Technology Model [28]

for the analysis and comparison of the proposed SRAM cell. As we havediscussed, the proposed cell
operation is not limited to read-write conflict sizing requirement, we have used minimum sized devices
for the cell core (24 nm width for both PU and PD transistors) to minimizethe area and leakage
overhead. However, we have upsized accesstransistors (36 nm width for both read and write access
transistors) to reduce the delays. Since in deep submicron technology, impact of process variations is
significant [29]; therefore, we perform MonteCarlo simulations with a sample size of 5000 to analyze the
impact of process variations on the cells considered in this work. To simulate the impact of local
variations, we take into account the variations in channel length (L), channel width (W), channel doping
concentration (NDEP), and oxide thickness (Tox). All these parameters are assumed to have an
independent normal Gaussian distribution with 3σ variation of 10% [21]. On top of it, to reflect the
impact of global variations, we

incorporate 20% variation in threshold voltage (Vth) and 10% variation in supply voltage (VDD) [30]. We
extract and compare the different performance parameters of the proposed SRAM cell with some
existing SRAM cells such as 6T, Conventional 8T (CONV8T), CHANG10T [9], BI12T [13] and ST-2 cell [31],
in the following sections.

3.2

Hold SNM or HSNM is a measure of the stability of the SRAM cell in

standby mode. It is defined as the maximum value of DC noise voltage that can be sustained by an SRAM
cell without altering the stored bit during hold mode [28]. Fig. 4(a) shows the conceptual test setup used
for SNM measurement for 6T SRAM cell. The bitlines are kept at VDD, where as WL is kept at ‘0’. The
node N1 and N2 represents the noise sources at QB and Q nodes, which are affecting the opposite node
Q and QB. The N1 is swept from 0 to VDD to measure voltage at Q, which is plotted in Fig. 4(b) (curve-I).
Similarly, N2 is swept from 0 to VDD to measure voltage at QB. Now QB is plotted in the same graph by
exchanging the axis (N2 as y-axis and QB as x-axis, as in curve-II). The resulting graph is a butterfly curve
as shown in Fig. 4(b). The HSNM is determined by the length of the side of the largest square that can be
inscribed between these two curves. The HSNM of PD12T is marginally better than 6T because of
stacked PMOS transistors. HSNM is best for ST-2 because of the use of Schmitt-trigger inverter that has a
better voltage transfer characteristics. The HSNM distribution plot of PD12T is depicted in Fig. 4(c). It is
observed that the minimum value of HSNM for PD12T cell is higher than all other cells. Fig. 4(d) plots the
temperature dependence of HSNM and it is observed that the change in temperature affects hold
stability equally

3.3

The proposed cell uses separate read buffer for read operation and

hence ‘read upset’ problem is of no concern and the read stability is

same as the hold stability. The read stability of an SRAM cell is determined in terms of Read SNM
(RSNM), which is graphically estimated as the length of a side of the largest square that can be
embedded inside the smaller lobe of the butterfly curve [32]. The RSNM is measured by following the
same procedure as discussed for HSNM, except that the WL is now activated (read condition for 6T cell).
Fig. 5(a) plots the RSNM of several SRAM cells at different supply voltages. The proposed cell has
significantly higher RSNM as compared with the conventional 6T and ST-2 cells. This is attributed to the
completely isolated cell core during read operation. Monte Carlo simulation results for 5000 samples at
VDD = 0.35 V are presented for the measurement of RSNM in Fig. 5(b). It confirms the robustness of the
proposed cell against process variations. We observe that the proposed cell offers 50% improvement in
the mean value of RSNM as compared with the ST-2 cell. When compared with CHANG10T and BI12T
cells, the PD12T cell gives1.14× and 1.1× larger value of mean RSNM.

3.4

The write-ability of an SRAM cell can be gauged in terms of Write

Margin [33]. In recent studies, it has been shown that the Write Margin technique is more appropriate
(as compared to traditional VTC SNM approach) to measure the write ability of an SRAM cell. In this
technique, data to be written is applied on the bitlines and then wordline (WL) is swept from 0 V to VDD
that replicates a real write operation. The Write Margin (WM) is defined as the difference between VDD
and WL voltage at which the nodes Q and QB flip [33]. A higher value of WM indicates the ease of
writing into the cell. Fig. 6(a) plots the WM for several SRAM cells at different supply voltages. The two
WMs for write ‘0’ and write ‘1’ are same for differential cells. The BI12T and PD12T cells show higher
WM than all other cells, which is attributed to the use of power cutting technique during node
discharging. However, PD12T

cell uses only two transistors in the discharging path, as discussed in section 2, in comparison of three
transistors in case of BI12T, which further improves the WM of the proposed cell. The CHANG10T cell
bshows worst WM because of its two series connected access transistors, makes it necessary to use
wordline boosting technique. Monte Carlo simulation results for 5000 samples at VDD = 0.35 V indicate
that the WMs of PD12T and BI12T cells are lesser susceptible to process variations as shown in Fig. 6(b).
This is because of the power cut-off technique used in these cells. It is also observed that the WM of
cells are only marginally affected by the temperature. Therefore, it is clearly seen that the PD12T cell
offers best WM among all the cells considered in this work.

3.5

Read access time or read delay (TRA) is the time duration between

the RWL activation to the instant when the ‘RBL’ voltage is discharged by 50 mV from its initial high level
value [34]. For the differential read SRAM cell, the 50 mV differential between ‘BL’ and ‘BLB’ is good
enough to be detected by a sense amplifier, thereby avoiding misread [34]. However in case of single
ended read, TRA is the time required for discharging the bitline voltage to (VDD – 50 mV) after the
activation of word line during a read operation [7]. Fig. 7(a) compares the TRA of PD12T cell with other
SRAM cells. The CONV8T, CHANG10T, BI12T and PD12T cells have similar read path; therefore, TRA is
found to be almost same for these cells. The small difference in the Read Delay ofthese cells is because
of the difference in parasitic capacitances at the intermediate nodes. The ST-2 and 6T cells have longer
delay because of the smaller read current and hence they require longer time (TRA) for discharging the
bitline. Write access time or write delay (TWA) for writing ‘1’ is estimated as the time duration between
the WWL activation time to the time when a ‘0’ storing node charges up to 90% of VDD. Similarly, TWA
for writing ‘0’ is estimated as the time duration between the WWL activation time to the time when a ‘1’
storing node discharges to 10% of VDD. For differential write, these two TWA are same. Fig. 7(b) shows
TWA of SRAM cells estimated at different values of supply voltages. The BI12T and PD12T cells have
relatively higher TWA as compared to 6T, CONV8T, CHANG10T and ST-2, since they incorporate two
stacked transistors in the pull-up path while charging the opposite node. Further, PD12T shows slightly
higher TWA than BI12T cell because the writing is not fully differential as in case of BI12T cell.

3.6

Fig. 8(a) depicts the plot of read power for various SRAM cells at

different supply voltages. There is always a trade-off between power

and delay. That is why, read power for ST-2 and 6T is smaller; while the cells like CONV8T, CHANG10T
and PD12T consume higher power during read operation. Fig. 8(b) plots the write power of SRAM cells
for a range of supply voltages. The proposed PD12T cell consumes least write power at all the supply
voltages among the considered cells due to pseudo-differential write scheme which is already explained
in Section 2. It is observed that, the PD12T cell shows 53% reduction in the write power as compared to
6T cell at 0.5 V supply voltage. At the same supply voltage, it consumes only 0.41× and 0.79× write
power with respect to CHANG10T and BI12T cells.

3.7

Leakage power contributes largely to the total power dissipation in

an SRAM cell because a major part of the cache remains in standby

mode for most of the time [35]. As technology scales to nanometer

regime, the subthreshold leakage in embedded memory becomes a

serious issue [36]. Fig. 9(a) plots the leakage power for SRAM cells at different supply voltages. It is
observed that the PD12T cell along with BI12T cell offers least leakage power at all supply voltages. This
is due to the stacked transistors in the read/write path as well as in the cell core which is the major
contributor of the leakage. The RWLB signal of PD12T is high in the hold mode, which significantly
reduces the leakage in the read path. It is a useful practice to operate SRAM cells at their minimum
supply voltage, VDD,min in the standby mode in order to reduce the static power [7]. Fig. 9(b) plots the
mean and standard deviation of leakage power of SRAM cells at their VDD,min, in the presence of local
and global process variations, which is determined by MC simulation with 20,000 samples at
temperature 50 °C and at FF worst case leakage corner. It is observed that the PD12T cell consumes
least mean leakage power that is only 7% of what is consumed by 6T cell. The PD12T cell shows
marginally higher leakage power as compared to

BI12T cell at higher supply voltages. However, it is shown that, it

consumes only 0.9× mean leakage power at VDD,min as compared with BI12T cells. At the same time, it
consumes 47% lesser leakage power as compared with CHANG10T cell. The least leakage power
characteristic of the proposed cell holds potential to significantly reduce the overall power consumption
of embedded memories.

3.8

Number of SRAM cells that can be connected to a given bitline in an

array is often dictated by the Ion/Ioff ratio of the read path of that cell[7]. Fig. 10 plots the Ion/Ioff ratio
for several SRAM cells at different supply voltages. We measure the Ion as the average current during
read access time for a cell and Ioff through access transistor in hold mode. It is clear from Fig. 10 that the
proposed SRAM cell is second best from Ion/Ioff ratio point of view. As compared to 6T SRAM, PD12T
offers more than 10× higher Ion/Ioff ratio for the read path at 0.7 V. This is because of the use of RWLB
control signal in the read path.

3.9

To exploit the advantage of voltage scaling for low power design, it is very important to design SRAM cell
that can successfully operate at lower supply voltages. The minimum supply voltage (VDD,min) of an
SRAM cell is the voltage at which HSNM and RSNM is at least 26 mV and Write Margin is positive [34].
VDD,min of an SRAM cell is defined as follows

compares the estimated VDD,min for the SRAM cells along

with the parameter that limits VDD,min for these cells. It is observed that the proposed PD12T cell offers
minimum value of VDD,min among all the considered cells. When compared with 6T cell, PD12T cell
successfully operates at 65% smaller VDD. This is because of the improvement in the RSNM, HSNM and
WM of the proposed cell. Smaller value of VDD,min holds great potential towards saving of leakage
power and thus overall power consumption.

3.10

Soft error in SRAM cell occurs when a high energy particle from

cosmic radiation or chip packaging materials causes enough of a charge disturbance to flip the data of
the storage node. SRAMs designed using eep submicron technology are highly susceptible to soft errors
due to small critical charge attributed to the smaller node capacitances and lower supply voltages [37].
The soft error tolerance of an SRAM cell can be evaluated from its critical charge, Qcrit, which is defined
as the minimum amount of charge, collected by storage node during the particle strike, that is sufficient
to flip the data bit stored in an SRAM cell. As shown in Eq. (2), soft error rate (SER) has exponential
dependency on Qcrit [38]. Therefore, a higher value of Qcrit translates into lower SER

2 eq

where Nflux is the intensity of the neutron flux, A is the cross section

area of the node and Qs is the charge collection efficiency of the device, in fC. From the above relation,
it is evident that, even a small increase in Qcrit, will lead to significant reduction in SER.

We estimate Qcrit of an SRAM cell by circuit simulation using double exponential current source model
[39] for the charge collection. A current pulse, Iinj is injected to the node (Q and QB in Fig. 11) that is hit
by the high energy particles. In a series of runs of simulations, the amplitude of injected current pulse,
shown in Fig. 12(a), is varied in order to find the minimum magnitude of Ipeak and duration (Tcrit) at
which the stored bit flips. Qcrit is then computed by integrating the injected current up to the time
when the cell node voltages cross each other [40]. The injected pulse is given by Eq

3eq

Here, Ipeak is the current pulse amplitude, τr is the rising time constant and τf the falling time constant.
The injected pulse has short rise time and a long fall time. We have used a typical value of 1 ps and 50 ps
for rise time and fall time respectively as suggested in [40]. Assuming that 6T SRAM cell stores ‘0’ and ‘1’
at node Q and QB respectively as shown in Fig. 11(a). When the particle strikes at node QB, the drain of
MNR collects the charge. When this charge is sufficient enough to produce a current more than the pull-
up current of MPR, QB undergoes a transition from ‘1’ to ‘0’. To mimic this process, the current pulse Iinj
is applied in such a way that it draws the current from ‘1’ storing node QB. Similarly, when the particle
strikes at node Q, as shown in Fig. 11(b), the charge is collected by the drain of pull-up device MPL.
When the collected charge is sufficient enough to produce a current that overcomes the pull-down
current of MNL, node Q moves from ‘0’ to ‘1’. Therefore, in order to mimic this process, the current
pulse is applied in such a way that it supplies the current to node Q. Since the carrier mobility of a PMOS
transistor is smaller than NMOS transistor, node storing ‘1’ is weaker and more susceptible to soft errors
than the node storing a ‘0’ [22]. This implies that node storing ‘1’ (QB) has a smaller critical charge.
Therefore, for a given cell voltage, we refer the critical charge of node QB as Qcrit of the SRAM cell.Fig.
12(b)

shows the critical charge of SRAM cells computed at VDD = 0.7 V and 0.35 V. It is observed that the
proposed PD12T cell shows highest critical charge among the considered cells. The normalized value of
Qcrit with respect to 6T cell is also presented in Fig. 12, which shows that PD12T cell achieves 15% and
18% improvement in Qcrit over 6T cell at VDD = 0.7 V and 0.35 V respectively. At the same time, BI12T
cell shows 9% and 6% lower Qcrit. The addition of PMOS switch in pull-up path in BI12T causes the pull-
up current responsible for maintaining ‘1’ to degrade significantly, while the node capacitance remains
almost same. Consequently, the node storing ‘1’ becomes weaker and the Qcrit of BI12T is lower as
compared to other cells. Whereas, in the case of proposed PD12T cell, addition of two parallel PMOS
switches in the pull-up path, too weaken the pull-up path, however the node capacitance increases
significantly. Therefore, PD12T cell achieves higher Qcrit

as compared to other cells. For all the cells considered in this work

except CONV8T and PD12T, Qcrit is same for both the data pattern (Q = 1, QB = 0 or Q = 0, QB = 1) due
to symmetry in configuration.

However, in CONV8T and PD12Tcell, one of the transistors in the read buffer is driven by node QB,
which increases its node capacitance. Therefore, Qcrit for Q = 0 is higher (20% and 25% higher in PD12T
cell compared with 6T) as compared to the opposite case. However, this paper reports the worst case
Qcrit, which is for the case of Q = 1 for these two cells.

3.11

SRAM cells usually have the lowest Qcrit among all other memory

elements, and subsequently experience the highest number of SEU and MCU [41]. Moreover, with
technology scaling, the occurrence of multibit errors or MCUs increases significantly. Since conventional
Error Correction Schemes can detect and correct only single bit errors, multibit errors are more
threatening. Bit- interleaving (BI) technique, as shown in Fig. 13, is used to deal with these errors
efficiently. However, bit-interleaving scheme can be implemented for only those cells, which are half-
select free. The proposed PD12T cell successfully eliminates the HS issue in both the column and row
operations. As shown in Fig. 3, for row HS cells, control signals WLA and WLB both are off and therefore,
storage nodes Q and QB are isolated from the write path. The high state of row based WWL signal turns
the control switches MPL2 and MPR2 off, but the pull-up path is maintained since MPL1 and MPR1 are
on and thus floating of Q and QB is avoided. Similarly for the column HS cells,

since WWL is off, no write disturb path exists. Moreover, pull-up path is not disturbed, since MPL2 and
MPR2 both are on. Since the two transistors (MPL1/MPR1 and MPL2/MPR2) in pull-up path is controlled
by different column based and row based signals, the power cut-off will take place only in cross-point
cell (write-selected cell) and data will not be disturbed in any of the HS cell. Fig. 14 shows the
distribution plot of the Hold SNM for both the row and column HS cells, which confirms that the bit-cell
can function properly in HS state. For both row and column HS cells, the mean Hold SNM is found to be
almost 30% of VDD, which is quite enough for a robust SRAM cell. The minimum of Hold SNM is found to
be 34 mV and 36 mV for column and row HS cells, which indicates that the chances of failure are
negligible. Therefore, the proposed cell PD12T can easily be integrated in a bit-interleaving architecture
without the need of write-back or any other assist scheme.

We have seen that, the PD12T cell has highest Qcrit among the considered cells and is least vulnerable
to single-bit soft error. Therefore, the proposed cell, when implemented in BI fashion will achieve high
MCU immunity.

3.12

Fig. 15 shows the layout view of 6T, BI12T and the proposed PD12T cells designed using 45 nm
technology rules. The cell areas are normalized with respect to 6T SRAM cell. Table 3 presents the
comparison of relative area and some other features of several SRAM cells considered in this work. The
proposed cell shows an area overhead of 2.5× as compared to 6T SRAM cell. The PD12T cell exhibits 7%
higher area as compared to BI12T cell. However, all-TFET implementation is not possible in BI12T
whereas PD12T offers this feature due to its all unidirectional transistors. The CHANG10T and ST-2 cells
exhibit additional area penalty of 98% and 105% as compared with 6T SRAM cell. It is obvious that the
proposed cell shows considerable area penalty, however, its other useful features attractively
compensate for that. This is further discussed in the following Section 3.13.

3.13

There is often a tradeoff among the different performance metrics of an SRAM cell. Therefore, to
comprehensively assess the performance of an SRAM cell, we utilize Electrical Quality Metric (EQM) [42]
to evaluate the overall quality of a cell. EQM is defined as:

Eq

where Read SNM and Hold SNM are the static noise margin during hold and read operation. WM is the
Write Margin of the cell. Read delay is the read access time. Pleak is the average leakage power. Pread
andPwrite are the dynamic power of the cell during read and write operation. Area used here is the bit-
cell area normalized to 6T SRAM cell. Fig. 16 shows the normalized EQM plot of SRAM cells considered in
this work at different supply voltages. We observe that the proposed PD12T cell has the best EQM at all
supply voltages. The overall quality metric of the proposed cell is increased by 22.2×, 9.3× and 1.4× as
compared to 6T, Chang10T and BI12T cells at 0.3 V supply voltage. It is also observed that the cell
performs much better at lower supply voltages considering the overall performance metrics. The
proposed PD12T cell, therefore, is an attractive choice considering the overall performance along with
high SNM and Qcrit at lower supply voltages.
4 conclusion

This work proposed a fully half-select-free robust low-power 12T

SRAM cell that is suitable for bit-interleaved architecture. The proposed PD12T cell eliminates Read
disturb and improves the Write-ability by using power-cutoff and Pseudo-Differential Write-Assist. The
proposed cell offers 4.58× higher RSNM, 1.41× higher write margin, provides 57% saving in leakage
power and 56% saving in write power (at VDD = 0.7 V). The proposed cell also offers 10× higher Ion/Ioff
ratio as compared to 6T cell and this property of the PD12T cell can be exploited to subside the area
overhead. The minimum supply voltage for the PD12T cell is only 0.35× compared to 6T cell and this
offers an opportunity to further reduce the hold power of the proposed cell. The proposed cell achieves
18% and 26% higher Qcrit compared with 6T and BI12T cell and therefore it significantly enhances the
soft-error immunity. The proposed PD12T cell shows the best overall quality metric (EQM) which is
much better at lower supply voltages. The proposed cell is also suitable for all-TFET implementation as it
uses only unidirectional transistors. The MC simulations incorporating local and global

variations confirm the robustness of the design in terms of stability and leakage power. Although, the
proposed cell has a longer write delay; nevertheless, the proposed cell could be good circuit solution for
ultralow voltage moderate speed applications that demands high stability.