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Comparative static leakage power analysis of 4t and 6t SRAM

Project work done by S.Radha Guided by Asst. Prof Vijay Kiran


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Types of SRAM
Two types of SRAM is designed using cadence analog design 180 nm technology 4t SRAM uses 4 transistors 6T SRAMuses 6transistors

comparitive power analysis of 4t and 6t SRAM

6t SRAM

comparitive power analysis of 4t and 6t SRAM

6t SRAM

Consists of two cross coupled inverters with two pass transistors connected to complementry bit lines The access transistors are connected to wl to perform read and write operation

comparitive power analysis of 4t and 6t SRAM

OPERATION OF 6t SRAM cell

For write operation apply desired value to the bit control lines. Assert the word line.written bit is latched in the flipflop For reading assert both b and b/ bit lines to one and set word line to one

comparitive power analysis of 4t and 6t SRAM

4t SRAM

comparitive power analysis of 4t and 6t SRAM

Operation of 4t SRAM cell

For write operation, the write drive discharges one of the bitline pair, Cell data is flipped During read operation ,the cell discharges A sense amplifier amplifies the differential voltage.

comparitive power analysis of 4t and 6t SRAM

4t SRAM
It consists of two access pmos and two drive nmos.no load element.
Pre charged bitline voltage must be maintained at powerlevel

comparitive power analysis of 4t and 6t SRAM

FORMULAE USED

Supply voltage =1.8v Pav-4T-Vin = [(1/T) 0 T I dt] Vin Power consumed =input power-output comparitive power analysis of 4t power and 6t SRAM

Comparison of power consumption


Average power consumed by 6t transistor is 0.87 mW Average power consumed by 4t transistor is 0.023 mW Power is saved by 29%

comparitive power analysis of 4t and 6t SRAM

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Symbol diagram of 6t SRAM

comparitive power analysis of 4t and 6t SRAM

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Schematic of 6t SRAM

comparitive power analysis of 4t and 6t SRAM

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Simulation Result

comparitive power analysis of 4t and 6t SRAM

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Conclusion & future applications

A comparitive power analysis of 4t and 6t SRAM with optimized area which allows precise control over speed. The design can be mapped and optimized on cadence tools For faster clock speed RAM , logic should be mapped with next generation micro electronics like micro fluid chips
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