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  • Nguyen Masters Report06

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    This document discusses the design of read/write assist circuits used in SRAM cells to overcome cell variations. It explains variability problems in SRAM bit-cells and approaches to address them. Specifically, it discusses a write assisted circuit called the Negative Bit-line Voltage Bias scheme, which was implemented at the transistor level using a six-transistor SRAM cell. Simulation results showed this write assist circuit helped the memory array successfully perform writes at 0.6V and low voltage, a condition that would fail without the assist, by achieving a negative bit-line bias of -70mV.

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    This document discusses the design of read/write assist circuits used in SRAM cells to overcome cell variations. It explains variability problems in SRAM bit-cells and approaches to address them. Specifically, it discusses a write assisted circuit called the Negative Bit-line Voltage Bias scheme, which was implemented at the transistor level using a six-transistor SRAM cell. Simulation results showed this write assist circuit helped the memory array successfully perform writes at 0.6V and low voltage, a condition that would fail without the assist, by achieving a negative bit-line bias of -70mV.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    5 views1 page

    Nguyen Masters Report06

    Uploaded by

    PhiPhi
    This document discusses the design of read/write assist circuits used in SRAM cells to overcome cell variations. It explains variability problems in SRAM bit-cells and approaches to address them. Specifically, it discusses a write assisted circuit called the Negative Bit-line Voltage Bias scheme, which was implemented at the transistor level using a six-transistor SRAM cell. Simulation results showed this write assist circuit helped the memory array successfully perform writes at 0.6V and low voltage, a condition that would fail without the assist, by achieving a negative bit-line bias of -70mV.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    Abstract

    Read/Write Assist Circuits and SRAM Design

    QuocDat Tai Nguyen, M.S.E.


    The University of Texas at Austin, 2009

    Supervisor: Abraham A. Jacob

    This report discusses the design of read/write assist circuits which are used in a
    SRAM cells design to overcome the cells variations. It also explains the variability
    problems in a SRAM bit-cell and many approaches to address them.

    The basic

    operations, SNM concept, and write margin of an SRAM are described theoretically as
    well as measured in simulation. The write assisted circuit, the Negative Bit-line Voltage
    Bias scheme, is discussed and implemented at transistor level using a six-transistor (6T)
    SRAM cell. With the write assisted circuit, the implemented memory array successfully
    25

    performs a write operation at 0.6V and

    , the condition in which the same

    operation would fail without the write assisted circuit. During the simulation, this write
    assisted circuit helps to achieve the negative bias voltage of -70mV on the SRAMs bitlines. The cost overhead includes chip area, power consumption, and current leakage
    when this Negative Bit-line Voltage scheme is implemented.
    vi

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