NATIONAL INSTITUTE OF TECHNOLOGY

WARANGAL

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
SPECIALIZATION: VLSI SYSTEM DESIGN (M. TECH. I YEAR)

LPVLSI Assignment 03
Different designs of low power SRAM cells with their analysis
of Noise margin and Power Dissipation

Submitted by
Anish Kumar Mishra
Reg No:23ECM2R01
M.Tech (VLSI Design-1ST Year)
SRAM (Static Random Access Memory):

SRAM has emerged as a critical component in numerous VLSI chips owing to its
high storage density and swift access times. The significant advancements in
low-power, low-voltage memory design in recent years have spurred extensive
research into SRAM technology. This surge is largely fuelled by the escalating
demand for notebooks, laptops, IC memory cards, and handheld communication
devices. SRAMs find extensive application in mobile devices, serving as both
on-chip and off-chip memories, thanks to their user-friendly nature and minimal
standby leakage.
6T static random-access memory is a type of semiconductor memory that uses
bistable latching circuitry to store each bit. The term static differentiates it from
dynamic RAM which must be periodically refreshed. SRAM exhibits data
remembrance, but is still volatile in conventional sense, that data is eventually
lost when memory is not powered.

1.1 Structure of an SRAM Cell:

1. Cross-Coupled Inverters: The heart of an SRAM cell consists of two

cross-coupled inverters. Each inverter is composed of two complementary
metal-oxide-semiconductor field-effect transistors (CMOSFETs): one p-
channel (PMOS) and one n-channel (NMOS). These inverters are
connected in a feedback loop, creating a bistable circuit.
2. Access Transistors: Two access transistors (one NMOS and one PMOS)
are used to connect the cross-coupled inverters to the bitlines and bitline bar
(complementary bitline). These access transistors control the read and write
operations of the SRAM cell.
3. Bitlines and Worldlines: SRAM cells are organized in an array, and each
cell is connected to two bitlines (BL and BLB) and one wordline (WL). The
bitlines carry the complementary values of the stored bit, and the wordline
is used to enable the access transistors and control the read and write
operations.
Schematic:

6T SRAM CELL OPERATION:

1. Hold (the circuit is idle):

In standby mode word line is notasserted (word line=0), so pass transistors
N3 and N4which connect 6t cell from bit lines are turned off. Itmeans that
cell cannot be accessed. The two crosscoupled inverters formed by N1-N2
will continue to feedback each other as long as they are connected to
thesupply, and data will hold in the latch.

2. Read Mode (the data has been requested):

In read modeword line is asserted (word line=1), Word line enablesboth the
access transistor which will connect cell fromthe bit lines. Now values
stored in nodes (node a and b)are transferred to the bit lines. Assume that 1
is stored atnode a so bit line bar will discharge through the drivertransistor
(N1) and the bit line will be pull up through theLoad transistors (P1) toward
VDD, a logical 1. Design ofSRAM cell requires read stability (do not
disturb datawhen reading).
 3. Write Mode (updating the contents):
Assume that thecell is originally storing a 1 and we wish to write a 0. Todo
this, the bit line is lowered to 0V and bit bar is raisedto VDD, and cell is
selected by raising the word line toVDD. Typically, each of the inverters is
designed so thatPMOS and NMOS are matched, thus inverter threshold
iskept at VDD/2. If we wish to write 0 at node a, N3operates in saturation.
Initially, its source voltage is 1.Drain terminal of N2 is initially at 1 which
is pulled downby N3 because access transistor N3 is stronger than N1.Now
N2 turns on and P1 turns off, thus new value hasbeen written which forces
bit line lowered to 0V and bit bar to VDD. SRAM to operate in write mode
must have write ability which is minimum bit line voltage required to flip
the state of the cell.

Schematic:
Sizing ratios of CMOS 6Ts cells:

Simulation Waveform:
Average Power = 221mW
7T SRAM Cell:

Operation:
Read Operation:

The read operation is improved by utilizing a single transistor (M7) for

the readout path to reduce the read access time. Suppose that a '0' data is
stored on Q. While read word line (RWL) changes to zero, read
operation commences. Thus, the BL starts to discharge via a single
transistor (M7). Also, with this technique, the read operation can be
performed at ultra-low supply voltages. Because of using a single
readout path transistor (M7) in the proposed design, the bit-line
capacitance and readout path resistance of the proposed cell are lower.
Write Operation:
During the write operation, the static write stability or static write
margin metric is defined the difference between VDD and the WWL
voltage when the nodes Q and QB flip. This approach sweeps the
voltage of WWL at both sides simultaneously to provide a real write
operation. To increase the write stability, the access transistors should
be strengthened while the pull-up transistors should be weakened. The
WM of the proposed design is larger. In this cell, utilizing single
transistor in the readout path enables low voltage write operations.

Schematic:
9T SRAM CELL
Operation:

Read Operation
The proposed cell's read operation mirrors that of the reference 8T cell, utilizing
transistors M7 and M8 to form a read buffer that separates the readout path from
the internal storage. Node "X" controls M7, allowing it to turn off when a '1' is
stored and conduct when a '0' is stored. During a read operation, the read bit line
(RBL) is precharged, and the read word line (RWL) is activated. If a '0' is stored,
the RBL discharges through M7 and M8, while if a '1' is stored, M7 blocks the
discharge path, maintaining the precharged level of RBL. A single-ended sensing
scheme determines whether RBL has discharged. Despite the reduced voltage
level when holding a '1', node "X" is always clamped to VDD or GND, ensuring
strong conduction through M7 (or M8) and maintaining equivalent read
performance to the 8T reference cell.
This decoupling of the readout path provides a read margin equivalent to the hold
margin, sufficient across various supply voltages and process variations.
However, read performance depends on factors like bitline capacitance, sense
amplifier sensitivity, and the drive strength of read buffer transistors (M7, M8).
Thus, read performance is tailored to specific applications and architectures, but
it significantly degrades with reduced supply voltage.
Write Operation

The SF-SRAM cell's intriguing aspect lies in its unique write operation
performance. Similar to an 8T cell, writing begins by setting the write bit lines
(WBL and WBLB) to the data level and activating the write word line (WWL).
In standard 8T cells, ensuring successful writes involves overcoming the pull-up
pMOS by the pull-down path. However, fluctuating currents due to process
variations often disrupt this balance, leading to failed writes. The proposed cell
employs a feedback loop from node "X" to weaken the pull-up path,
addressingthis issue and ensuring successful writes, especially in asymmetric
write scenarios.

Write 1 Operation:

When transitioning the cell from a hold '0' state to writing a '1', WBL is set to
VDD and WBLB is grounded. Activation of WWL initiates the write operation.
Initially, M9 facilitates contention to the pull-down path through M5, aiming to
pull towards an intermediate voltage between VDD and GND. In challenging
conditions like the SF corner, M9's feedback weakens as the cell is charged,
aiding in achieving a successful write by facilitating an "easy" write process. The
proposed SF-SRAM cell demonstrates significant advantages over the reference
8T cell, particularly evident at lower supply voltages, maintaining positive write
margins down to below 200 mV under global variations, whereas the 8T cell's
write margin becomes negative below 500 mV
Write 0 Operation:

During the Write '0' operation, assuming that node "X" is charged toVDD and
node "Y" is discharged to GND, WBL is grounded while WBLB is set to VDD.
Upon asserting WWL, node "X" begins at a lower voltage, and M9 is initially cut
off. This configuration ensures a strong pull-up current from M2 overwhelms any
residual pull-up current from M9, initiating rapid positive feedback in the cross-
coupled inverters to pull the storage nodes to their respective rails. This
straightforward process leverages the initial conditions and the cutoff state of M9
to achieve efficient write '0' operations.
Schematic:

Figure 10: Read operation.

Figure 11: Write operation.
 Figure 12: Hold operation.

10T SRAM Cell:

Circuit Diagram

Figure 13: 10T SRAM Cell.

Simulation Waveform

Figure 14: Hold operation.

Figure 15: Read operation.

Figure 16:Low Area 10T SRAM Cell

Simulation Waveform

Figure 17:Hold Operation

 Figure 18:Read Operation

Figure 19:Low Energy 10T SRAM Cell

Simulation waveform:

Figure 20: Hold Operation

Figure 21:Read Operation