Design of 6T, 5T and 4T SRAM Cell on Various
Performance Metrics
Wazir Singh
IIIT-Delhi, India
Email Id: wazirs@iiitd.ac.in
Abstract- As the technology is shrinking, a significant
amount of attention is being paid on the design of high
stability Static Random Access (SRAM) cells in terms of static
Noise Margin (SNM) for different levels of cache memories.
This paper presents a qualitative design of 6T, 5T and 4T
Static Random Memory Access cell in terms of Read cell
current, Write time, Static Noise Margin (Read and Hold),
Write Noise Margin in 65nm CMOS technology. Simulation
results shows that the 6T SRAM cell exhibits 173% higher
SNM than 4T SRAM cell which indicates that it is highly
stable than 4T configuration.
Keywords– SRAM cell, Static Noise Margin, CMOS
Technology.
I. INTRODUCTION
Shrinking transistor dimensions and reducing supply voltages
lead to lowering of noise margins and increase the impact of
variability. The use of minimum-size transistors in static
random access memories (SRAMs), along with technology
scaling, increases the variation [1] in the intrinsic properties
and also causes a lot of variation in the properties of the
transistors like increasing or decreasing the threshold voltage
(Vt). An SRAM bit cell is said to be functional if, a non-
destructive read and a successful write operations. Data
stability can be enhanced by carefully selecting the threshold
voltages and relative sizes of transistors in an SRAM cell.
Static random access memory (SRAM) can retain the
information which is stored as long as the power is supplied.
SRAM will have less leaky path because of pull up’s to store
the data, hence SRAM works without refreshing. The term
``random access'' means that in an array of SRAM cells, the
accessing time of any cell is equal irrespective of the position of
the cell. Typical 6T SRAM [2] structure will be like as shown
below. The cell if formed by cross coupling of two inverters
back to back forming the positive feedback loop. The access
transistors and the word and bit lines, WL and BL, are used to
read and write from or to the cell. The bit lines act as I/O buses
which carry the data from the memory cell to the sense
amplifier. SRAM cell perform three different operations, read,
write and hold operations.
978-9-3805-4416-8/15/$31.00 2015
c IEEE
G. Anil Kumar
IIIT-Delhi, India
Email Id: anil13154@iiitd.ac.in
In this paper, simulations for different types of SRAM on
various performance metrics using 65nm CMOS technology are
performed and corresponding results are presented. This paper further
organized as follows. Different types of SRAM are briefly
discussed in Section II. simulation results are introduced with
performance comparison in section III. Finally, the paper is
concluded in Section IV.
II. DIFFERENT TYPES OF SRAM
A. 6T-SRAM
The 6T SRAM cell can be designed by using two PMOS
transistors and four NMOS transistors. A conventional 6T
SRAM consists of two crossed coupled inverters and two
access NMOS transistor M5 and M6. Both the inverters are
connected with each other back to back. With the help
transistors M5 and M6, the data can be either accessed or
written into the cell [3]. These two cross-coupled inverters are
used for storing one bit of information at a time (either 0 or 1).
6T SRAM cell as shown in Fig.1 must to guarantee a non-
destructive read operation, NMOS driver transistors M1 and
M2 must be1.5-2.5 times larger than NMOS access transistors
M5 and M6.
B. 5T-SRAM
The Schematic of 5T bit cell is depicted in Fig. 2 looks similar
like a conventional 6T SRAM bit cell, but the only difference
is missing of one access transistor. Read and Write access are
similar to the 6T except they have single ended through the
lone access transistor. Writing a ‘0’ to the 5T bit cell [4] is not
an issue since the lone NMOS access transistor, M5, can pass
a strong ‘0’. However, writing a ‘1’ is virtually impossible
without a write assist since M5 cannot pass a strong ‘1’.
Moreover, if the sizing approach used strengthens M1, writing
a ‘1’ becomes even more challenging due to the ratioed fight
between M5 and M1.
C. 4T-SRAM
All existing SRAM cells can be divided into two groups like
6T and 4T cell having load element. The 4T SRAM cells have
dominated the stand-alone SRAM market since they have
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 much less cell area than 6T SRAM cells. However, for on-chip • Write Time
storage in microprocessors and other logic circuits, the 4T Write time of the 6T SRAM is defined as the time taken to
SRAMs have not been used, because they need a complex write the data into the memory bit cell. When we try to write
process to form a load element and have poor stability at low the data into the SRAM cell, we can write only zero into the
voltage. Due to few disadvantages of the conventional 4T load bit, and 1 is automatically written into the memory cell. Here,
element SRAM memory cells, a new 4T cells without loads [5], writing is the first event which will occur and the writing the 1
[6] had evolved. Below Fig. 3 shows the basic load less 4T into the other end is the last even which occurs. So, time taken
memory cell which uses the supply voltage of 1.2 volts. to change the data from 0 to 1 in the other word when we
write the data 0 is called the Write time. When calculating the
III. SIMULATION RESULTS write time we preset the internal nodes Q=0V and QB=1.2 V
and pre-charged both the bit lines to 1.2V. Finally the bit line
A. 6T-SRAM capacitor has to discharge to the value 0V which indicates on
the other side (means Q node) becomes 1. This entire transient
• Static Noise Margin (SNM) time is called write time which is shown in Fig. 9.
The SRAM cell immunity to Static Noise is measured in terms
of SNM [7], [8] that qualifies the maximum amount of noise
voltage that can be tolerated at the cross coupled inverter nodes B. 5T SRAM
without flipping the output data or the cell data. The SNM is • Static Noise Margin
generally plotted like whenever the bit lines are pre charged to In 6T SRAM bit cell design we use the Width of the pull down
high voltage at the time of reading the data from the cell. The transistors are equal and the width of the two pull up
method of calculating the Read Static Noise Margin as shown transistors are equally sized. We observe in the 6T transistor
in Fig. 4 is that by varying the ‘W’ noise and checking the that the lower lobe of the butterfly curve is somewhat
output of the bit cells whether the data stored in the bit are squashed due to the voltage divider formation of the access
flipping or not. By adopting this technique we should take care transistor and the pull down transistor. Thus we see a lesser
of the polarities noise voltage source at the input of each area of lower lobe in the butter fly curve in 6T transistor.
inverter. The simulated results for read and hold SNM are Where as in 5T bit cell [4]-[10] because of the absence of one
given in Fig 5 and 6. access transistor there will not be fight between the access
transistor and the pull down transistor as in the case of 6T bit
• Write Noise Margin (WNM) cell. So the lower lobe of the butter fly curve will get
Minimum WL Voltage for which data flips when Bit line (BL) enhanced and the upper lobe of the curve will be constant as
is at ground (0 Voltage). From Fig. 1, Assume that left inverter like in the 6T cell. The simulated results for SNM and write
stores 1 and we want to write zero then, time are shown in Fig. 10 and 11 respectively.
VDS ≤ VGS − VT (1)
 VBL ≤ VWL − VT (2) • Write Time
 VBL + VT ≤ VWL (3) TABLE II. PERFORMANCE COMPARISON OF DESIGN
The above equation indicates the minimum WL voltage for METRICS
which the data flips off. In the same way other definition is, SRAM SNM SNM Cell Write Write
maximum level of bit line that ensures the cell flips the data Read hold current Noise time
when Word line (WL) is at VDD. (mV) (mV) (μA) Margin (ps)
(mV)
VDS ≤ VGS − VT (4)
6T 233.682 353.145 42.286 518.866 246.34
VBL ≤ VWL − VT (5)
5T 449.612 - 42.281 - 125.16
The above equation indicates the maximum level of Bit line
4T 85.566 353.317 24.647 - 462.50
voltage for which it flips the data. The simulated result is
depicted in Fig.7.
• Cell Current
In 6T SRAM bit cell current can be seen as the current which C. 4T SRAM
flows into the access transistors and the pull down transistors • Static Noise Margin
when the read mode operation is held [9]. When calculating the After the functionality of the cell is proven, simulations are
cell current we pre-charge both the bit lines (BL and BLB) to performed and mentioned in Fig.12 and 13 to determine the
high voltage (1.2V) and we preset the internal node voltages (Q stability of the cell during read operation which is the most
and QB) to low and high voltages (0 and 1.2V). Then the vulnerable period during all the operations.
current which flows through the access transistors and pull • Cell Current
down transistors gives the read cell current. The result for the The simulation of cell current for 4T shown in Fig.3 is
read current related to Fig. 1 is shown in the Fig.8. depicted in Fig.14.

900 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom)
 [10] S. Nalam and B. Calhoun, “Asymmetric sizing in a 45 nm 5T
• Write Time SRAM to improve read stability over 6T,” in Proc. 2009 IEEE
The simulation of write time for 4T shown in Fig.3 is shown in Custom Integrated Circuits Conf. (CICC), 2009, pp. 709–712.
Fig.15.
FIGURES
IV. CONCLUSION
A comparative analysis of the 6T, 5T and 4T SRAM cell is
made w.r.t Static Noise Margin, Cell Current, Write Time and
Write Noise Margin. All the simulations were carried on
cadence tool in 65nm technology environment. All the
simulations are made for TYPTYP lot corners and it can be
observed that the cell current is almost same for 6T and 5T
SRAM cell whereas 4T SRAM cell exhibits less cell current. It
can be observed from the simulations that the hold SNM is
almost same for both 4T and 6T memory cell. The future work
for this SRAM cell design could be analyzing the SRAM cell
w.r.t design parameters like Yield, cell current distribution
statistically by incorporating Vt variations and random dopant
fluctuations at all Voltage, Temperature and process corners for
different capacities of memories.

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2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom) 901
 Fig. 3 4T SRAM

Fig. 4 6T SRAM SNM setup

Fig. 5 6T SRAM read SNM

Fig. 6 6T SRAM hold SNM

Fig. 8 6T SRAM cell current

Fig. 7 6T SRAM Write Noise Margin

902 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom)
 Fig. 9 6T SRAM write time

Fig. 11 5T Write time

Fig. 12 4T SRAM read SNM

Fig. 10 5T SRAM read SNM

Fig. 14 4T SRAM cell read current

Fig. 13 4T SRAM hold SNM

2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom) 903
 Fig. 15 4T Write time

904 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom)