A Study of Fin Width Effect on the Performance of

FinFET
Kai-Lin Lee1 , Ren-Yu He1, Hung-Wen Huang1, Chih-Chieh Yeh1, Iue-Hen Li1, Osbert Cheng1
1
No. 18, Nanke 2nd Rd., Tainan Science Park, Sinshih Township, Tainan Country 741, Taiwan, ROC
United Microelectronics Corporation
Phone: 886-6-505-4888 Fax: 886-6-505-0966 Email: kai_lin_lee@umc.com

Abstract- As short channel effect (SCE) and subthreshold leakage III. RESULTS AND DISCUSSIONS
is demonstrated to be controlled effectively from conventional
planar MOSFETs to the FinFET, we used a three-dimensional A. Top- & sidewall-gate control ability with varied fin width
simulation of nFinFET structure to analysis fin width effect on the In order to understand the gate control ability of FinFET, we
FinFET performance from perspectives of both on-state and
used an ideal case to separate tri-gate into ³top-gate´ and
off-state. In this study, the major leakage path of FinFET with
varied Wfin takes place at middle fin where is controlled by ³sidewall-gate´ individually. Fig. 1(a) shows electric field
double-gate, in the meanwhile, on-state current density is not distribution for long channel device with Wfin = 12nm and
uniform within active fin and a higher current density is observed top-gate/sidewall-gate was set to ground/floating respectively.
at fin top. FinFET with increasing Wfin induces more on-state The top-gate field penetrates down to the fin within region A,
current and also Isub reduction because of impact ionization is meanwhile, another apparent electric filed is found at region C,
suppressed. In order to enjoy both on-state and off-state that comes from diffusion of sub-fin counter doping APT. The
advantages, the FinFET with wide Wfin at fin top and thin Wfin at introductions of both tri-gate and APT performs a better
middle fin/fin bottom is proposed for desired effective fin area and electrostatic control of FinFET device, that is, the major leakage
electrostatic control.
path takes place at region B, where electrostatic is controlled by
double gate, if the barrier potential induced by APT is higher
I. INTRODUCTION
than region B. With Wfin = 14nm and 16nm the electric field
distribution is shown in Fig. 1(b) and 1(c), the change in electric
The evolution from planar MOSFETs to the FinFET is
field at region A of Fig. 1(b) and 1(c) with reference to Fig. 1(a)
adopted as a solution of SCE which is controlled effectively by
results in plentiful top-gate control because of increasing fin
multi-gate structure, a FinFET device with thinner Wfin leads to
width.
a better electrostatic control as well as SCE and subthreshold
The major leakage path of FinFET could be changed between
leakage [2]. We used a bulk nFinFET TCAD model to analysis
region B to region C as barrier potential is strong
the fin width effect on device performance, tri-gate is separated
doping-dependent, there is a leakage path from the source to the
into top-gate and sidewall-gate to monitor individual gate
drain as shown in Fig. 2(a) and 2(b). Fig. 2(b) indicates the
control ability. In addition, a counter doping region at sub-fin is
punch-through leakage path could not be blocked and the
defined as anti-punch through (APT) implantations, which
subthreshold leakage becomes larger due to low counter doping
introduces a barrier height to suppress leakage between source
concentration at the sub-fin.
and drain. The major leakage path always occurs at either
double-gate region or APT region.
B. Short channel effect with varied fin width
A high current density is found at fin top due to more
Fig. 3(a) and 3(b) presents a short channel device electric field
inversion charge is induced by tri-gate compared with
distribution, which is extracted at VGS = 0V and VDS = Vcc, at
double-gate, the ratio of total current at fin top region to whole
region B in the X-Y plane. The Electrostatic Integrity (EI), as we
active fin is 36%. Large hot carrier injection accompanies fin
know, can be improved by reducing the thickness of gate oxide,
width scaling [3] due to the impact ionization is enhanced as
silicon film [4] and/or drain bias. We defined a parameter, Lpen,
well as electric field.
which represents the length of penetration of the electric field
into fin in the channel direction. Fig. 4(a) shows Lpen of short
II. EXPERIMENT
channel device can be reduced by decreasing Wfin and drain bias
respectively. The Lpen has high sensitivity to Wfin compared with
Our analysis is based on a bulk nFinFET simulation results,
that to drain bias, smaller Wfin especially. Fig. 4(b) presents
the FinFET structure was created by 3D process simulation and
DIBL is improved with decreasing Wfin due to better
the device dimensions is correspond to bulk nFinFET
sidewall-gate control as well as Lpen.
production process worldwide. The advanced process features
includes fin definition, high-k metal gate process, source/drain
C. On-state current density distribution for FinFET with 12, 14
epitaxy, low specific resistivity contact are performed. In order
and 16 nm fin width
to compare the effect of different fin width on the performance
The on-state current density distribution of the FinFET with
of nFinFET, the fin width Wfin changed from 12nm to 16nm in
Wfin = 12nm is presented in Fig. 5(a), a higher current density is
steps of 2nm.
observed at region W because tri-gate structure leads to more

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inversion charge compared to double-gate. To divide active fin
into four parts with equal size, there is 36% total current within
region W and 15% total current only flows through region Z.
The ratio of total current at region W to whole active fin is
increasing from Wfin = 12nm to 16nm due to effective fin area is
increasing mainly as shown in Fig. 5(b) and 5(c). In addition,
Fig. 6 presents a larger Wfin results in a benefit of Isub reduction,
which comes from less impact ionization and low electric field
(a) (b)
accompanies increasing Wfin as shown in Fig. 7(a)-(f). Fig. 4(a) Length of electric field penetration and 4(b) DIBL are both
as a function of Wfin under Vcc - 100mV in steps of 50mV
IV. CONCLUSIONS
Abs (Current
In this paper, we have analyzed nFinFET off-state gate W 36% 39% 42% Density) [A.U.]

control of varied Wfin. The middle fin exhibits worse 7

X 24% 26% 26%
electrostatic compared to fin top and fin bottom where enjoys 6
5
better electrostatic controlled by tri-gate and APT respectively, Y 24% 23% 23%
4
and the EI can be improved effectively by reducing Wfin. On the
Z 11% 3
other hand, the on-state current density of FinFET within active 15% 13%
2
fin is not uniform, a higher current density is observed at fin top,
1
the introduction of larger Wfin at fin top leads to on-state current
enhancement as well as Isub reduction. FinFET with wide Wfin at (a) (b) (c)
fin top and thin Wfin at middle fin/fin bottom will enjoy both Fig. 5. On-state current density distribution and its integral total current of
FinFET with (a) Wfin = 12 nm, (b) Wfin = 14 nm, (c) Wfin = 16 nm
effective fin area and electrostatic control advantages.

Fig. 6. Isub of short channel FinFET with varied Wfin under fixed overdrive
(a) (b) (c)
Fig. 1. Electric field distribution of top-gate control of FinFET with
(a) Wfin = 12 nm, (b) Wfin = 14 nm, (c) Wfin = 16 nm

D D D

Wfin = 12nm Wfin = 14nm Wfin = 16nm

(a) (b) (c) (d) (e) (f)

Fig. 7(a)-(c). Impact ionization of FinFET with fixed overdrive voltage
Fig. 7(d)-(f). Electric field distribution of FinFET with fixed overdrive voltage
(a) (b)
Fig. 2. Off-state current density distribution of FinFET structure cross section REFERENCES
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