IV.

SRAM CELL DESIGN AND SIMULATION:

As discussed above, a deep sub-micron memory design faces many challenges: one of

the biggest challenges is the on-die process variation which is the same challenge that the
whole Semiconductor industry faces today.

It is widely discussed that the current

Semiconductor road-map is getting near the end.

The percentage of variability increases

and diversifies into many sources such as process induced, environmental, and Physical
limit induced variation, etc. These sources of variation can greatly shift the balance of
the circuit. Especially in SRAM design where circuit operates in meta-stability state, any
shift in Vt, physical dimension can cause SRAM cell to fail. Fortunately, there are many
researchers in the Semiconductor industry today who have made progress to compensate
for this variability problem and provide solutions such as the Read and Write assist
circuits. This report will employ a Write assist into a 256x7 bit memory array to evaluate
the total overhead cost including chip area, power consumption and speed.

4.1 SRAM Cell Basic Operation and SNM Simulation

4.1.1

MEMORY BIT-CELL SIMULATION:

The conventional 6-T single port memory bit cell is shown in Figure 4.1. The bit cell
is sized and optimized to achieve the best balanced of SNM and Write Margin (WMG).
The simulation of the memory cell was constructed as described in Section SNM
above, the transistor sizes were parameterized at Typical Voltage and Temperature to
find the optimal SNM. Once the SNM is achieved, the memory cell WMG is then
simulated.

However, because of the way the memory cell functions, getting the best

SNM compromises WMG and therefore the process of optimizing the SNM and WMG
need to be repeated in order to achieve performance targets. Figure 4.2 & 4.3 below
show the optimal SNM and WMG at the desired 45A memory cell currents. The
SRAM memory cell current is also presented in the Figure 4.4 below.
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