VLSI Design

Name:-Juhi Randhir Holkar

UEC2021312

Batch:-C1

Experiment 8: SRAM cell Implementation

Aim: Design of CMOS single bit SRAM cell layout and verify the functionality by
simulation

Equipment: PC with Micro-wind software and printer.

Theory: The circuit for an individual SRAM memory cell comprises typically four
transistors configured as two cross coupled inverters. In this format the circuit has two stable
states, and these equate to the logical "0" and "1" states.

Access to the SRAM memory cell is enabled by the Word Line. This controls the two access
control transistors which control whether the cell should be connected to the bit lines. These
two lines are used to transfer data for both read and write operations.
Output: The screen shot of layout & output for SRAM cell.

Conclusion:

In summary, the VLSI experiment involving the design of a CMOS single-bit SRAM
cell layout and the subsequent verification of its functionality through simulation has
enriched our proficiency in layout design, deepened our understanding of SRAM cell
operation, and enhanced our simulation skills. This hands-on experience emphasized
the importance of manufacturability considerations, design rule adherence, and the
practical application of SRAM technology. It bridges the gap between theoretical
knowledge and practical skills in digital integrated circuit design, preparing us for
real-world applications in semiconductor technology.

Assignment Questions :

1. Distinguish between Static RAM & Dynamic RAM

Ans:-Static RAM (SRAM) and Dynamic RAM (DRAM) differ in the following ways:

1. Data Retention: SRAM retains data without refreshing, while DRAM requires periodic
refresh cycles to maintain data.

2. Storage Cell Structure: SRAM uses complex flip-flops, DRAM uses simpler capacitors and
transistors.

3. Access Speed: SRAM is faster with low latency, suitable for caches, while DRAM is
slower with higher latency, used for main memory.

4. Density: DRAM has higher data storage density, making it cost-effective for large memory
modules.
5. Power Consumption: SRAM is more power-efficient due to no refresh cycles, while
DRAM consumes power during refresh.

6.Cost: SRAM is more expensive due to its complexity, while DRAM is cost-effective for
large capacities.

2. Which RAM is faster & why Static RAM or Dynamic RAM ?

Ans:-Static RAM (SRAM) is faster than Dynamic RAM (DRAM). The primary reasons for
this speed difference are:

1. Simplicity of Circuitry: SRAM cells are built using multiple transistors configured as flip-
flops to store each bit of data. This arrangement results in a relatively simple and direct path
for data access. There are no capacitors or periodic refresh cycles to deal with.

2. No Need for Refresh: DRAM requires constant refresh cycles (typically every few
milliseconds) to maintain the charge on its memory cells, as the charge tends to leak away
due to the capacitor-based storage mechanism. These refresh cycles introduce delays and
consume additional power, which slows down access times.

3. Low Latency: SRAM offers low latency, which means it can respond quickly to read and
write requests. This makes SRAM suitable for high-speed applications like cache memory in
processors, where immediate data access is essential.

4. Lack of Complex Timing Constraints: DRAM cells have complex timing constraints
related to refresh cycles, which can introduce delays in accessing data. In contrast, SRAM
cells do not have such complex timing constraints.

While SRAM is faster, it is more expensive and less dense than DRAM, which makes it
suitable for smaller, high-speed memory applications. DRAM, on the other hand, is slower
but provides higher storage density and is cost-effective for main memory applications where
capacity matters more than speed.