CHAPTER-1: INTRODUCTION

Random access memory is a type of memory that provides the direct access to
any byte on the chip and byte addressing means the contents of any byte can be read or
written without regard to the bytes before or after the read and write speeds. RAM plays
an important role in many systems such as computer and communication systems; and
there is several applications software used for implementing the digital circuits of RAM.
It takes no longer to write a byte than it does to read one. RAM (also referred to as read-
write memory) is considered volatile storage because its contents are lost when the
power is removed. Computer and other types of system require the permanent or semi
permanent storage for large amounts of binary data. Memory is the portion of a system
used for storing binary data in large quantities.

Memory unit is a device to which binary information is transferred for storage

and from which information is available when needed for processing. Binary
information received from the input device is stored in memory and information
transferred to an output device is taken from memory. There are two categories of
memory in current use; semiconductor and magnetic within each category are a variety
of memory types, generally the semiconductor memories are used for smaller capacity
and faster access applications.

Normally RAM consists of the following connections:

 Address lines means it defines the memory location to be selected for read or write.

 Input/output data lines mean it defines the data to be written or read from memory.

 Write enable (WE) are a control input that selects between the memory read and write
operations (usually active low).

 Output enable (OE) is a control input that enables the output buffer for reading data
from the memory (usually active low).

 Chip select (CS) selects the memory (usually active low).

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1.1 Static random-access memory (SRAM)

Static random-access memory (static RAM or SRAM) is a type

of semiconductor memory that uses bistable latching circuitry (flip-flop) to store each
bit. SRAM exhibits data remanence, but it is still volatile in the conventional sense that
data is eventually lost when the memory is not powered.

The term static differentiates SRAM from DRAM (dynamic random-access memory)
which must be periodically refreshed. SRAM is faster and more expensive than DRAM;
it is typically used for CPU cache while DRAM is used for a computer's main memory.

1.2 Clock rate and power

The power consumption of SRAM varies widely depending on how frequently it is

accessed; in some instances, it can use as much power as dynamic RAM, when used at
high frequencies, and some ICs can consume many watts at full bandwidth. On the other
hand, static RAM used at a somewhat slower pace, such as in applications with
moderately clocked microprocessors, draws very little power and can have nearly
negligible power consumption when sitting idle – in the region of a few micro-watts.
Several techniques have been proposed to manage power consumption of SRAM-based
memory structures.

1.3 SRAM exists primarily as:

 general purpose products

 with asynchronous interface, such as the ubiquitous 28-pin 8K × 8 and 32K × 8
chips (often but not always named something along the lines of 6264 and
62C256 respectively), as well as similar products up to 16 Mbit per chip
 with synchronous interface, usually used for caches and other applications
requiring burst transfers, up to 18 Mbit (256K × 72) per chip integrated on chip
 as RAM or cache memory in micro-controllers (usually from around 32 bytes
up to 128 kilobytes)
 as the primary caches in powerful microprocessors, such as the x86 family, and
many others (from 8 KB, up to many megabytes)
 to store the registers and parts of the state-machines used in some
microprocessors (see register file)

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  on application specific ICs, or ASICs (usually in the order of kilobytes)
 in Field Programmable Gate Array and Complex Programmable Logic Device

Embedded use

 Many categories of industrial and scientific subsystems, automotive electronics, and

similar, contain static RAM.
 Some amount (kilobytes or less) is also embedded in practically all modern
appliances, toys, etc. that implement an electronic user interface.
 Several megabytes may be used in complex products such as digital cameras, cell
phones, synthesizers, etc.

SRAM in its dual-ported form is sometimes used for realtime digital signal
processing circuits.

In computers

SRAM is also used in personal computers, workstations, routers and peripheral

equipment: CPU register files, internal CPU caches and external burst mode SRAM
caches, hard diskbuffers, router buffers, etc. LCD screens and printers also normally
employ static RAM to hold the image displayed (or to be printed). Static RAM was
used for the main memory of some early personal computers such as the ZX80, TRS-80
Model 100 and Commodore VIC-20.

Hobbyists

Hobbyists, specifically home-built processor enthusiasts often prefer SRAM due to the
ease of interfacing. It is much easier to work with than DRAM as there are no refresh
cycles and the address and data buses are directly accessible rather than multiplexed. In
addition to buses and power connections, SRAM usually requires only three controls:
Chip Enable (CE), Write Enable (WE) and Output Enable (OE). In synchronous SRAM,
Clock (CLK) is also included.

1.4 Non-volatile SRAM

Non-volatile SRAMs, or nvSRAMs, have standard SRAM functionality, but they save
the data when the power supply is lost, ensuring preservation of critical information.
nvSRAMs are used in a wide range of situations – networking, aerospace, and medical,

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among many others – where the preservation of data is critical and where batteries are
impractical.

By transistor type

 Bipolar junction transistor (used in TTL and ECL) – very fast but consumes a lot of
power
 MOSFET (used in CMOS) – low power and very common today

By function

 Asynchronous – independent of clock frequency; data in and data out are controlled
by address transition
 Synchronous – all timings are initiated by the clock edge(s). Address, data in and
other control signals are associated with the clock signals

In 1990s, asynchronous SRAM used to be employed for fast access time. Asynchronous
SRAM was used as main memory for small cache-less embedded processors used in
everything from industrial electronics and measurement systems to hard disks and
networking equipment, among many other applications. Nowadays, synchronous
SRAM (e.g. DDR SRAM) is rather employed similarly like Synchronous DRAM –
DDR SDRAM memory is rather used than asynchronous DRAM (dynamic random-
access memory). Synchronous memory interface is much faster as access time can be
significantly reduced by employing pipeline architecture. Furthermore, as DRAM is
much cheaper than SRAM, SRAM is often replaced by DRAM, especially in the case
when large volume of data is required. SRAM memory is however much faster for
random (not block / burst) access. Therefore, SRAM memory is mainly used for CPU
cache, small on-chip memory, FIFOs or other small buffers.

By feature

 Zero bus turnaround (ZBT) – the turnaround is the number of clock cycles it takes
to change access to the SRAM from write to read and vice versa. The turnaround for
ZBT SRAMs or the latency between read and write cycle is zero.
 syncBurst (syncBurst SRAM or synchronous-burst SRAM) – features synchronous
burst write access to the SRAM to increase write operation to the SRAM

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 DDR SRAM – Synchronous, single read/write port, double data rate I/O
 Quad Data Rate SRAM – Synchronous, separate read and write ports, quadruple
data rate I/O
1.5 SRAM Operation:

An SRAM cell has three different states: standby (the circuit is idle), reading (the data
has been requested) or writing (updating the contents). SRAM operating in read mode
and write modes should have "readability" and "write stability", respectively. The three
different states work as follows:

Standby

If the word line is not asserted, the access transistors M5 and M6 disconnect the cell
from the bit lines. The two cross-coupled inverters formed by M1 – M4 will continue to
reinforce each other as long as they are connected to the supply.

Reading

In theory, reading only requires asserting the word line WL and reading the SRAM cell
state by a single access transistor and bit line, e.g. M6, BL. However, bit lines are
relatively long and have large parasitic capacitance. To speed up reading, a more
complex process is used in practice: The read cycle is started by precharging both bit
lines BL and BL, i.e., driving the bit lines to a threshold voltage (midrange voltage
between logical 1 and 0) by an external module (not shown in the figures). Then
asserting the word line WL enables both the access transistors M5 and M6, which causes
the bit line BL voltage to either slightly drop (bottom NMOS transistor M3 is ON and
top PMOS transistor M4 is off) or rise (top PMOS transistor M4 is on). If the BL voltage
rises, the BL voltage drops, and vice versa. Then the BL and BL lines will have a small
voltage difference between them. A sense amplifier will sense which line has the higher
voltage and thus determine whether there was 1 or 0 stored. The higher the sensitivity of
the sense amplifier, the faster the read operation.

Writing

The write cycle begins by applying the value to be written to the bit lines. If we wish to
write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is
similar to applying a reset pulse to an SR-latch, which causes the flip flop to change

5
state. A 1 is written by inverting the values of the bit lines. WL is then asserted and the
value that is to be stored is latched in. This works because the bit line input-drivers
input are
designed to be much stronger than the relatively weak transistors in the cell itself so
they can easily override the previous state of the cross
cross-coupled
coupled inverters. In practice,
access NMOS transistors M5 and M6 have to
o be stronger than either bottom NMOS (M1,
M3) or top PMOS (M2, M4) transistors. This is easily obtained as PMOS transistors are
much weaker than NMOS when same sized. Consequently, when one transistor pair
(e.g. M3 and M4) is only slightly overridden by the write process, the opposite
transistors pair (M1 and M2) gate voltage is also changed. This means that the M1 and
M2 transistors can be easier overridden, and so on. Thus, cross
cross-coupled
coupled inverters
magnify the writing process.

Bus behaviour

RAM with an access time of 70 ns will output valid data within 70 ns from the time that
the address lines are valid. But the data will remain for a hold time as well (5–10
(5 ns).
Rise and fall times also influence valid timeslots with approximately 5 ns. By reading
the lower part of an address range, bits in sequence (page cycle) one can read with
significantly shorter access time (30 ns).

1.6 Design:

1.6.1 6T SRAM

Figure 1.1 6T SRAM

A typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM is stored on
four transistors (M1, M2, M3, M4) that form two cross-coupled
cross coupled inverters. Thi
This storage
cell has two stable states which are used to denote 0 and 1. Two
additional access transistors serve to control the access to a storage cell during read and
write operations. In addition to such six-transistor
six transistor (6T) SRAM, other kinds of SRAM
chips use 4, 8, 10 (4T, 8T, 10T SRAM), or more transistors per bit. Four-transistor
SRAM is quite common in stand
stand-alone
alone SRAM devices (as opposed to SRAM used for
CPU caches), implemented in special processes with an extra layer of polysilicon,
allowing for very high-resistance
resistance pull-up
pull up resistors. The principal drawback of using 4T
SRAM is increased static power due to the constant current flow through one of the
pull-down transistors.

1.6.2 4T SRAM

Figure 1.2 4T SRAM

Four transistors SRAM provides advantages in density at the cost of manufacturing

complexity. The resistors must have small dimensions and large values.

This is sometimes used to implement more than one (read and/or write) port, which may
be useful in certain types of video memory and register files implemented with multi
multi-
ported SRAM circuitry.

Generally, the fewer transistors needed per cell, the smaller each cell can be. Since the
cost of processing silicon wafer is relatively fixed, using smaller cells and so packing
more bits on one wafer reduces the cost per bit of memory.

Memory cells that use fewer than four transistors are possible – but, such 3T or 1T cells
are DRAM,, not SRAM (even the so-called
so 1T-SRAM).

Access to the cell is enabled by the word line (WL in figure) which controls the
two access transistors M5 and M6 which, in turn, control whether the cell should be
connected to the bit lines: BL and BL. They are used to transfer data for both read and
write operations. Although it is not strictly necessary to have two bit lines, both the
signal and its inverse are typically provided in order to improve noise margins.

During read accesses, the bit lines are actively driven high and low by the inverters in
the SRAM cell. This improves SRAM bandwidth compared to DRAMs – in a DRAM,
the bit line is connected to storage capacitors and charge sharing causes the bit line to
swing upwards or downwards. The symmetric structure of SRAMs also allows
for differentia signaling, which makes small voltage swings more easily detectable.
Another difference with DRAM that contributes to making SRAM faster is that
commercial chips accept all address bits at a time. By comparison, commodity DRAMs
have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over
the same package pins in order to keep their size and cost down.

The size of an SRAM with m address lines and n data lines is 2m words, or 2m × n bits.
The most common word size is 8 bits, meaning that a single byte can be read or written
to each of 2m different words within the SRAM chip. Several common SRAM chips
have 11 address lines (thus a capacity of 2m = 2,048 = 3d words) and an 8-bit word, so
they are referred to as "2k × 8 SRAM".

1.6.3 8T SRAM

Figure 1.3 8T SRAM

For further needs to extremely low supply voltage and fast operation, eight transistor
cell (8T cell) has been proposed. A novel 8T SRAM cell structure to reduce the leakage

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current and dynamic power consumption has been reported in this work . The schematic
of proposed 8T SRAM cell at 65nm technology is as shown in fig. 3. The proposed
SRAM cell composed of write access transistor (M3), controlled by Write Word Line
(WWL) and read access transistor (M8) is controlled by the Read Word Line (RWL).
During the write operation WWL is transitions to high value and RWL and BLB both
are maintained at Vgnd. Hence, the read access transistor (M8) cut OFF. To write „1‟
into the cell Bit Line (BL) is pre charged to a high value, then „1‟ is forced through the
write access transistor (M3). Similarly, to write „0‟ into the cell, BL is discharged.
Hence, to perform write operation the proposed cell utilizing single BL, which could
leads to reduction in the dynamic power consumption and leakage power.

During read operation, RWL is transition to high value and WWL is maintained at
Hence the write access transistor is cut OFF. Prior to read operation BL and BLB are
pre charged to . Assume that „1‟ is stored left and „0‟ is stored right side, then BL
discharged through M7 and M8. Since, „M6‟ is cut OFF there is no path to discharge
the BLB. Hence BLB is held at high value. Alternatively, if „1‟ is stored right side,
BLB is discharged through „M6‟ and „M8‟. Since, „M7‟ is cut OFF there is no path
exists to discharge the BL. Hence, it can maintain at high value. With this, storage
nodes completely isolated from the Bit Lines (BL) during read operation, hence stability
increases significantly.

1.6.4 9TSRAM Cell

Figure 1.4. Schematic of 9T SRAM Cell

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The schematic of the 9T SRAM cell, for CMOS technology, is shown in
Figure.1.4. The upper sub-circuit of the 9T memory circuit is essentially a 6T
SRAM cell with minimum sized devices (composed of M3, M4, M5, M6, M1 and
M2).The two write access transistors (M5 and M6) are controlled by a write signal
(WL). The data is stored within this upper memory sub-circuit. The lower sub
circuit of the new cell is composed of the bit-line access transistors (M7 and M8)
and the read access transistor (M9). The operations of M7 and M8 are controlled
by the data stored in the cell. M9 is controlled by a separate read signal (RD).The
9T SRAM cell completely isolates the data from the bit lines during a read
operation.

1.6.5 10T SRAM Cell

Figure.1.5 Schematic of 10T SRAM Cell

Figure.1.5 shows the schematic of the 10T sub threshold bit cell. Transistors are
identical to a 6T bit cell except that the source of M1 and M2 tie to a virtual
supply voltage rail Vdd. Write access to the bitcell occurs through the write access
transistors, M5 and M6, Transistors from the write bitlines, WBLT and WBLC.
Transistors M8 through M10 implement a buffer used for reading.

Read access is single-ended and occurs on a separate bitline, RBL, which is

precharged to prior to read access. The wordline for read also is distinct from the
write wordline. One key Advantage to separating the read and write wordlines and
bit lines is that a memory using this bit cell can have distinct read and write ports.

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1.6.6 Modified 10T SRAM Cell

Figure.1.6 Schematic of Modified 10T SRAM Cell

Figure.1.6 shows a schematic of a 10T SRAM with differential read bitlines (BL
and BLB). Two NMOS transistors (M9 and M7) for the RBL and the other
additional NMOS transistors (M8 and M10) for BLB are appended to the 6T
SRAM. The 10T cell permits bit interleaving and exhibits superior sense margin
with a differential read path based on a DCVSL (differential cascade voltage-
switch-logic level) structure at the column periphery . There is a performance
degradation from stacked transistors that requires boosted WL voltages, but BL
leakage is reduced at the same time.

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 CHAPTER 2:
LITERATURE SURVEY/REVIEW OF LITERATURE

2.1 Survey on low power and high speed SRAM cell

Shilpa Saxena and Rajesh Mehra (2017) has proposed a method using FinFETs
in this proposed method Fin field-effect transistors (FinFETs) are replacing the
traditional planar metal-oxide semiconductor FETs (MOSFETs) because of superior
capability in controlling short channel effects, leakage current, propagation delay, and
power dissipation. Planar MOSFETs face the problem of process variability but the
FinFETs mitigate the device-performance variability due to number of dopant ions.
This work includes the design of static-random access memory (SRAM) cell using
FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and
with power gating sleep transistors is given in this study using the Cadence Virtuoso
Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET
transistor structure is better than the conventional planar complementary MOS
technology. The proposed design aims at the power reduction and speed improvement
for the SRAM cell. From the result it is clear that optimised proposed FinFET-based
ST13T SRAM cell is 92% more power efficient with the use of power gating
technique, i.e. sleep transistors approach and having 12.84% less delay due to the use
of transmission gates in the access path.
Kundan Vanama,Govind Prasad (2005) has developed a theory where the
power consumption (Static power, dynamic power) and stability (noise margin) are the
major concern areas of today's CMOS technology. Although various approaches have
been developed to reduce the power dissipation, one of the most adopted approaches
to reduce the static power dissipation is to reduce the supply voltage in standby mode,
that technique has been implemented in this paper. In this paper we present a novel
nine transistors SRAM cell to reduce the static power and total power dissipation.
When compared to basic conventional six transistors SRAM cell, the proposed SRAM
cell shows 81.82% reduction in total power dissipation, where stability is almost same
as compare to the conventional six transistors SRAM cell.

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 CMOS SRAM Circuit Design and Parametric Test in Nano scaled
Technologies by Andrei Pavlov and Manoj Sachdev (2008) say that as technology
scales into nano-meter region, design and test of Static Random Access Memories
(SRAMs) becomes a highly complex task. Process disturbances and various defect
mechanisms contribute to the increasing number of unstable SRAM cells with
parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells
with marginal stability and pose strict constraints on transistor parameters
distributions. Standard functional tests often fail to detect unstable SRAM cells.
Undetected unstable cells deteriorate quality and reliability of the product as such cells
may fail to retain the data and cause a system failure. Special design and test measures
have to be taken to identify cells with marginal stability. However, it is not sufficient
to identify the unstable cells. To ensure reliable system operation, unstable cells have
to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled
Technologies covers a broad range of topics related to SRAM design and test. From
SRAM operation basics through cell electrical and physical design to process-aware
and economical approach to SRAM testing. The emphasis of the book is on challenges
and solutions of stability testing as well as on development of understanding of the
link between the process technology and SRAM circuit design in modern nano-scaled
technologies.

Evelyn Grossar, Michele Stucchi, Karen Maex (2006) has proposed SRAM
cell read stability and write-ability are major concerns in nanometer CMOS
technologies, due to the progressive increase in intra-die variability and Vdd scaling.
This paper analyzes the read stability N-curve metrics and compares them with the
commonly used static noise margin (SNM) metric defined by Seevinck. Additionally,
new write-ability metrics derived from the same N-curve are introduced and compared
with the traditional write-trip point definition. Analytical models of all these metrics
are developed. It is demonstrated that the new metrics provide additional information
in terms of current, which allows designing a more robust and stable cell. By taking
into account this current information, Vdd scaling is no longer a limiting factor for the
read stability of the cell. Finally, these metrics are used to investigate the impact of the
intra-die variability on the stability of the cell by using a statistically-aware circuit

13
optimization approach and the results are compared with the worst-case or corner-
based design.

Shyam Akashe, Meenakshi Mishra, Sanjay Sharma (2012) has proposed The
trend of decreasing device size and increasing chip densities involving several hundred
millions of transistors per chip has resulted in tremendous increase in design
complexity. Power dissipation occurs in various forms, such as dynamic, sub threshold
leakage, gate leakage, etc. and there is need to reduce each of these. A low leakage
power, 45-nm 7T SRAM is designed in this paper. The stand-by leakage power of 7T
sram is reduced by incorporating a newly-developed leakage current reduction circuit
called a "Self-controllable Voltage Level (SVL)" circuit. Simulation result of 7t
SRAM design using CADENCE tool shows the reduction in total average power. In
this design seven Transistor (7T) gated-ground sram is used as a Load Circuit. The
Cadence Virtuoso simulation in standard 45nm CMOS technology confirms all results
obtained for this paper.

Tadayoshi Enomoto and Yuki Higuchi (2008) says that a low leakage power,
180-nm 1K-b SRAM was fabricated. The stand-by leakage power of a 1K-bit memory
cell array incorporating a newly-developed leakage current reduction circuit called a
“Self-controllable Voltage Level (SVL)” circuit was only 3.7nW, which is 5.4% that
of an equivalent conventional memory-cell array at a VDD of 1.8V. On the other hand,
the speed remained almost constant with a minimal overhead in terms of the memory
cell array area.

Shyam Akashe, Shishir Rastogi (2011) proposed this paper is based on the
observation of a various CMOS seven transistor SRAM cell for very high density and
low power applications. This cell retains its data with leakage current and positive
feedback without refresh cycle. These various 7T SRAM cell uses one word-line and
one bit-line and NMOS transistor to control. Simulation and analytical results show
purposed cell has correct operation during read/write and also the delay of new cell is
70.15% smaller than a six-transistor SRAM cell. The various new 7T SRAM cell
contains 72.10% less leakage current with respect to the 6T SRAM memory cell using
cadence 45 nm technology and power consumption during read and write operation
are approximate 20.34% less than the conventional 6T SRAM memory cell.

14
 Basavaraj Madiwalar and Dr. Kariyappa B S (2013) say that Memories are
integral parts of most of the digital devices and hence reducing power consumption of
memory is very important in improving the system performance, efficiency and
stability. Most of the embedded and portable devices use SRAM cells because of their
ease of use as well as low standby leakage. Standard CMOS 6T SRAM cell uses two
bit-lines and a word line for both read and write operations. This 6T SRAM cell
consumes more power and shows poor stability at small feature sizes with low power
supply. During read operation, the stability drastically decreases due to the voltage
division between the access and driver transistors. In this paper new 7T SRAM cell is
proposed, which uses single bit-line for both read and write operations. Power
consumption is reduced because of single bit line usage and read stability is very high
compared to conventional 6T SRAM cell. Proposed cell also provides high static noise
margins (SNMs). The proposed 7T SRAM cell is compared with conventional 6T
SRAM cell in terms of power consumed, delay and SNMs. The Proposed 7T SRAM
cell consumes 22.03% less power for write `0' operation, 17.33% less power for write
`1' operation, 17.52% less power for read `0' operation and 21.36% less power for read
`1' operation compared to conventional 6T SRAM cell. The proposed cell has 2.64
times SNM in read state; 1.082 times SNM in hold state and 1.064 times SNM in write
0 state compared to conventional 6T SRAM cell. Schematics are drawn using virtuoso
ADE of Cadence, and all simulations are carried out using Cadence Spectre Analyzer
with 90nm Technology library at 1.8V VDD.

S.Nijantha, Prof. K.A.Dattathreya (2016) propose that static Random Access

Memory (SRAM) is a type of Memory which is faster and more suitable than other
memories such as Dynamic Random Access Memory (DRAM) or Flash Memories.
The main advantage of the SRAM is need not to be refreshed. SRAM is mainly used
for Cache memory in many applications such as Microprocessors, Engineering
Workstations, Mainframe Computers etc…for High Speed and Low Power
Consumption. The Energy Efficiency and Speed of SRAM are the most Crucial issue
for minimizing the power during read and write operations. The Aim of this Paper is to
provide a Energy Efficient Low Power SRAM Cell and here Technique called “Self
controllable voltage level circuits” are used and various Approaches are discussed to

15
Achieve the Better Performance. Simulation result of 9T SRAM cell with reduced
power is implemented using TANNER EDA tool.

V.Rukkumani, M Saravanakumar, K Srinivasan (2016) says that SRAM

memory cell consists of many input signals like precharge, write enable, sense
amplifier enable, read enable and row and column encoders. To develop a novel
SRAM design, different transistor circuits are available. Normally SRAM cell uses
conventional 4 transistor circuit in low power applications. In this thesis, instead of
conventional circuit, 8 transistor (8T) and ten transistor(10T) designs are tried to
improve the power efficiency under various temperature conditions. Initially 8T and
10T SRAM circuits are designed with write driver logic and the power is calculated
for both static and dynamic conditions. Then, charge recycling logic is tried along with
precharge logic with various temperature ranges. From the design, total power, static
power, dynamic power, Transient time, transient delay and static current in 8T SRAM
and 10T SRAM cell are calculated and compared. The 8T SRAM has the least
transistor count and least area efficient, but speed of operation is somewhat reduced.
Further, increase in the transistor count in 10T SRAM cell, however, makes area and
delay large in room temperature. When temperature increases from a particular value,
the 10T SRAM cell performs better than the 8T SRAM cell. This justifies the use of
10T SRAM cell for low power applications with varying temperature conditions. The
proposed SRAM memory design can be implemented in any digital circuit.

A.Agarwal, C. H. Kim, S. Mukhopadhyay and K Roy (2004) propose that

CMOS devices have been scaled down aggressively in each technology generations to
achieve higher integration density and performance. However, the leakage current has
increased drastically with technology scaling and has become a major contributor to
the total IC power. Moreover, the increasing statistical, variation in the process
parameters has emerged as a serious problem in the nano-scaled circuit design and can
cause significant increase in the transistor leakage current. Designing with the worst
case leakage may cause excessive guard-banding, resulting in a lower performance.
Hence, accurate estimation of the total leakage current considering the effect of
random variations in the process parameters is extremely important for designing
CMOS circuits in the nano-meter regime.

16
 A. Agarwal, H. Li, K. Roy (2002) in his paper we propose a novel integrated
circuit and architectural level technique to reduce leakage power consumption in high
performance cache memories using a single Vt (transistor threshold voltage) process.
We utilize the concept of gated-ground (an NMOS transistor inserted between the
ground line and SRAM cell) to achieve a reduction in leakage energy without
significantly affecting performance. Experimental results on gated-ground caches
show that data are retained (DRG-cache) even in stand-by mode of operation. Data are
restored when the gated-ground transistor is turned on. Turning off the gated-ground
transistor in turn gives a large reduction in leakage power. This technique requires no
extra circuitry; the row decoder itself can be used to control the gated-ground
transistor. The technique is applicable to data and instruction caches as well as
different levels of cache hierarchy such as the L1, L2, or L3 caches. We fabricated a
test chip in TSMC 0.25 /spl mu/ technology to show the data retention capability and
the cell stability of DRG-cache. Our simulation results on 100 nm and 70 nm
processes (Berkeley Predictive Technology Model) show 16.5% and 27% reduction in
consumed energy in L1 cache and 50% and 47% reduction in L2 cache with less than
5% impact on execution time and within 4% increase in area overhead.

S. Mutoh et al (1996) propose that a 1-V power supply low-power and high-
speed 16-b fixed-point digital signal processor using a 0.5-/spl mu/m process has been
developed for mobile phone applications. A 1-V multithreshold-voltage CMOS
(MTCMOS) technology that uses both high-threshold-voltage and low-threshold-
voltage transistors is one key to attaining low power consumption, keeping processing
throughput high. A maximum operating frequency of 13.2 MHz and an energy
consumption of 2.2 mW/MHz were achieved at 1 V. The second key to low-power
operation is a power management scheme that uses a secondary embedded
microprocessor. This proposed scheme minimizes the standby power in the waiting
state by effectively controlling the sleep mode in the MTCMOS design. We confirmed
that the standby leakage current was reduced three orders of magnitude and that the
energy consumed in the waiting state was less than 1/10 of that consumed by
conventional CMOS circuits with lowered supply voltage and threshold voltage but
without power management.

17
 G. Pasandi and S. M. Fakhraie (2015) they present a new 9T SRAM cell that
has good write-ability and improves read stability at the same time. Simulation results
show that the proposed design increases Read SNM (RSNM) and Ion/Ioff of read path
by 219% and 113%, respectively at supply voltage of 300mV over conventional 6T
SRAM cell in a 90nm CMOS technology. Proposed design lets us to reduce minimum
operating voltage of SRAM (V DDmin) to 350mV, whereas conventional 6T SRAM
cannot operate successfully with acceptable failure rate at supply voltages bellow
725mV. We also compared our design with three other SRAM cells from recent
literature. To verify the proposed design, a 256kb SRAM is designed using new 9T
and conventional 6T SRAM cells. Operating at their minimum possible VDDs, the
proposed design decreases write and read power per operation by 92%, and 93%,
respectively over the conventional rival. Area of proposed SRAM cell is increased by
83% over conventional 6T one. However, due to large Ion/Ioff of read path for 9T cell,
we are able to put 1k cells in each column of 256kb SRAM block, resulting in the
possibility for sharing write and read circuitries of each column between more cells
compared to conventional 6T. Thus, area overhead of 256kb SRAM based on new 9T
cell is reduced to 37% compared to 6T SRAM.

B. H.Calhoun and P.Chandrakasan (2007) say that Low-voltage operation for

memories is attractive because of lower leakage power and active energy, but the
challenges of SRAM design tend to increase at lower voltage. This paper explores the
limits of low-voltage operation for traditional six–transistor (6 T) SRAM and proposes
an alternative bitcell that functions to much lower voltages. Measurements confirm
that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-
threshold to below 400 mV. At this low voltage, the memory offers substantial power
and energy savings at the cost of speed, making it well-suited to energy-constrained
applications. The paper provides measured data and analysis on the limiting effects for
voltage scaling for the test chip.

Tae Woo Oh, Hanwool, Jeong,et.al (2017) brief proposes a novel power-gated
9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled
access buffer and power-gating transistors to execute reliable read and write
operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error

18
immunity and utilizes a column-based virtual VSS signal to eliminate unnecessary
bitline discharges in the unselected columns, thereby reducing the energy
consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM cell has a
minimum operating voltage of 0.32 V while achieving the 6σ read stability yield.
Compared with the previously proposed 9T SRAM cell, the proposed cell consumes
45% and 17% less energy per read and write operation, respectively, at the minimum
operating voltage, and has a 12% smaller bit cell area.

B.S.K.Lakshmi, R.Vinay Kumar (2013) say that Memories are critical parts of
most of the digital gadgets and therefore reducing energy intake of memory may be
very essential in improving the performance, efficiency and stability. Static Random
Access Memory (SRAM) is faster and greater suitable than other such as Dynamic
Random Access Memory (DRAM) or Flash Memories. The power performance and
speedof SRAM are the most vital difficulty for minimizing the strength all through
read and write operations. The primary cause of this paper is to provide an Energy
Efficient Low Power SRAM cell and right here method called “Self Controllable
Voltage Logic” are used and numerous processes are mentioned to reap the higher
overall performance. Simulation result of SRAM cellular with decreased strength is
carried out using Tanner EDA tool.

David Hentrich,Erdal Oruklu and Japan Saniie (2009) propose that Static
Random Access Memory (SRAM) units are often directly integrated onto the same die
with the microprocessors and influence the design metrics significantly. SRAM often
consumes large percentages of the die size and their leakages significantly contribute
to the static power dissipation of those chips. The main objective of this article is to
characterize the speed and power consumption of five different SRAM cells in a
predictive high performance 22nm transistor process and in a predictive low power
22nm transistor process. The five types of studied cells are traditional 6T, gated-
ground 7T, full Self- Controlled Voltage Level (SVL) 12T, SVL 9T Footed, and SVL
9T Headed. The simulation results indicate that the timing behavior of SRAM cells are
largely the same but power dissipation, leakage power in particular, vary significantly
in 22nm technology. The gated-ground 7T cells are deemed superior in the high

19
performance process, while traditional 6T cells are deemed the best in the low power
process.

Yen Hsiang Tseng, Yimeng Zhang , Leona Okamura (2010) brief about the
conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM
(6T), suffered from the external noise, because they have direct paths through bit-
line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM
which has no direct path through BL to the data storage nodes and has higher
endurance against external noise. The proposed cell is composed of two separate data
access mechanisms; one is for the read operation and another is for the write one.
Based upon our SRAM design, data destruction never occurs in the read operation.
Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell
is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell
respectively. We also manufactured a chip and confirmed its performance.

K. Takeda (2006) through this paper we can know how to overcome the limits
that means it helps to overcome limits to the speed of conventional SRAMs, we have
developed a read-static-noise-margin-free SRAM cell. It consists of seven transistors,
several of which are low-Vth nMOS transistors used to achieve both low-VDD and
high-speed operations. For the same speed, the area of our proposed SRAM is 23%
smaller than that of a conventional SRAM. Further, we have fabricated a 64-kb SRAM
macro using 90-nm CMOS technology and have obtained with it a minimum VDD of
440 mV and a 20-ns access time with a 0.5-V supply.

Kevin .Z (2009) supports and say that Embedded Memories for Nano-Scale
VLSIs provides a comprehensive and in-depth view on the state-of-the-art embedded
memory technologies. The material covers key technology attributes and advanced
design techniques in nano-scale VLSI design. It also discusses how to make decisions
concerning the right design tradeoffs in real product development. This book first
provides an overview on the landscape and trend of embedded memory in various
VLSI system designs, including high-performance microprocessor, low-power mobile
handheld devices, micro-controllers, and various consumer electronics. It then shows
an in-depth view on each different type of embedded memory technology, including
high-speed SRAM, ultra-low-voltage and alternative SRAM, embedded DRAM,

20
embedded nonvolatile memory, and emerging or so-called "universal" memories such
as FeRAM and MRAM. Each topic includes coverage of the key technology attributes
from a product application perspective, ranging from technology scaling challenges to
advanced circuit techniques for achieving optimal design tradeoff in performance and
power. VLSI systems are becoming increasingly dependent on on-die memory to
provide adequate memory bandwidth for various applications and this book gives
readers a broader view of this important field to help them to achieve their optimal
design goals for different applications.

K. Madhukar, Y.Shiva Prasad nayak, N.Ramchander (2016) explains about the

major concerns of SRAM and says that For SRAM power, stability, delay and area are
the major concerns. And they are trade-offs to each other. But all are important and
should be in acceptable range. In this paper we mainly concentrated on power and
stability and we designed an optimized proposed 9T-SRAM for low power
consumption by placing an NMOS transistor between supply voltage VDD and the
latches formed by cross coupled inverters. This NMOS transistor is in diode connected
mode and it scales down the VDD. So total power is reduced by 98%. Because power is
directly proportional to square of VDD. But this effect the stability, as stability
decreases when supply voltage decreases. In order to increase stability an extra PMOS
transistor is placed in between access transistor and pull down transistor. This PMOS
transistor separate's the storage node and writing node of data. It also scales the bit line
voltage and prevent the flipping the contents of cell at low voltages. So stability
parameters like SINM, SVNM, WTI and WTV also increased by 93%, 45%, 86% and
56% respectively. In this proposed cell static power is also reduced by 55% due to
stacking effect. This all values are when compared with Sub-threshold 10T SRAM
cell. This proposed circuit is also tested by giving 0.3 V power supply. Cadence
Virtuoso tools are used for simulation with gpdk-90nm CMOS process technology.

Naman S Kumar, Sudhanva N G ,Shreyas Hande V (2017) discuss about the

major hurdles that is Power consumption is one of the major hurdles in scaling the
technology of memories. Static Random Access Memories (SRAMs), in particular,
contribute to major dissipation of static and dynamic power in processors that are
utilized for building caches, buffers, reservation stations, portable devices, etc. The

21
leakage current is increased to a greater extent because of technology scaling.
Introduction of non-volatility into any system is advantageous. The time required to
start a closed (due to abrupt power loss or forced shutdown) application decreases
when non-volatility exists. This paper proposes a design of SRAM cell utilizing
memristors and Self-Controllable Voltage (SVL) techniques. Simulation on standard
45 nm CMOS technology is done in Cadence Virtuoso. The results obtained show that
leakage power reduces by 90.59% than that of 7T cell.

22
 CHAPTER 3: SOFTWARE

3.1 Cadence Software

Cadence Design Systems, Inc. is an American multinational electronic design

automation (EDA) software and engineering services company, founded in 1988 by the
merger of SDA Systems and ECAD, Inc. The company produces software, hardware
and silicon structures for designing integrated circuits, systems on chips (SoCs)
and printed circuit boards.
It is headquartered in San Jose, California, in the North San Jose Innovation District,
is a supplier of electronic design technologies and engineering services in the electronic
design automation (EDA) industry. The company develops software used to design
chips and printed circuit boards, as well as intellectual properties (IP) covering a broad
range of areas, including interfaces, memory, analog, SoC peripherals, dataplane
processing units, and verification.Cadence design tools are used in a variety of
undergraduate and graduate classes to provide practical experience in the design of
integrated circuits and systems. Additionally, they are used by several research groups
in the design of chips integrating analog, digital, RF and MEMScircuitry, with foundry
fabrication
through EuroPractice, GlobalFoundries, LFoundry, MOSIS, Samsung, STMicroelectron
ics, TowerJazz, and UMC. This page links to the various informational web pages
maintained in these classes and research groups for the benefit of the first time user.

Cadence products primarily target SoC design engineers, and are used to move a design
into
packaged silicon, with products for custom and analog design, digital design, mixed-
signal design, verification, and package/PCB design, as well as a broad selection of IP,
and also hardware for emulation and FPGA prototyping.
To help integrate, verify, and implement complex digital SoCs, there are solutions that
encompass design IP, timing analysis and signoff, services, and tools and
methodologies. The
company also provides products that assist with the development of complete hardware
and software platforms that support end applications.

23
3.2 Cadence products
Cadence’s product offerings are targeted at various types of design and verification task
which include:
 Custom IC technologies - Virtuoso Platform - Tools for designing full-
custom integrated
circuits; includes schematic entry, behavioral modeling (Verilog-AMS), circuit
simulation, custom layout, physical verification, extraction and back-annotation. Used
mainly for analog, mixed-signal, RF, and standard-cell designs, but
also memory and FPGA designs.
 Digital & Signoff technologies - RTL to GDS II implementation: Genus
Synthesis, Joules Power Analysis, Innovus Place & Route, Tempus Timing
SIgnoff, Voltus Power Integrity Signoff, Modus Automatic Test Pattern Generation.
 System & Verification technologies - Verification Suite - JasperGold Formal
Verification, Xcelium simulation, Palladium Z1 emulation, Protium S1 FPGA
prototyping, Perspec software-driven tests, vManager plan & metrics, Indago
debug, and Verification IP catelog.
 Intellectual Property - Design IP targeting areas including memory / storage / high-
performance interface protocols, Tensilica DSP processors for audio, vision, wireless
modems and convolutional neural nets.
 PCB & Packaging technologies: Allegro Platform - Tools for co-design
of integrated
circuits, packages, and PCBs, OrCAD/PSpice - Tools for smaller design teams and
individual PCB designers., and Sigrity technologies - Tools for signal and power
verification for system-level signoff verification and interface compliance. In addition
to EDA software, Cadence provides contracted methodology and design services as
well as silicon design IP, and has a program aimed at making it easier for other EDA
software to interoperate with the company’s tools.

3.2.1 Design flow

Cadence design Systems is electronic design automation software and engineering
Services Company that offers various types of design and verification tasks that include:
Virtuoso Platform - Tools for designing fullcustom integrated circuits, includes

24
schematic entry, behavioral mo
modeling (Verilog-AMS),
AMS), circuit simulation, full custom
layout, physical verification, extraction and back
back-annotation.
annotation. Used mainly for analog,
mixed-signal,
signal, RF, and standard
standard-cell designs. Encounter Platform - Tools for creation of
digital integrated circuits
circuits.. This includes floor planning, synthesis, test, and place and
route. Typically a digital design starts from Verilog netlists. Incisive Platform - Tools
for simulation and functional verification of RTL including Verilog, VHDL and System
C based models. Includes
cludes formal verification, formal equivalence checking, hardware
acceleration, and emulation.

Figure 3.1: Cadence design flow

3.3 Spectre simulator
Spectre is a SPICE-class circuit simulator. It provides the basic SPICE analyses and
component models. It also supports the Verilog-A modeling language. Spectre comes in
enhanced versions that also support RF simulation (SpectreRF) and mixed-signal
simulation (AMS Designer).
Spectre is currently a leading circuit simulator, competing with HSPICE and several
others.
The Spectre Circuit Simulator is an industry-proven, fast, SPICE-accurate and RF
simulator for tough analog RF, mixed signal circuit simulation, and library and IP
characterization. It is tightly integrated with the Virtuoso custom design platform and
provides a comprehensive set of detailed transistor-level analyses in multiple domains
for faster convergence on design goals. Its superior advanced architecture allows for
low memory consumption and high-capacity analysis. Benefits • Provides high-
performance, high-capacity SPICE-level analog and RF simulation with out-of-the-box
tuning for accuracy and faster convergence • Facilitates the tradeoff between accuracy
and performance through user-friendly simulation setup applicable to the most complex
analog and custom-digital ICs • Enables accurate and efficient post-layout simulation •
Supports out-of-the-box S-Parameter models, enabling simulation of complex n-port
devices • Delivers signal integrity analysis capability with an advanced transmission
line library and graphical editor • Provides a platform to measure and analyze system-
level performance metric • Performs application-specific analysis of RF performance
parameters (spectral response, gain compression, inter modulation distortion, impedance
matching, stability, and isolation) • Offers advanced statistical analysis to help design
companies improve the manufacturability and yield of ICs at advanced process nodes
without sacrificing time to market • Delivers fast interactive simulation setup, cross-
probing, visualization, and post-processing of simulation results through tight
integration with the Virtuoso Analog Design Environment • Ensures higher design
quality using silicon-accurate, industry-standard, foundry-certified device models
shared across the simulation engines Features Production-proven circuit simulation
techniques The Spectre Circuit Simulator uses proprietary techniques—including
adaptive time step control, sparse matrix solving, and multi-processing of MOS
models— to provide high performance while maintaining signoff accuracy. It includes
native support for both Spectre and SPICE syntax, giving users the flexibility to use
Spectre technology for any design flow without worrying about the design format.
Additionally, it converges to results that are “silicon-accurate” by modeling extensive
physical effects in devices for deep sub-micron processes. Comprehensive statistical
analysis The Spectre Circuit Simulator bridges the gap between manufacturability and
time to market at advanced process nodes by providing a comprehensive set of
statistical analysis tools tailored to IC design. Advanced Monte Carlo algorithms enable
smart selection of process and design parameters to characterize the yield with
significantly reduced simulation runs. The DC Match capability efficiently analyzes
local process mismatch effects and identifies the yield-limiting devices and parameters.

26
Tight integration between the Spectre Circuit Simulator and the Virtuoso Analog
Design Environment offers user-friendly interactive setup and advanced visualization of
statistical results. Transient noise analysis The Spectre Circuit Simulator provides
transient noise analysis for accurate calculation of the large signal noise in nonlinear
non-periodic circuits. All noise types are supported, including thermal, shot, and flicker.
Spectre Circuit Simulator Figure 2: Spectre Circuit Simulator delivers significant
performance and capacity for accurate analog simulation. www.cadence.com 5 Virtuoso
Multi-Mode Simulation with Spectre Platform Built-in Verilog-A and MDL The
Spectre Circuit Simulator offers design abstraction for faster convergence on results,
including behavioral modeling capabilities in full compliance with Verilog-A 2.0. The
compiled Verilog-A implementation is optimized for compact device models offering
comparable performance to built-in device models. In addition to supporting standard
SPICE measurement functions (.measure), it offers a measurement description language
(MDL) to automate cell and library characterization. Spectre MDL enables the designer
to post-process the results and tune the simulator to provide the best
performance/accuracy tradeoff for a specific measurement. Advanced device modeling
and support The Spectre Circuit Simulator supports MOS, BJT, specialty transistor
models, resistors, capacitors, inductors, transformers and magnetic cores, lossy and
lossless transmission lines, independent and controlled voltage and current sources, and
Z and S domain sources. The Spectre Circuit Simulator provides a user-defined
compiled model interface (CMI). It allows for the rapid inclusion of user-defined
models for a “model once, use everywhere” capability. It offers a curve tracer analysis
capability for rapid model development and debugging. RF simulation Spectre RF, an
option to the Spectre Circuit Simulator, provides a set of comprehensive RF analyses
built on two production-proven simulation engines: harmonic balance and shooting-
Newton. Spectre RF supports all industry-standard models. • Harmonic balance-based
analyses, optimized for high dynamic range, high-capacity circuits with distributed
components • Shooting-Newton-based analysis, optimized for strongly non-linear
circuits • Advanced fast envelope analysis supporting all analog and digital modulation
techniques • Rapid IP2 and IP3 calculation based on perturbation technology • Periodic
noise analysis for the accurate calculation of noise in non-linear time variant circuits
with detailed analysis options including modulated noise, sampled noise, and jitter •
Full spectrum periodic noise provides a fast and silicon-accurate Pnoise analysis for
circuits with sharp transitions • Noise and distortion summary to identify the
contribution of each device to the total output noise, harmonic, or inter-modulation
distortion • Small signal analysis includes AC, transfer function, S-Parameters, and
stability based on a periodic or quasi periodic operating point • Monte Carlo, corner-
case, and parametric sweep analysis Advanced Transmission Line Library Signal-
integrity issues can be very difficult and time consuming to identify, analyze, and
resolve for high-speed designs. The Spectre RF rftline (RF transmission line) library
enables the designer to perform signal-integrity analysis of the design in context of the
package and PCB trace. Spectre rfTlineLib provides a comprehensive set of multi-layer

27
transmission lines and models. Spectre rftline models are based on rigorous 2-D
electromagnetic simulations and include state-of the-art descriptions of dielectric and
conductor losses, delivering accurate models, tightly integrated into Virtuoso ADE. An
intuitive and easy-to-use graphical editor gives the user the ability to accurately define
and graphically capture the substrates. Wireless Analysis The modern mobile platform
with exponentially evolving wireless standards is increasing the complexity of wireless
RFIC designs. To meet specification requirements and productivity goals, designers
must evaluate the system-level performance metrics in an integrated, automated, and
easy-to-use simulation based flow. Spectre RF wireless analysis feature provides a fully
automated flow integrated in Virtuoso ADE, enabling the designer to easily apply the
standard-compliant modulation sources and measure the output to calculate system-
level performance. The simulation is based on an advanced, accurate, and fast envelope
following algorithm in Spectre RF. The wire analysis is designed with the RFIC
designer in mind. It provides an automated setup of simulation parameters and standard-
specific post-processing, eliminating the hassle and tedious nature of working with
changing wireless standard sources. Spectre RF wireless Figure 3: Spectre RF rftline
library enables accurate modeling of transmission line www.cadence.com 6 Virtuoso
Multi-Mode Simulation with Spectre Platform analysis provides a rich set of
visualization that includes EVM, BER, and spectrum. A broad set of wireless standards-
compliant library sources is supported. Co-simulation with Simulink The Math Works
Simulink interface to Spectre Circuit Simulator offers system and circuit designers a
unique integrated environment for design and verification. Designers can insert their
analog and RF schematics and post-layout netlist directly in the system-level block
diagram and run a co-simulation between Simulink and Spectre technologies. Designers
can reuse the same Simulink testbench from system-level design to post-layout
verification, minimizing the unnecessary format conversion while maintaining accuracy
throughout the design flow. Multi-Mode Simulation toolbox for MATLAB Multi-Mode
Simulation toolbox for Math Works MATLAB reads PSF and SST2 files directly in
MATLAB. Users benefit from the rich set of MATLAB mathematical functions to post-
process simulation results from Spectre Circuit Simulator, Spectre APS, Spectre XPS,
and AMS Designer. All sweep types are supported in the toolbox, including Monte
Carlo and parametric. Special data structures are used to store RF signals and harmonics
resulting from PSS and QPSS analysis. Furthermore, the Spectre Simulation toolbox
complements the rich MATLAB libraries with communication product-specific post-
processing functions such as Fast Fourier Transform, third-order intercept point, and
1dB gain compression point. Post-layout simulation The Spectre Circuit Simulator
enables analog and RF block and subsystem post-layout verification at near the speed of
pre-layout simulation. An accurate parasitic reduction technique enhances the
simulation performance of parasitic dominant circuits by a significant amount over
traditional SPICE-level simulation. The technology enables designers to trade-off
accuracy and performance using a simple user-friendly setup.

28
 CHAPTER 4: PROPOSED METHOD
SRAM makes up a large portion of a system-on-chip area, and most of the time,
it also dominates the overall performance of a system. In addition to this, the
tremendous growth in the popularity of mobile devices and other emerging applications,
such as implanted medical instruments and wireless body sensing networks, necessitates
the requirement of low-power SRAMs. Therefore, a robust low-power SRAM circuit
design has drawn great research attention and has become important. However, a design
of robust low-power SRAM faces many process and performance related challenges.
This is because, in deep sub micrometer technology, near/sub threshold operation is
very challenging due to increased device variations and reduced design margins. In
addition, with each technology node, the share of leakage power in the total power
dissipated by a circuit is increasing. Since, most of the time, SRAM cells stay in the
standby mode, thus, leakage power is very important. The increasing leakage current
along with process variations leads to large spread in read static noise margin (RSNM)
and causes read failures at the tail of the distribution.
This approach offers an RSNM that is almost the same as hold SNM (HSNM),
therefore, resulting in better read stability. The conventional 8T uses two extra
transistors in the read path and one extra bitline (BL) for reading. It incorporates two
series-connected transistors in its write path, which degrade the write ability of the
bitcell. It needs write-assist circuits, such as wordline (WL) boosting for a successful
write operation, and, hence, increases dynamic power of the cell. These bitcells address
the read-disturb problem; nevertheless, having cross coupled inverter pair topology,
similar to conventional 8T cell, offers little immunity to process variations at low supply
voltages. For successful SRAM operation under process, voltage, and temperature
(PVT) variations, the stability of the cross-coupled inverter is very important. Therefore,
in this paper, we propose a new single-ended Schmitt-trigger (ST)-based robust low-
power SRAM cell (hereafter referred to as ST11T), which offers high RSNM, reduced
power consumption along with high robustness to PVT variations.
Stability is the major concern in order to improve the system performance,
stability and efficiency. Static Noise Margin (SNM) is useful performance parameter to
measure the stability of a system. Today’s everyone wants low power, stable and fast
accessible device. Though, the high speed devices use SRAM as a cache memory.

29
Mostly SRAM is used in low power and high speed applications because of its fast and
random access. The main and biggest role of low power SRAM in most of the digital
devices is due to their battery life and good stability of portable devices. For proper,
stable and reliable operation in a SRAM cell, appropriate sizing is done according to the
cell ratio and pull ratio up ratio of the transistor. The internal node of SRAM which
stores '0' will be pulled up through the access transistor and the drive transistor. This
increase in voltage severely degrades the SNM mainly during read operation. In this
paper, Schmitt Trigger based SRAM Topology is compared with the conventional 8T
SRAM Cell which has better Read and Write static noise margin.

4.1 Read Stability

The read stability of an SRAM cell is determined in terms of RSNM, and we measure
the RSNM using the method suggested in [28] at different supply voltages. Fig. 3 shows
that the proposed cell offers a higher RSNM at all supply voltages. MC simulation
results for RSNM using 5000 samples with Vdd = 0.45 V are shown in Fig. 4. Fig. 4(a)
shows the RSNM distribution of ST11T and other SRAM cells at a supply voltage of
450 mV. We observe that the proposed cell provides a 26% improvement in the mean
value of the RSNM as compared with the conventional 8T cell.

4.2 Write Ability

The write ability of an SRAM cell can be gauged in terms of write margin [29]. Recent
studies have demonstrated that the write margin technique is more appropriate (as
compared
with the traditional butterfly SNM approach) to measure write ability of an SRAM cell.
In this technique, data to be written are applied on the BLs, and then, WL is swept from
0 V to Vdd that replicates a real write operation. The write margin is defined as the
difference between Vdd and WL voltage at which the nodes Q and QB flips. It is
observed that ST-2 offers best write 0 and write 1 margin. Chang 10T demonstrates
poor write margin because of two series-connected write-access transistors. The
proposed cell offers 1.85× and 1.20× higher write 0 and write 1 margin, respectively, as
compared with Chang 10T. We measure Vdd minimum for the SRAM cells using the
transient analysis.

30
 CHAPTER 5: RESULTS AND DISCUSSION
5.1 Schematic:
In the Cadence software the circuit of the 11T Schmitt triggered based SRAM was
implemented and the respective control signals were applied to the WL/RL ports based
on the operation i.e to perform the read and write operation as shown in figure 5(a).
When the control signal is HIGH it will either read or write the data from the bitline BL
and when it was LOW the SRAM was in HOLD state, where it retains the data stored
after the write operation.

Fig 5.1: 11-T SRAM schematic

5.2 SPECTRE simulation for VTC to obtain SNM:

Using the SPECTRE simulator the transient analysis is performed and the VTC graph
is obtained. From the butterfly curve shown in fig 5(b) obtained the SNM for the read
operation is calculated by determining the area under the curve.
Steps to measure SNM:
 Fit the largest square in the butterfly.
 A higher SNM indicates better read stability
 During a write, WL is at VDD, and the data is driven onto the BLs
 Break the feedback from the cross-coupled inverters
 Plot voltage transfer characteristics (VTCs) of the inverter in the half circuit as
shown below (V2 vs V1 and V1 vs V2).

31
 Fig 5.2: Butterfly curve of 11T SRAM

Fig 5.3: Butterfly curve of 8T SRAM

On comparing the above two graphs it can be observed that the 11T SRAM has better
SNM compared to the 8T SRAM. Here, VTCs of the two halves are not the same but
since one of the BL is driven to VDD and other to 0 (asymmetry). Write NM is the side
of the largest square fitted in between the two curves.

5.3 Parametric analysis:

Parametric analysis performs multiple iterations of a specified standard analysis while
varying a global parameter, model parameter, component value, or operational
temperature. The effect is the same as running the circuit several times, once for each
value of the swept variable. The parametric analysis was performed with respect to the
temperature where we will know how the SRAM cell behavior changes with the
temperature. The variation of the output response with change in the temperature is

32
shown in figure 5(c). For a temperature analysis, PSpice A/D reruns standard analyses
set in the Simulation Settings dialog box at different temperatures.

Fig 5.4: Parametric analysis with respect to temperature

We can specify zero or more temperatures. If no temperature is specified, the circuit is

run at 27°C. If more than one temperature is listed, the simulation runs once for each
temperature in the list.

Temperature Vdd
-40 999.82mV
7.5 316.776mV
55 351.859mV
102.5 396mV
150 451mV
Table 1: Parametric results

33
 CHAPTER 6: CONCLUSION

This paper presented a robust low-power single-ended SRAM cell. The proposed cell
significantly improved HSNM and RSNM while consuming least energy per operation
among all the considered cells. The leakage power is also found to be smallest for this
cell. The proposed SRAM cell has 2.02× areas overhead over 8T SRAM cell. However,
6.9× higher ION/IOFF ratio of the proposed cell holds potential for significantly
subsiding this area overhead by making it possible to connect larger number of cells
with a BL. MC simulations incorporating PVT variations further confirmed the
robustness of the design in terms of read and write operation. However, the single-
ended read and write operation
in this cell affects read/write delay; nevertheless, the proposedcell could be an attractive
choice for low-power applications where RSNM is of prime concern. The proposed
SRAM cell demonstrates significant immunity to half-select disturb issue. Finally, a
new metric (denoted by SAPR) has been proposed that comprehensively weighs the
tradeoffs among various performance parameters of an SRAM cell. The proposed cell
has the second best SARP among all the cell configurations considered in this paper.

34
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