ANNA UNIVERSITY

REGIONAL CAMPUS COIMBATORE

VLSI AND CHIP DESIGN – EC3552

ADSHAYA B R
PRAKASH RAJ J S
KAVI BHARATHI T
POORANA KUMAR
R
 LOW POWER,HIGH SPEED
4-BIT
MAGNITUDE COMPARATOR
ABSTRACT

In this paper,we present a 4-bit magnitude comparator designed for low

power consumption and high-speed performance. Leveraging advanced
CMOS technology, it employs sub-threshold logic, voltage scaling, and
parallel comparison for reduced power usage and fast operation.
Transistor sizing optimization balances power and speed. Through
thorough simulation and analysis, we evaluate metrics such as power
consumption and power-delay product. Comparative assessments
highlight the advantages of this design, making it ideal for applications
demanding both power efficiency and responsiveness, such as IoT
devices and embedded systems.
N-BIT COMPARATOR:

CONVENTIONAL CMOS DESIGN OF 4 BIT COMPARATOR:

To find comparison of magnitude of two 4bit numbers we have a similar procedure. Input A=AAAA: B-BBBB..
To examine whether A<B or vice-versa then firstly test MSB of both inputs. If MSB both the inputs are
different i.e.; if A, B, then A>B, & A<B in vice versa. If MSB are equal of both inputs, then go for next
consecutive bit and then compare next bit of both the inputs. A-B will Come in case of same inputs.
TRUTH TABLE
• TRUTH TABLE FOR 4-BIT MAGNITUDE COMPARATOR
 PROGRAM
• VERILOG CODE:
module comparator(a, b, eq, lt, gt);
input [3:0] a, b;
output reg eq, lt, gt;

always @(a, b)
begin
if (a == b)
begin
eq = 1'b1;
CONTINUED….

lt = 1'b0;
gt = 1'b0;
end
else if (a > b)
begin
eq = 1'b0;
lt = 1'b0;
gt = 1'b1;
end
CONTINUED…..

else
begin
eq = 1'b0;
lt = 1'b1;
gt = 1'b0;
end
end
endmodule
OUTPUT:
CONCLUSION

Thus, this project achieved a 4-bit magnitude comparator that strikes a

harmonious balance between low power consumption and high-speed
operation. Leveraging advanced CMOS technology, sub-threshold logic,
and parallel comparison techniques, it excels in power efficiency, making it
suitable for battery-powered devices and energy-efficient applications. The
optimized transistor sizing and efficient resource utilization ensure rapid
response times, even in high-frequency scenarios. Comprehensive
simulation and analysis quantified power consumption and power-delay
product, while comparative assessments underscored its advantages over
existing designs. This low-power, high-speed comparator proves its
versatility in diverse applications, meeting the demands of modern digital
systems.
THANK YOU