A Seminar Report on

Low-Power SAR ADC Design: Overview and Survey

of State-of-the-Art Techniques

Submitted By
ISMAIL
(4NM19EC066)
Section: B

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

N.M.A.M. INSTITUTE OF TECHNOLOGY, NITTE - 574110
2022 – 2023
 Department of Electronics and Communication Engineering

CERTIFICATE

This is to certify that ISMAIL(4NM19EC066), a bonafide student of N.M.A.M. Institute

of Technology, Nitte has submitted the report for the seminar entitled “Low-Power
SAR ADC Design: Overview and Survey of State-of-the-Art Techniques” in partial
fulfillment of the requirements for the award of Bachelor of Engineering Degree in
Electronics and Communication Engineering during the year 2022-2023.

Name of the Reviewer Signature with date

…………………………….. ………………………………..
 Low-Power SAR ADC Design

INFERENCE AND CONCLUSION DRAWN FROM REFERED

PAPER

In the real world, analog signals have continuously changing values which come from
various sources and sensors which can measure sound, light, temperature or
movement. Digital circuits on the other hand work with binary signal which have only
two discrete states, a logic “1” (HIGH) or a logic “0” (LOW). So, it is necessary to have
an electronic circuit which can convert between the two different domains of
continuously changing analog signals and discrete digital signals, and this is where
Analog-to-Digital Converters (ADC) is used. In ADC's the original analog signal is
filtered by an anti-aliasing filter to remove any high-frequency component in the signal.
The signal is passed through a sample and hold circuit, which then has to be quantized
into an N-bit digital word. The accuracy of the digitized signal is dependent on two
things: the number of samples taken and the resolution, or number of quantization
levels, of the converter.

Among the several kinds of ADC available, one of the most commonly used is
successive approximation register (SAR) ADC. The basic SAR is shown figure 1. An
overview of basic SARs is as follows: A 1 is applied to the input of the shift register.
For each bit converted, the 1 is shifted to the right 1-bit position. BN - 1 = 1 and BN − 2:
B0 = 0. The MSB of the SAR, DN − 1 , is initially set to 1, while the remaining bits, DN − 2
: D0 , are set to 0. Since the SAR output controls the DAC and the SAR output is
𝑉𝑟𝑒𝑓
100...0, the D A C output will be set to .VIN is compared to DAC output. If Vin
2
𝑉𝑟𝑒𝑓 𝑉𝑟𝑒𝑓
≥ then comparator output is 1 and DN − 1 remains at 1. If VIN < then
2 2

comparator output is 0 and comparator resets DN − 1 to 0. DN − 1 is the actual MSB of

the final digital output code. The 1 applied to the shift register is then shifted by one
position so that BN − 2 = 1, while the remaining bits are all 0. Figure 2 shows how this
can be accomplished using a flow chart.

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Figure 1 Basic SAR Figure 2 SAR Flow chart

A SAR ADC can suffer from various types of errors that can reduce its effective
resolution in different ways. A well-designed SAR ADC should have a signal-to-noise-
and-distortion ratio (SNDR) that is limited primarily by noise, not distortion. Noise
reduction typically requires increased power consumption. Most of its noise is
generated by the sampling noise and the comparator noise. Accurate sampling is the
foundation of the SAR conversion. There are two major error sources during the
sampling process: clock jitter and sampling noise. Jitter is the variation in a signal's
timing from its nominal value. Quantization noise comes from the process of mapping
an infinite number of analog voltages to a finite number of digital codes. When the
SAR conversion phase is in progress, the reference buffer and DAC switches
contributes to noise. The comparator is the key circuit block that converts an analog
voltage into a digital output. A comparator usually consists of a pre-amplifier that
amplifies the input signal, followed by a latch that uses positive feedback to resolve
the final decision. The effect of the pre-amplifier is to attenuate the large offset, noise,
and kickback from the latch. With a sufficient pre-amplifier gain, the comparator noise
are typically set by its pre-amplifier.

The dynamic comparator offers a smaller gain, stronger common-mode and power
supply rejection, and greater robustness against process, voltage, and temperature
(PVT) variations while consuming static current, it is often inefficient in terms of energy
consumption. In order to save power, dynamic preamplifiers are becoming
increasingly popular. Strong-arm latches have been widely used as the comparator in
SAR ADCs. Despite its speed and energy efficiency limitations, it has a limited

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performance. Many researches have been conducted to improve the comparator

design techniques.

The paper first discusses low-power design techniques for a standalone comparator.
They found that in order to achieve higher energy efficiency it was necessary to
increase the effective pre-amplification gain. However, the pre-amplifier consumes the
majority of the power in a low-noise comparator design, approximately 80%. Hence,
there is a strong need to improve the energy efficiency of the pre-amplifier itself. To
save the pre-amplifier reset power, we can use bi-directional dynamic comparator. As
shown in Figure 3, the pre-amplifier stage consists of both NMOS and PMOS input
pairs. During the first half of the pre-amplification phase, the PMOS pair switches on
so that the pre-amplifier loads are charged up from ground. Once they cross half 𝑉𝐷𝐷 ,
the PMOS side turns off, and NMOS pair turns on to perform the second half of the
pre-amplification. As a result, the pre-amplifier loads return to their initial condition,
2
which avoids the reset power. It only consumes an energy of 𝐶𝑋 *=𝑉𝐷𝐷 while realizing
the same gain and noise performance as the conventional design. Theoretically, it can
improve the pre-amplifier energy efficiency by 2 times. Limited by the extra circuits
needed for operation control, the overall comparator energy efficiency improvement is
1.5 times compared to that of a Strong-Arm latch which is shown in figure 4.

In addition to designing an energy-efficient comparator, we can also reduce the total

comparator power by using the architectural level properties of a SAR ADC. A SAR
ADC with N bits requires its comparator to fire N times, but the noise requirements
vary for different comparisons. For a small comparator input, the comparator noise
needs to be low. The noise requirement of a comparator can, however, be significantly
relaxed if the input is large while still producing the correct decision. The comparator
input is less than LSB/2 only once out of N comparisons to save energy, the noise
requirement can be loosened for all other comparisons. Unlike the conventional design
where the low noise comparator fires for every N decision, in this strategy it only fires
twice and thereby reduce the total comp power by 55%.DAC switching power
contributes significantly to the overall power consumption. There are many switching
techniques, but conventional switching consumes a lot of power. Other switching
techniques include monotonic, bi-directional, VCM, split-cap, and CAS. In terms of
emerging switching techniques, VCM-based and split-capacitor-based schemes are
recent favorites because they combine energy efficiency with simplicity of

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implementation and good common-mode control. The detect-and-skip technique is

widely used in high-resolution designs with large DAC capacitances to reduce
switching energy.

Figure 3 Bi directional dynamic comparator Figure 4 Schematic of Strongarm latch

To improve power and area efficiency, the designer should minimize the DAC
capacitor size towards the fundamental thermal noise limit. Due to the shrinking
feature sizes, mom capacitors provide energy efficiency improvement and gained
popularity recently as it eliminated the need for additional masks in metal-insulator-
metal (MIM). Power is consumed by both active and leakage circuits in digital circuits.
In spite of the technology scaling automatically, researchers have developed
techniques to further reduce active and leakage power consumption, such as
simplified SAR logic and power gating and has proven very effective to lower the
supply voltage at the cost of potential speed limitation. Adopting asynchronous
operation can greatly reduce the amount of power required for clock generation and
distribution. Further improvements to SAR ADC performance are challenged by noise,
mismatch, and other physical constraints. Researchers are currently exploring a few
future trends like Search Algorithm Optimization, System-Level Co-Optimization,
Hybrid SAR Converters, SAR Design Automation. Finally, SAR architecture has
already succeeded in a wide variety of industry applications. SAR-based data
converters will continue pushing state-of-the-art energy efficiency with the emerging
techniques and innovations in recent years. These techniques can be used by
designers to find the right low-power techniques for particular design targets, and can
be a good starting point for new SAR-related research.

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REFERENCES

[1] McCreary and P. R. Gray, “All-MOS charge redistribution analog to-digital

conversion techniques. I,” IEEE J. Solid-State Circuits, vol. SSC-10, no. 6, pp.
371–379, Jun. 1975.
[2] H. S. Bindra, C. E. Lokin, D. Schinkel, A.-J. Annema, and B. Nauta, “A 1.2-V
dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise,”
IEEE J. Solid-State Circuits, vol. 53, no. 7, pp. 1902–1912, Jul. 2018
[3] T.-Y. Wang, H.-Y. Li, Z.-Y. Ma, Y.-J. Huang, and S.-Y. Peng, “A bypass-
switching SAR ADC with a dynamic proximity comparator for biomedical
applications,” IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1743–1754, Jun.
2018.

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REFERRED PAPER

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