Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018)

IEEE Xplore Compliant Part Number: CFP18K74-ART; ISBN:978-1-5386-2842-3

Design and simulation of modified ultra low power

CMOS Comparator for Sigma Delta Modulator

Monika Gangwar Atul Kumar Nishad

M.Tech (VLSI Design) Dept. of electronics and communication
NIT Kurukshetra NIT kurukshetra
Harayana Haryana
moni.gangwar@gmail.com

Abstract—Comparator plays a very important role in most of

the analog circuits like ADC and DAC and the performance of
these analog circuits is majorly influenced by the choice of the
comparator. A low power and high speed comparator is required
for high speed Analog to digital converter. In this paper a well
defined and improved design of CMOS comparator is presented
which is suitable for Ultra Low power Sigma to Delta Converter.
The comparator design is a modified design of two stage CMOS
op-amp. The proposed comparator is realized using Cadence
Virtuoso. Design and Simulation are carried using 180nm CMOS
process technology and 1.8 power supply. Input voltage and Fig. 1.Basic operation of comparator
reference voltage are taken as 1V and 0V respectively for
comparison. The results of the proposed comparator are
II. TWO STAGE OPEN LOOP COMPARATOR
compared with the earlier work done [1], [3], [4] and hence we
can clearly see the improvement in power dissipation of the Two- stage open loop comparator is basically a two stage
proposed comparator. With the proposed comparator design we op-amp. Here the only difference is of compensated network
achieve ultra low power consumption of 21.16uW consisting of capacitor. Comparator doesn’t need
compensation network because its function is to switch rail to
Keywords—comparator, sigma delta, cadence, virtuoso, ADC, rail. Compensation in two stage op-amp is needed to improve
DAC. stability but here stability is not needed as it will only slow
down the switching speed. So, to improve the speed of op-amp
I. INTRODUCTION here we remove the compensation part. Also, if the
comparator is not compensated it will have the largest B.W
Analog to Digital Converter are widely used electronic
possible and have a faster response.
component to convert analog to digital signals. The increased
integration of different components on a single chip and
battery powered biomedical appliances require a low power
and low voltage ADC. Sigma delta ADC’s are the most
suitable ADC for low power and high performance
applications as they are structured simply with low accuracy
analog parts. Sigma delta ADC consists of a modulator and
decimator filter. The modulator comprises of summing
amplifier, integrator, comparator and 1-bit DAC. The
performance of this ADC extensively depends on the
performance of comparator. So A comparator with low power
dissipation is required and used in analog and digital systems.
Comparator basically compares one analog signal with a
reference voltage or other analog signal and produce an output
(binary signal) on the basis of comparison. So it is also called
as 1-bit ADC. The basic operation of the comparator is shown
by fig.1. Fig. 2. Two stage open loop comparator

The above fig. represents the two stage op-amp based

comparator. There are two stages in this comparator. One is
the differential stage and other is a common source stage to
increase the gain of the comparator.

978-1-5386-2842-3/18/$31.00 ©2018 IEEE 1425

Authorized licensed use limited to: Norges Teknisk-Naturvitenskapelige Universitet. Downloaded on July 03,2022 at 14:43:44 UTC from IEEE Xplore. Restrictions apply.
 Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018)
IEEE Xplore Compliant Part Number: CFP18K74-ART; ISBN:978-1-5386-2842-3

III. PROPOSED DESIGN IV. SIMULATIONS AND RESULTS

The proposed design of two-stage open loop Comparator The simulations are performed using Cadence Virtuoso suit in
also has two stages. First stage is differential input stage which 180nm process technology.
comprises of transistor Q1, Q2, Q6, Q7. The second stage is
differential stage used for additional voltage gain comprise of
transistor Q5, Q8.

Fig. 4. Design results of proposed comparator

Fig. 3. Proposed design of open loop two stage comparator

Transistor Q3 and Q4 are used for biasing. The power

supply used here is VDD=1.8V and VSS= -1.8V. The inputs
are applied on the PMOS Q1 and Q2. Input voltage applied
here is sinusoidal with amplitude of 1V and reference voltage Fig. 5. Power consumption of proposed comparator
is taken as 0V. Now when the VIN >VREF then the comparator
will give logic high i.e. 1.8V and when VIN < VREF then the
The gain of the comparator is found to be 54db and phase
comparator output will give logic low i.e. -1.8V. The resistor
margin of 47degree. The power consumption of this proposed
value taken here is 175KΩ.
comparator is calculated as 21uW. Table II given below shows
the comparison of present work with the earlier reported work
TABLE I. ASPECT RATIO OF TRANSISTORS OF PROPOSED DESIGN
and we noted the improvement in power consumption of
present proposed design.
Transistors W/L
PMOS Q1 1/1
TABLE II. COMPARISON OF RESULTS OF PROPOSED DESIGN WITH
PMOS Q2 1/1 EARLIER DESIGN
PMOS Q3 10.6/1 Design Earlier Earlier Earlier Proposed
parameters work by work by work by design
PMOS Q4 1.77/1 [1] [3] [4]
PMOS Q5 2.66/1 Power 5V 5V 2.5V 1.8V
NMOS Q6 1.77/1 supply
CMOS 1um 0.8um 0.5um 1.8um
NMOS Q7 1.77/1
Technology
NMOS Q8 1/1 Power 1.8mW 0.8mW 0.31mW 21uW
consumption
Input range 2V 2-3V 2.5V 1.8V

978-1-5386-2842-3/18/$31.00 ©2018 IEEE 1426

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 Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018)
IEEE Xplore Compliant Part Number: CFP18K74-ART; ISBN:978-1-5386-2842-3

V. CONCLUSION
This paper represents the modified CMOS comparator
design and simulation results of low power consumption.
Proposed design was based on two stage CMOS op-amp
where we remove the compensation part to achieve the better
results. This comparator is designed for ultra low power sigma
to delta converters. Simulation results are obtained by using
1.8 power supply and cadence 180nm process technology.
With the proposed design we achieve power consumption of
21uW which is very low as compared to earlier work by [1],
[3], [4] shown in Table II.

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