Date: 11/11/20

Advanced VLSI Design Lab (EC17203)

EXPERIMENT NO. 9
Aim: To design and simulate CS Amplifier with active and passive load and find the
transconductance.

Tools used: SymicaDE 3.1.0.0209

Theory:
In electronics , a common-source amplifier is one of three basic single-stage
field-effect transistor (FET) amplifier topologies , typically used as a voltage or trans-
conductance amplifier. The input being a voltage between the gate and ground, and
the output being a voltage between the drain and ground. A MOSFET can operate as
a resistor if its gate and drain terminals are shorted. In CMOS technology it is difficult
to fabricate resistors with tightly controlled values of physical size. Hence the load
resistor RD is replaced by the MOS transistor. In circuit design, an active load is a
circuit component made up of active devices, such as transistors, intended to present
a high small-signal impedance yet not requiring a large DC voltage drop, as would
occur if a large resistor were used instead. CS stage with resistive load con- verts the
changes in overdrive voltage, to a small signal drain current, which then passes
through load resistor, R d to produce an output voltage,
Here the gain of the amplifier is given by replacing the R D with the corresponding load
resistance of NMOS and PMOS diode connected loads.
For PMOS diode connected load,
An = - gm1

a) b)
Fig.9.1 Circuit diagram of CS amplifier with a)PMOS active load and b)resistive load
Circuit Diagram:

Figure 9.2 Schematic of CS amplifier with active load

Figure 9.3 Schematic of CS amplifier with resistive load.

Observation:

Figure 9.4 transient analysis of CS amplifier with resistive load.

Figure 9.5DC analysis of CS amplifier with resistive load

 Figure 9.6 DC analysis of CS amplifier with active load

CS amplifier With resistive load With active load

Transconductance(amp/v) 1.6m 399.4µ
Gain(v) -3 -5.9
Table9.1: observation

S. No. Parameters Value

1 CMOS Technology PTM 130nm
4 VDD 1.8V
5 Input Pulse V1 = .9V, V2 = 0V, per=500n, pw=60n
2 NMOS (W/L) 200nm/180nm
3 PMOS (W/L) 200nm/180nm

Table 9.2: Design specifications of CMOS Inverter:

Result:
 CS amplifier with active and resistive load were designed successfully and
simulated using symica DE.
 The transient analysis and DC analysis was also obtained for the same