Date: 4/11/20

Advanced VLSI Design Lab (EC17203)

EXPERIMENT NO. 8
Aim: To design and simulate D-Flip Flop as master-slave configuration.

Tools used: SymicaDE 3.1.0.0209

Theory: A flip-flop is a device where output remains either low or high. The high state
is 1 called, SET state and Low state is 0 called, RESET state. The D-type flip-flop is a
modified Set-Reset flip-flop with the addition of an inverter to prevent the S and R
inputs from being at the same logic level. A Master Slave flip flop is the cascaded
combination of two flip-flops among which the first is designated as master flip-flop
while the next is called slave flip-flop. Those two flip-flops can be J-K, S-R or D flip-
flop. The master-slave configuration has the advantage of being edge-triggered,
making it easier to use in larger circuits, since the inputs to a flip-flop often depend on
the state of its output. The circuit consists of two D flip-flops connected together.
When the clock is high, the D input is stored in the first latch, but the second
latch cannot change state. When the clock is low, the first latch's output is stored
in the second latch, but the first latch cannot change state.

clk D Q Q’
0 0 Q Q’
0 1 Q Q’
1 0 0 1
1 1 1 0

Fig.8.1 Circuit diagram of Master Slave D-FF Table 8.1 Truth Table of D-FF
Circuit Diagram:

Figure 8.2 Schematic of D Flip-Flop

Figure 8.3 Schematic of Master Slave Configuration

Observation:

Figure 8.4 Output waveform of D-FF Master Slave

S. No. Parameters Value

1 CMOS Technology PTM 130nm
4 VDD 1.8V
5 Input Pulse V1 = 1.8V, V2 = 0V, per=200n, pw=60n
2 NMOS (W/L) 360nm/180nm
3 PMOS (W/L) 720nm/180nm

Table 8.2: Design specifications of CMOS Inverter:

Result:
 Master Slave configuration of D Flip-Flop has been successfully designed
using SymicaDE tool.
 The transient analysis was also obtained for the same