MECHATRONICS LAB

ME 140L

FLIP-FLOPS, SEQUENTIAL CIRCUITS,

AND 555 TIMER

I. FLIP-FLOPS: SEQUENTIAL CIRCUITS

Combinatorial Circuits: output depends only on the present states of the inputs.

Sequential Circuits: output depends upon its present/previous state and present state of
the inputs and the transitions (state changes) are timed. Used for memory.

A. FLIP-FLOPS: synchronous bistable devices

Commands and processes in a digital computer are based on sequential steps,
usually governed by a clock.

Sychronous: clock triggers when changes of state can occur

Bistable: two states (set/reset or 1/0)
Clock: Edge-Triggered
Changes in output state only occurs when the clock goes from:
Low to high (0 to 1: leading/rising edge-triggered) or
High to low (1 to 0: trailing/falling edge-triggered)

Note: traling edge-triggered also denoted by a circle on the IC or with a

bar on a pin input.

Applications: Flip-Flops are used for:

Memory storage
Counting (base 2)
Shifting (parallel to serial)

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B. S-R Flip Flop: Inputs S(set) and R(reset), Output Q

Clocked S-R Flip Flop

Used as switch debouncer.

Note: Use with R=S=1 is not valid, output can be 1 or 0.

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C. J-K Flip Flop:: Inputs JJ(set) and K(reset), Output Q
Most common Flip--Flop (made from logic gates)

Note:
circuit on
right is
shown
as falling
edge FF

Note: symbol and truth table shown as leading (rising) edge-triggered

triggered JK FF.

Symbol Truth Table

Recall for this JK-FF,

FF, changes only occur on the rising edge of the clock

Toggle: change state when J=K=1

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D. T-Flip-Flop (Toggle): Change state---J=K=1

Change state on every clock pulse (just like JK FF when J=K=1)

E. D-Flip-Flop (Latch): Output=Input at Clock

Used to store binary data

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Example: For the following trailing edge triggered JK flip-flop circuit, determine the
outputs C, B, A, and Q. Assume they all start at zero states.

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F. Applications

Frequency Divider: output frequency half that of the clock frequency

Counters: 3-bit up-counter (counts 0-7):

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II. 555 TIMER
Timing device that provides a single pulse or sequence of pulses of varying
duty cycles.

Duty Cycle
• 555 Timer provides duty
cycle from 50% to 100%

555 Timer (Astable Mode)

Four Components
Voltage Divider
1/3 Vcc
2/3 Vcc
Op-amp Comparators & Flip-Flop
• When V2 (Trigger) <Vcc/3
Sets FF (S=1)
• When V6 (Threshold) >2Vcc/3
Resets FF (R=1)
Note: FF output is the base of
the npn transistor

npn Transistor
• V7 (Collector) “discharges” the
external timing capacitor to
ground when V3 (output) goes
LOW—acts as a switch

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 External RC circuit has different
RC time constants

• Discharge (7): R2 and C

Determines Off-time

• ChargeThreshold (6): R1, R2

and C
Determines On-time

By varying R1, R2 and C, one can change the duty cycle (see prelab
handout) and frequency

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In next week’s lab, will count the timer pulses and display sequentially
the numbers 0 through 9. Change speed of count by changing R1, R2,
C.

555 Timer IC
• Provides pulses of varying pulse width

7490 Decade Counter IC

• Counts ten cycles (0-9) and outputs a Binary Coded Decimal
(BCD) 4-bit output (QD QC QB QA)=pins(11 8 9 12)

Number BCD output Number BCD output

0 0000 5 0101
1 0001 6 0110
2 0010 7 0111
3 0011 8 1000
4 0100 9 1001

7447 Binary Coded Decimal (BCD) to 7-segment Display

Driver IC
• Takes the BCD output and lights the proper LED in the 7-segment
display.

Example: if the BCD=0011 (represents 3), will light a,b,c,d,g LEDs

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7-segment Display

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