UNIT

4 Special ICs

Functional block, characteristics of 555 Timer and its

PWM application - IC-566 voltage controlled oscillator
IC; 565-phase locked loop IC, AD633 Analog multiplier
ICs.
 IC 555 TIMER
The 555 timer IC is a monolithic timing circuit that can produce accurate & highly stable time delays or
oscillation. The timer basically operates in one of two modes: either Astable or Mono-stable mode.

(i) Astable (free running) multivibrator:

It is also known as self triggering or free running mode. It has no stable state. It has two quasi stable
states that automatically changes from one to another. It changes from high to low state and low to high
state without any trigger input after pre determine time. This mode is used to generate square wave
oscillations, clock pulse, PWM wave etc.
(ii) Mono-stable (one - shot) multivibrator:
It is also known as single shot mode. It has one stable state and one quasi stable state. It jumps into quasi
stable state from stable state when trigger input is applied and comes back to stable state after pre
determine time automatically. It is used in generating pulses, time delay etc.

The important features of the timer are these:

(i) It operates on +5V to +18 V supply voltages
(ii) It has an adjustable duty cycle
(iii) Timing is from microseconds to hours
(iv) It has a current output.
 IC 555 TIMER: FUNCTIONAL BLOCK DIAGRAM
From the circuit, three 5KΩ internal resistors act as
voltage divider providing bias voltage of 2/3Vcc to the
Upper Comparator (UC) and 1/3Vcc to the Lower
Comparator (LC). A control voltage (pin 5) accepts a
modulation control input voltage applied externally.
In the standby (Stable) state makes the output Q of the
control flip-flop is HIGH. This makes that the output is
LOW because of power amplifier which is basically an
inverter.
When a negative going trigger pulse applied at pin2, the
negative edge of the trigger passes through 1/3Vcc,
the output of the lower comparator becomes HIGH
and sets the control FF making Q=1and Q=0.
When threshold voltage at pin6 exceeds 2/3Vcc, the
output of the upper comparator goes HIGH and resets
the control FF with Q=0 and Q=1.
The reset terminal at pin4 provides a mechanism to reset
the timer by grounding or reducing its voltage level
below 0.4V. This makes the output low, overriding the
operation of lower comparator.
 IC 555 TIMER: Mono-stable Mode Operation
When a negative ( 0V ) pulse is applied to the trigger
input (pin 2) of the Monostable configured 555 Timer
oscillator, the lower comparator detects this input and
“sets” the state of the flip-flop, changing the output
from a “LOW” state to a “HIGH” state. This turns
“OFF” the discharge transistor Q1 connected to pin 7,
thereby removing the short circuit across the external
timing capacitor C. This action allows the timing
capacitor C to start to charge up through
resistor R, until the voltage across the capacitor reaches
the threshold (pin 6) voltage of 2/3Vcc set up by the
internal voltage divider network. Now the upper
comparator output goes “HIGH” and “resets” the flip-
flop, back to its original state which is turns “ON” the
transistor Q1 and the capacitor discharges to ground
through pin 7. This causes the output to change its state
back to the original stable “LOW” value awaiting
another trigger pulse to start the timing process over
again. The Mono-stable Multivibrator has only “ONE”
stable state.
 IC 555 TIMER: Mono-stable Mode Operation
Voltage across the capacitor Vc is given by
 

Vc = Vcc (1 -
At t=T, Vc = (2/3)Vcc
Therefore, (2/3)Vcc = Vcc (1 -
Or, T=RC ln (1/3)
Or, T=1.1RC (seconds)
 IC 555 TIMER: Mono-stable Mode Operation
Example: Graph of RC combinations for
different time delays
R=100K, time delay T=100ms.
Calculate the value of Capacitor C.

Solution:
 IC 555 TIMER: Mono-stable Mode Operation
Example:
Design a monostable multivibrator using
555 Timer for a pulse period of 1ms.

Solution:
Time period of pulse T=1.1RC
Let C=0.01µF
T=1 x 10-3
R=T/1.1 x C
Therefore, R=8.2kΩ
 IC 555 TIMER: Mono-stable Mode :- Applications
The important applications of monostable multivibrator are (i) Frequency divider, (ii) Pulse
Width Modulation (PWM) and (iii) Ramp generation.
Frequency Divider:
A continuously triggered mono-stable circuit when triggered by a square wave generator can be
used as a frequency divider, if timing interval T of monostable multivibrator is designed to be
longer than the period of the triggering square wave input signal.

The mono-stable multivibrator will be triggered

by the first -ve going edge of the square wave
input but the output will remain HIGH for next
–ve going edge of the input square wave. The
mono-shot will however be triggered on the third
–ve going input, depending on the choice of the
time delay. In this way the output can be made
integral fractions of the frequency of the input
triggering square wave.
 IC 555 TIMER: Mono-stable Mode :- Applications
Pulse Width Modulation (PWM):
When applied with a modulating control input signal at pin5 can act as a PWM. By the
continuous trigger at pin2 generates a series of output pulses. The duration of the output pulses
are determined by the triggering of the upper comparator, which in turn depends on the
modulating signal input at pin5.
 IC 555 TIMER: Astable Mode Operation
Re-triggering is basically achieved by connecting the trigger input (pin 2) and the threshold input (pin 6)
together, thereby allowing the device to act as an astable oscillator.
During each cycle, capacitor C charges up through both timing resistors, RA and RB but discharges itself only
through resistor,  RB  as the other side of  RB  is connected to the discharge terminal, pin 7.
During charge, the capacitor charges towards Vcc with
a time constant (RA + RB)C. During this period, output
(pin3) is HIGH as control FF inputs makes R=0, S=1,
output becomes . When the capacitor voltage
equal to 2/3Vcc the upper comparator triggers the control
FF. This turns ON transistor Q1 and capacitor
starts discharging towards ground through RB with time
constant RB C.

During discharge, the capacitor voltage reaches 1/3Vcc,

the lower comparator triggered and this sets the FF
S=1 R=0, which turns OFF transistor Q1.
Thus, the capacitor C periodically charged and discharged
between 2/3Vcc and 1/3Vcc respectively.
IC 555 TIMER: Astable Mode Operation
 The individual times required to complete one charge and
discharge cycle of the output.
The capacitor voltage is given as: Vc = Vcc (1 -
The time t1 taken by the capacitor to charge from 0 to (2/3) Vcc,
then (2/3)Vcc = Vcc (1 -
Therefore, t1 = 1.09 RC
The time t2 taken by the capacitor to charge from 0 to (1/3)Vcc,
then (1/3)Vcc = Vcc (1 -
Therefore, t2 = 0.405 RC
The time taken by the capacitor to charge from (1/3)Vcc to
(2/3)Vcc is given by,
tHIGH = t1 – t2 = 1.09RC – 0.405RC = 0.69RC
So, for the given circuit, tHIGH = 0.69(RA+RB)C
The output is LOW while the capacitor discharges from (2/3)Vcc
to (1/3)Vcc and the voltage across the capacitor is given by
(1/3)Vcc = (2/3)Vcc (
solving, we get t = 0.69RC.
So, given circuit, tLOW = 0.69RBC
Time period, T = tHIGH + tLOW = 0.69 (RA+2RB)C
 IC 555 TIMER: Astable Mode Operation
Example problem:
From circuit, RA = 6.8K, RB = 3.3K and C = 0.1MF,
calculate i) tHIGH ii) tLOW iii) Free running frequency and iv) Duty cycle.

Solution:
From circuit, RA = 6.8K, RB = 3.3K and C = 0.1µF,
calculate
tHIGH = 0.69(RA+RB)C =

tLOW = 0.69RBC =

T = 0.69 (RA+2RB)C =

Free running frequency, F = 1/T =

Duty cycle,
D = tHIGH / (tLOW + tHIGH ) x 100 =
 IC 555 TIMER: Astable Mode - Applications
The importance applications of the astable multivibrator are i) Frequency Shift Keying (FSK)
generator, ii) Pulse Position Modulator (PPM) and iii) Schmitt Trigger.
 FSK Generator:
In digital data communication, binary code is transmitted by
shifting a carrier frequency between two preset frequencies.
This type of transmission is called frequency shift keying
(FSK) technique.
When input is HIGH, transistor Q1 is OFF and timer
works as normal astable mode operation. The frequency
of the output waveform written as
f1 =
When input is LOW, Q1 goes ON and connects the
resistance RC across RA. Now the output frequency is given
by f2 =
Resistance RC can be adjusted to get the output frequency
1270Hz.
 IC 555 TIMER: Astable Mode - Applications
Pulse Position Modulator (PPM):
The PPM can be constructed by applying modulating signal to pin-5 of timer connected for astable
operation. The output position varies with the modulating signal, since the threshold voltage and hence
the time delay is varied.
 IC 555 TIMER: Astable Mode - Applications
Schmitt Trigger:
In Schmitt trigger circuit using 555 timer, two internal comparators are tied together and externally biased at
Vcc/2 through R1 and R2. Since the upper comparator will trip at (2/3)Vcc and lower comparator at (1/3)Vcc, the
bias provided by R1 and R2 is centered within these two thresholds. Thus a sine wave of sufficient amplitude
(>Vcc/6 = 2/3Vcc-Vcc/2) to exceed the reference levels causes the internal flip-flop to alternatively set and reset,
providing a square wave output.
 IC 566 Voltage Controlled Oscillator (VCO)
Voltage controlled oscillator is a type of oscillator where the frequency of the output oscillations can be varied by
varying the amplitude of an input voltage signal. Voltage controlled oscillators are commonly used in Frequency
Modulator (FM), Pulse Modulator (PM) and Phase Locked Loop (PLL).
Features:
 The maximum operating voltage is 10V to 24V
 High temperature stability
 Operating temperature is 0˚C to 70˚C
 The frequency can be controlled by means of current, voltage, resistor or capacitor
 Power dissipation is 300mV
 Excellent power supply rejection
Applications:
 Function / Signal generator (square or triangular)
 FM modulation
 Frequency shift keying i.e., FSK demodulator
 Converting low frequency signals such as EEG
(ElectroEncephaloGram) and EKG
(ElectroCardioGram) into audio frequency range
signals.
 IC 566 Voltage Controlled Oscillator (VCO)
The timing capacitor CT is linearly charged or discharged by a constant current source/sink. The amount of
current can be controlled by changing the control voltage VC applied at the modulating input (pin 5) or by changing
the timing resistor RT external to the IC chip. The voltage at pin 6 is held at the same voltage as pin 5. Thus, if the
modulating voltage at pin 5 is increased, the voltage at pin 6 also increases, resulting in less voltage across RT and
thereby decreasing the charging current.
The voltage across the capacitor CT is applied to the inverting input terminal of Schmitt trigger via buffer amplifier.
The output voltage swing of the Schmitt trigger is designed to V CC and 0.5VCC.
If Ra = Rb in the positive feedback
loop, the voltage at the non-inverting
input terminal of Schmitt trigger
swings from 0.5VCC to 0.25VCC.
When the voltage on the capacitor CT
exceeds 0.5VCC during charging, the
output of the Schmitt trigger goes
LOW (0.5VCC). The capacitor now
discharges and when it is at 0.25VCC,
the output of Schmitt trigger goes
HIGH (VCC).
 IC 566 Voltage Controlled Oscillator (VCO)
Since the source and sink currents are equal, capacitor charges and
discharges for the same amount of time. This gives a triangular voltage
waveform across CT which is also available at pin 4. The square wave
output of the Schmitt trigger is inverted by buffer amplifier and is available
at pin 3.
The output frequency of the VCO can be changed either by (i) RT, (ii) CT or
(iii) the voltage VC at the modulating input terminal pin 5. The voltage VC
can be varied by connecting a R1R2 circuit as shown in the figure below.

The components RT and CT are

first selected so that VCO
output frequency lies in the
centre of the operating
frequency range. Now the
modulating input voltage is
usually varied from 0.75VCC to
VCC which can produce a
frequency variation of about
10 to 1.
 IC 566 Voltage Controlled Oscillator (VCO)
Calculation of the output frequency of the VCO:
The total voltage on the capacitor changes from In eqn (2) sub VC = 7/8VCC,
0.25Vcc to 0.5Vcc. Thus Δv = 0.25Vcc. The capacitor 2(Vcc  (7 / 8)Vcc ) 1 0.25
fo  . . ..................(3)
charges with a constant current source. RT CT Vcc 4 RT CT RT CT
v i
 Voltage to Frequency conversion factor (KV):
t CT
It is determined by KV =∆fO/∆VC , where ∆VC is the
0.25Vcc i
 change in modulating voltage required to produce a
t CT
corresponding shift ∆fO in frequency. Assume the centre
0.25Vcc CT
t  ....................(1) frequency is fO and the new frequency is f1, then
i 2(VCC  VC  VC ) 2(VCC  VC ) 2VC
The time period T of the triangular waveform = 2Δt. f o  f1  f 0   
RT CTVCC RT CTVCC RT CTVCC
The frequency of the oscillator fo is,
f o 2
1 1 i  KV 
fo    VC RT CTVCC
T 2t 0.5Vcc CT
fOVCC
V  vc Putting the values of VC 
i  cc VC is voltage at pin5 8 fO
RT RTCT from eqn (3)
2(Vcc  vc ) fO 8 fO
Therofore , f o  ....................(2) KV  
RT CT Vcc VC VCC
 IC 565 Phase Locked Loop (PLL)
The PLL IC 565 is usable over the frequency range 0.1 Hz to 500 kHz. It has highly stable centre frequency and is
able to achieve a very linear FM detection. The output of VCO is capable of producing TTL compatible square
wave. The dual supply is in the range of ±6V to ±12V. The IC can also be operated from single supply in the range
12V to 24V. The following figure shows the pin-out and the internal block schematic of PLL IC NE 565.
 IC 565 Phase Locked Loop (PLL) Operation
The basic block schematic of the PLL system consists of i) Phase detector/comparator, ii) A low pass filter, iii) An
error amplifier and iv) A Voltage Controlled Oscillator (VCO).
The VCO is a free running multivibrator and operates at a set frequency fO called free running frequency. This
frequency is deter­mined by an external timing capacitor CT and an external resistor RT. It can also be shifted to
either side by applying a dc control voltage VC to an appropriate terminal of the IC. The frequency deviation is
directly proportional to the dc control voltage and hence it is called a "Voltage Controlled Oscillator".
If an input signal VS of frequency fS is applied to the PLL, the phase detector compares the phase and frequency
of the incoming signal to that of the output VO of the VCO. If the two signals differ in frequency and/or phase, an
error voltage Ve is generated. The phase detector is basically a multiplier and produces the sum (fS+fO) and
difference (f S - f O ) components at its output.
The high frequency component (fS+fO) is removed by
the low pass filter and the difference frequency
component is amplified and then applied as control voltage
VC to VCO. The signal VC shifts the VCO frequency in a
direction to reduce the frequency difference between fS and
f O.
Once this action starts, we say that the signal is in the
capture range. The VCO continues to change frequency
till its output frequency is exactly the same as the input
 IC 565 Phase Locked Loop (PLL) Operation
Once locked, the output frequency fO of VCO is identical to fS except for a finite phase difference. This phase
difference generates a corrective control voltage VC to shift the VCO frequency from fO to fS and thereby maintain
the lock. Once locked, PLL tracks the frequency changes of the input signal. Thus, a PLL goes through three stages
(i) free running, (ii) capture and (iii) locked or tracking.

As capture starts, a small sine wave appears.

This is due to the difference frequency between the VCO and the input signal. The dc component of the beat drives
the VCO towards the lock. Each successive cycle causes the VCO frequency to move closer to the input signal
frequency.
The difference in frequency becomes smaller and a large dc component is passed by the filter, shifting the VCO
frequency further. The process continues until the VCO locks on to the signal and the difference frequency is dc.
The low pass filter controls the capture range. If VCO
frequency is far away, the beat frequency will be too high
to pass through the filter and the PLL will not respond.
We say that the signal is out of the capture band.
However, once locked, the filter no longer restricts the
PLL. The VCO can track the signal well beyond the
capture band. Thus tracking range is always larger than
the capture range.
IC 565 Phase Locked Loop (PLL) Operation
 IC 565 Phase Locked Loop (PLL)
 Derivation of Lock in Range:
When PLL is in lock, it can trap frequency changes in the incoming signal. The range of frequencies over which
the PLL can maintain lock with the incoming signal is called as lock range.
8 f out
The lock range, fL= ± Hz.
V

 Derivation of Capture Range:

The range of frequencies over which the PLL can acquire lock with the input signal is called as capture range.

Refer book
Complete derivation
 IC 565 Phase Locked Loop (PLL) Applications
Important applications are i) Frequency Multiplier, ii) Frequency Synthesizer,
iii) FM Demodulator and iv) FSK Demodulator.
Frequency Multiplier:
The block diagram for a frequency multiplier using PLL 565. Here, a divide by N network is
inserted between the VCO output (pin 4) and the phase comparator input (pin 5).
Since the output of the divider is locked to the input frequency fS, the VCO is actually running at
a multiple of the input frequency. Therefore, in the locked state, the VCO output frequency fO is
given by, fO = NfS
By selecting proper divider by N
network, we can obtain desired
multiplication.
For example, to obtain output
frequency fO = 6fS, a divide by N
should be equal to 6.
 IC 565 Phase Locked Loop (PLL) Applications
Frequency Synthesizer / Translation:
The PLL can be used as the basis for frequency synthesizer that can produce a precise series of frequencies that are
derived from a stable crystal controlled oscillator.
It is similar to frequency multiplier circuit except that divided by M network is added at the input of phase lock
loop. The frequency of the crystal-controlled oscillator is divided by an integer factor M by divider network to
produce a frequency fosc /M, where fosc is the frequency of the crystal controlled oscillator.

The VCO frequency fVCO is similarly divided by

factor N by divider network to give frequency equal
to fVCO /N. When the PLL is locked in on the
divided-down oscillator frequency, we will have
fosc /M = fVCO /N, so that fVCO = (N/M) fosc.
By adjusting divider counts to desired values large
number of frequencies can be produced, all derived
from the crystal controlled oscillator.
 IC 565 Phase Locked Loop (PLL) Applications
FM Demodulator:
The PLL can be very easily used as an FM detector or demodulator. When the PLL is locked in on the FM signal,
the VCO frequency follows the instantaneous frequency of the FM signal, and the error voltage or VCO control
voltage is proportional to the deviation of the input frequency from the centre frequency.
Therefore, the a-c component of error voltage or control voltage of VCO will represent a true replica of the
modulating voltage that is applied to the FM carrier at the transmitter. The faithful reproduction of modulating
voltage depends on the linearity between the instantaneous frequency deviation and the control voltage of VCO.

It is also important to note that the FM frequency

deviation and the modulating frequency should
remain in the locking range of PLL to get the
faithful replica of the modulating signal.
If the product of the modulation frequency fm and
the frequency deviation exceeds the (∆fC)2, the
VCO will not be able to follow the instantaneous
frequency variations of the FM signal.
 IC 565 Phase Locked Loop (PLL) Applications
FSK Demodulator:
In digital data communication, binary data is transmitted by means of a carrier frequency. It uses two different
carrier frequencies for logic 1 and logic 0 states of binary data signal. This type of data transmission is called
frequency shift keying (FSK). In this data transmission, on the receiving end, two carrier frequencies are converted
into 1 and 0 to get the original binary data. This process is called as FSK demodulation. A PLL can be used as a
FSK demodulator. It is similar to the PLL demodulator for analog FM signals except for the addition of a
comparator to produce a reconstructed digital output signal. Let us consider that there are two frequencies, one
frequency (f1) is represented as "0" and other frequency (f2) is represented as “1".
If the PLL remain is locked into the FSK signal at both f 1 and f2, the VCO control
voltage which is also supplied to the comparator will be given as V C1= (f1- fO ) / KV and
VC2 = (f 2 - fO) / KV respectively.
Where KV is the voltage to frequency transfer
coefficient of the VCO. The difference between the
two control voltage levels will be ∆VC = (f2 – f1) /
KV. The reference voltage for the comparator is
derived from the additional low pass filter and it is
adjusted midway between VC1 and VC2 . Therefore,
for VC1 and VC2, comparator gives output '0' and '1',
respectively.
 AD633 Analog Multiplier
AD633 is a four quadrant, analog multiplier in either an 8-PDIP (Plastic Dual-in-Line Package) or 8-SOIC
(Standard Small Outline Package) package. The device is laser calibrated which makes it reliable and stable with a
guaranteed accuracy of 2% of full scale. There is a high 10 MΩ input resistance that makes the signal source
loading negligible. The AD633 is ideal for applications that need high reliability and stable performance such as
modulation / demodulation and voltage controller amplification.

Features
• Function: analog multiplier
• Number of stages: four quadrant
• Voltage supply: ±8 V to ±18 V
• Temperature operating range:
• AD633J: 0°C to +70°C
• AD633A: -40°C to +85°C
• Package / case:  8-PDIP, 8-SOIC

Applications
• Voltage controlled amplifiers / attenuators
• Multiplication, division, squaring
• Modulation / demodulation, phase detection
 AD633 Analog Multiplier
The AD633 is a low cost multiplier comprising a translinear core, a buried Zener reference, and a unity-gain
connected output amplifier with an accessible summing node. The differential X and Y inputs are converted to
differential currents by voltage-to-current converters. The product of these currents is generated by the multiplying
core. A buried Zener reference provides an overall scale factor of 10 V. The sum of (X × Y)/10 + Z is then applied
to the output amplifier. The amplifier summing Node Z allows the user to add two or more multiplier outputs,
convert the output voltage to a current, and configure various analog computational functions.
The functional block diagram shows the overall transfer function is
 AD633 Analog Multiplier
Application : MULTIPLIER
The X and Y inputs normally have their negative nodes
grounded, but they are fully differential, and in many
applications, the grounded inputs may be reversed (to
facilitate interfacing with signals of a particular polarity
while achieving some desired output polarity), or both
may be driven.
Application : SQUARING
The squaring of an input signal, E, is achieved simply
by connecting the X and Y inputs in parallel to
produce an output of E2/10 V. The input can have
either polarity, but the output is positive. However, the
output polarity can be reversed by interchanging the X
or Y inputs. The Z input can be used to add a further
signal to the output.
 AD633 Analog Multiplier
Application : FREQUENCY DOUBLING
When the input is a sine wave E sin ωt, this squarer behaves as a frequency doubler, because

Equation 2 shows a dc term at the output that varies strongly with the amplitude of the input, E. This can be avoided using the
connections shown in Figure 14, where an RC network is used to generate two signals whose product has no dc term. It uses the
identity

At ωo = 1/CR, the X input leads the input signal by 45° (and is attenuated
by √2), and the Y input lags the X input by 45° (and is also attenuated by
√2). Because the X and Y inputs are 90° out of phase, the response of the
circuit is (satisfying Equation 3)

which has no dc component. Resistor R1 and Resistor R2 are included to

restore the output amplitude to 10 V for an input amplitude of 10 V.
The amplitude of the output is only a weak function of frequency; the
output amplitude is 0.5% too low at ω = 0.9 ω0 and ω0 = 1.1 ω0.