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NE555 pinouts
Here threshold and trigger are the inputs of the 555 timer IC
So, whenever the threshold voltage becomes greater than
2/3Vcc the output of the 1st comparator is HIGH or else LOW.
Similarly, in 2nd comparator if trigger voltage becomes less
than 1/3Vcc the output will become HIGH or else LOW.
With control pin we can control the timing, reset pin if LOW then it
resets the flip-flop.
Truth table of RS Flip-Flop:
To change the input at threshold pin external capacitor and resistor are
connected b/w threshold and discharge pin.
Discharge pin helps capacitor in discharging whenever the output is
LOW.
When the output is 1 the gate of the transistor will be at high voltage.
Here the transistor acts as a switch.
It is in ON mode when the voltage at gate terminal is HIGH and vice-versa.
Part 2
Design of a free running multi-vibrator for frequency and duty cycle
specifications:
Calculations:
The capacitor starts charging though the resistors R1(RA) and R2(RB).
Now capacitor starts charging and discharging between 1/3Vcc and
2/3Vcc.
Now let us assume t1 and t2 be time taken by capacitor for charging and
discharging between 1 /3Vcc and 2/ 3Vcc respectively.
So, for obtaining the duty cycle using standard resistor and capacitor
values we can use:
R1 =620 ohm, R2 = 82ohm, C = 0.18uf
Circuit diagram:
Circuit simulation:
Part 3
Design a monostable multi-vibrator with specifications:
It has only one stable state. i.e., it is usually in stable state but whenever
a trigger state is applied then momentarily output of the monostable
vibrator goes to the unstable state.
After certain time it comes back to the stable state.
Positive edge-triggered, 400us pulse width
For understanding the circuit, we draw the internal block diagram of
NE555 timer IC
Calculations:
While charging when the voltage at C1 just crosses the 2/3 Vcc the
output of the 1st comparator becomes logic 1.
And the output of the flip-flop will become 0. And output of the 555
timers will become 0. Transistor gets switched ON.
And voltage across the capacitor gets discharged instantly. And when
that happens both outputs of the comparator will become logic 0.
Let T be the time the 555 timer is in unstable state.
Circuit diagram:
Circuit simulation