Lab-6 ECN-252

Aman Sinha
19116007
Batch-O5

Part-1
My Set-ECE-4th
A=0010
B=0101
My Schematics:
Full Adder: Q2.asc
Full Adder Symbol: Q2.asy
Half Adder: Q1.asc
Half Adder Symbol: Q1.asy
Signed Multiplier: Signed Multiplier.asc
My Diagram:
Output:

Result: Simulated and Graphical are proved.

Part-2:
My Schematics: 4 bit _Comparator .asc

Theoretical Examples to show:

A B A>B A<B A=B
1101 1101 0 0 1
1011 1101 0 1 0
0111 1100 0 1 0
Diagram:

Graph:

Result: Both Theoretical and Graphical are proved.