4816 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO.
12, DECEMBER 2020
A Novel Area-Power Efficient Design for
Approximated Small-Point FFT Architecture
Xueyu Han, Jiajia Chen , Boyu Qin, and Susanto Rahardja , Fellow, IEEE
Abstract—Fast Fourier transform (FFT) is an essential algo-
rithm in digital signal processing and advanced mobile communi-
cations. With the continuous development of modern technology,
the area-power efficient hardware implementation of FFT has
attracted a lot of attention. In this article, a novel design for FFT
implementation is proposed. The number of resource-expensive
multiplications in our design is decreased by a twiddle factor
merging technique that reduces the hardware area. Subsequently,
a common subexpression sharing scheme is applied to reuse the
hardware resources to further save the hardware area. In addi-
tion, a magnitude-response aware approximation algorithm is
proposed for applications where the transformation accuracy can
be compromised a little bit for lesser hardware area and power
dissipation. Logic synthesis shows that the proposed 16-point FFT
architecture can save hardware area and power dissipation on
application-specific integrated circuit (ASIC) by up to 65.7% and
53.1% compared with recently published designs. Similarly, the
proposed 32-point FFT architecture achieves up to 58.8% reduc-
tion on hardware area and 60.0% reduction on power dissipation
on ASIC.
Index Terms—Approximated fast Fourier transform (FFT),
common subexpression sharing (CSSsharing), twiddle factor
merging (TFMerging).
I. I NTRODUCTION
AST Fourier transform (FFT) is a widely used algo-
F rithm in digital signal processing [1]–[3] and wireless
communication systems [4]–[8]. In long term evolution (LTE)
and its high-speed versions LTE-Advanced/LTE-Advanced
Pro [7], FFTs with different transformation sizes are desired.
Moreover, FFT generates the required radio frequency (RF)
beams for multibeam beamforming which is one of the
significant techniques in the fifth generation (5G) wireless
communication [8]. Nowadays, as most of mobile communi-
cations are designed to be implemented on portable devices,
the embedded FFT processor is required to have low hardware
area and power dissipation. It is also vital that the computa-
tion speed of the FFT processor is high enough to support
Manuscript received October 16, 2019; revised January 8, 2020; accepted
February 29, 2020. Date of publication March 6, 2020; date of cur-
rent version November 20, 2020. This work was supported by the
Nanjing University of Aeronautics and Astronautics, Nanjing, China, under
Grant 56YAH18043. This article was recommended by Associate Editor
R. Drechsler. (Corresponding authors: Jiajia Chen; Susanto Rahardja.)
Xueyu Han and Susanto Rahardja are with the School of Marine Science
and Technology, Northwestern Polytechnical University, Xi’an 710072, China
(e-mail: susantorahardja@ieee.org).
Jiajia Chen and Boyu Qin are with the College of Electronic and
Information Engineering, Nanjing University of Aeronautics and Astronautics,
Nanjing 211106, China (e-mail: jiajia_chen@nuaa.edu.cn).
Digital Object Identifier 10.1109/TCAD.2020.2978839
0278-0070 
c 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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high data rate requirement. Therefore, an area-power efficient
and high speed FFT architecture has been actively researched
in recent years [5], [9]–[11].
FFT can be implemented both in high-level software lan-
guages and on hardware. The software solution has the
advantage in flexibility but the solution is usually accompanied
with a bulky and complex hardware system which is unfriendly
to small-sized and battery-based devices [12], [13]. Motivated
by the challenging requirements in hardware area and power
budget, many hardware solutions for FFT implementation
have been developed for mobile and smart devices [14], [15].
As technology matures, application-specific integrated cir-
cuit (ASIC) has become more cost effective for some generic
classes of problems in digital signal processing such as the
FFT [16]. ASIC solution provides the ability to manage power
and exploit the robustness after processing in digital domain.
Existing hardware solutions for FFT implementation can
be mainly divided into reconfigurable and fixed architectures.
Reconfigurable architecture [17]–[19] is generally developed
for variable-length FFTs. Mixed-radix algorithms are com-
mon solutions to implementing a variety of transformation
lengths. Fixed FFTs can be further categorized into pipelined
and parallel architectures. The most classical approaches for
pipelined FFTs [20]–[24] are multipath delay commutator and
single-path delay feedback. The basic structure of these two
approaches consists of a processing element (PE) for data com-
putation and the required memory for data storage. Parallel
architectures on the other hand [25]–[29] can be constructed
by decomposing the FFT algorithm into several partitions and
using a combination of PEs to compute these partitions in
parallel. Different FFT architectures have different advantages
and disadvantages in terms of hardware complexity and com-
putation speed. Pipelined FFTs have simpler architectures but
larger latency as data are processed sequentially. In addition,
complex controller is required in pipelined architectures. On
the contrary, parallel architectures can deal with N inputs
simultaneously and have the advantage of easy control but
at the expense of more hardware resources.
It is challenging to implement FFT on hardware to achieve
high accuracy and low hardware cost. However, the accuracy
can be relaxed in some applications to achieve a substantially
reduction on hardware cost and power dissipation. To do this,
approximation [30] has become imperative for the tradeoff.
Recent published works in [24], [27], and [28] improved exist-
ing FFT architectures based on approximate computing. An
inexact pipelined FFT accelerator was proposed in [24]. A sta-
tistical learning technique based on normalized least mean
HAN et al.: NOVEL AREA-POWER EFFICIENT DESIGN FOR APPROXIMATED SMALL-POINT FFT ARCHITECTURE 4817

square algorithm is used to train the inexact FFTs, where

separate training and test sets are requisite. Han et al. [27]
proposed an efficient parallel FFT architecture where the
infinite-precision coefficients are approximated by cutting off
their insignificant bits. However, it may not be the most hard-
ware efficient solution when the error introduced is still less
than the transformation error allowed. Another approximated
parallel FFT architecture was recently proposed in [28] where
the design was simplified to be multiplierless. Although a low
area-power design is achieved in [28], the transformation error
caused by its heavy approximation is relatively high.
In this article, a novel design for area-power efficient FFT
architecture is proposed as a solution to address the above
challenges. First, a new twiddle factor merging (TFMerging)
technique is proposed where the low-cost unified adder–
subtractor (UAS) operator [31] is utilized for the merged
expressions. Second, duplicated multiplications in the merged
expressions are implemented by one sharable structure and
a dedicated common subexpression (CS) sharing algorithm is
proposed to maximize the sharing. Third, we propose a novel
Fig. 1. 16-point DIT-FFT algorithm.
approximation approach for the FFT coefficients under dif-
ferent requirements of transformation error. The approach
approximates the FFT coefficients, which takes care of both
bit sensitivity to the transformation error and the reduction in
hardware cost. The proposed new approach has two advan-
tages. The first one is the ability to generate more efficient
approximation solution by utilizing the margin between the Fig. 2. Butterfly block.
maximum error allowed and the error caused by the direct
truncation. The second one is the ability to achieve more
subexpression sharing by generating more approximated FFT FFT was proposed. The simplest and most commonly used
coefficient candidates. They contribute to the design of effi- is Cooley–Tukey radix-2 decimation-in-time (DIT) FFT [32].
cient FFT without the need of extra training and test sets. In Radix-2 DIT-FFT decomposes an N-point DFT into smaller
addition, the approximation approach can be applied with any DFTs by dividing the even- and odd-indexed input samples
given transformation error constraints to provide a solution into two parts as
with good quality. The proposed FFT architectures are com-
pared with the state-of-the-arts and the logic synthesis results X(k) = X1 (k) + WNk X2 (k) (2)
show that our designs successfully reduce the hardware area N/2−1
and power dissipation. where X1 (k) = n=0 x(2n)WN/2 and X2 (k)
nk =
N/2−1
n=0 x(2n + 1)WN/2 are two N/2-point DFTs. By recur-
nk
This article is organized as follows. Section II intro-
duces some prerequisite preliminaries for FFT algorithm and sively applying (2), an N-point DFT can be decomposed into
presents the problem formulation. Section III presents the log2 N stages as shown in Fig. 1 and each stage contains
proposed algorithm for FFT architecture design. The logic syn- a total of N/2 2-point DFTs. The butterfly block depicted in
thesis results of our architectures and competing designs are Fig. 2 is utilized to implement these 2-point DFTs based on
given in Section IV. Finally, a conclusion is given in Section V. the symmetric property of the twiddle factors
nk+ N2
II. P RELIMINARIES AND P ROBLEM F ORMULATION WN = −WNnk . (3)
A. DFT and FFT Preliminaries In each butterfly block, one CM, one CA, and one complex
The 1-D DFT of an input signal sequence x(n) is given by subtraction are required. Therefore, the computational com-
plexity of an N-point FFT decreases remarkably from O(N 2 )

N−1
X(k) = x(n)WNnk , n = 0, 1, . . . , N − 1 (1) to O(Nlog2 N) compared with the direct DFT.
n=0
where X(k) is the frequency domain representation of x(n) B. Problem Formulation
with k = 0, 1, . . . , N − 1. WNnk = exp(−j2π nk/N) is the According to (1) and (2), CM and CA are the two arith-
twiddle factor. Since N 2 complex multiplications (CMs) and metic operations required in DFT/FFT. The numbers of CMs
N(N − 1) complex additions (CAs) are required in (1), the and CAs needed in N-point DFT and DIT-FFT architectures
computational complexity of an N-point DFT grows quickly are given in the second and third columns of Table I. In
with increasing N. In order to compute DFT more efficiently, hardware implementation, CMs and CAs are converted to

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4818 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 12, DECEMBER 2020

TABLE I
R EQUIRED R ESOURCES IN N-P OINT DFT AND
DIT-FFT A RCHITECTURES

operations on their real and imaginary parts. The numbers of

real multiplications (RMs) and real additions (RAs) required
in N-point DFT and DIT-FFT architectures are computed and
given in the fourth and fifth columns, respectively, in Table I.
In many previous works, RMs are implemented by shift
and add network to achieve a low hardware cost [33], [34].
Knowing that the shifts can be implemented by direct hard-
wiring, addition is the core operation that requires look-up
table (LUT) count in FPGA. Therefore, the total number
of RAs can be used to estimate the required hardware
resources. We assume all RAs are implemented with ripple
carry adders (RCAs) whose complexity is proportional to its
wordlength [35], [36] to have a more accurate estimation. By
doing so, the number of full adders (FAs) in the carry chain of
RCA can be used as the cost of each particular RA. For imple-
mentation on ASIC, although there are many different types
of FA cell, the number of FAs needed gives valid information
about the hardware complexity. Therefore, the total FA count
is used as an estimation for the hardware cost of the FFT
architecture, which is denoted as final_cost.
Besides the hardware cost, transformation accuracy is
another major consideration. Given an input signal sequence
x = [x(0), x(1), . . . , x(N − 1)], the exact FFT outputs X =
[X(0), X(1), . . . , X(N − 1)] are computed by (2). To imple-
ment FFT on hardware, infinite-precision twiddle factors
in (2) have to be approximated to finite-precision. When
approximated twiddle factors are used in (2), the outputs cor-
responding to the given input x can be denoted as Xappro =
[Xappro (0), Xappro (1), . . . , Xappro (N − 1)]. The corresponding
Fig. 3. Multiplication of NTFs across stages in an N-point radix-2 DIT-FFT
architecture.
III. P ROPOSED M ETHOD
A. Twiddle Factor Merging
In an FFT architecture, multiplication is the most resource-
expensive arithmetic operation. To minimize the FFT hard-
ware cost with a limited transformation error, we propose
a TFMerging method to reduce the number of multiplications.
Twiddle factor multiplications (TFMs) in FFT architecture can
be divided into two categories: 1) trivial TFM and 2) nontrivial
TFM. Trivial TFMs refer to the multiplications with twiddle
factors which can be implemented by direct hardwiring, such
as multiplying the input with −1, 1, or −j. Nontrivial TFMs
are multiplications which need to be implemented by shift
and add network. Only those nontrivial TFMs are actually
resource-expensive multiplications of which the number needs
to be reduced. Based on the conventional radix-2 DIT-FFT
architecture, we merge two nontrivial twiddle factors (NTFs)
s s
WNp and WNp+1 , in two adjacent stages p and p + 1, into a new
NTF, as shown in Fig. 3. r, t, u, and v are four intermediate
results in the FFT architecture. R is computed as
s s
 s

R = r + WNp t + WNp+1 u + WNp v
s s s s
= r + WNp t + WNp+1 u + WNp+1 WNp v. (6)
Using Euler’s rule to re-express the twiddle factor, we have

2π nk 2π nk 2π nk
error E caused by the approximation is evaluated based on WN = exp −j
nk
= cos − j sin (7)
N N N
the root-mean-square error (RMSE) between Xappro and X as
follows: where cos(2π nk/N) and sin(2π nk/N) are twiddle factor
s s
 coefficients (TFCs). The term WNp+1 WNp in (6) can then be
N−1  2 represented by a single NTF
k=0 X(k) − Xappro (k)    
E= . (4)
N sp sp+1 2π sp + sp+1 2π sp + sp+1
WN WN = cos − j sin
With the estimated hardware cost final_cost and the com- N N
sp +s
puted error E, the design problem can then be formulated = WN p+1 . (8)
as a minimization of final_cost provided that E is less than
Therefore, each TFM in (6) is decomposed into two
required
multiplications with nontrivial TFCs. Similar to nontrivial
TFMs, nontrivial TFCs are coefficients which need to be
Minimize{final_cost}, s.t. E ≤ δ (5)
implemented by shift and adder network. When sp+1 =
where δ is the maximum RMSE allowed. To solve (5), N/4 − (sp + sp+1 ), (6) is rewritten as
we propose an algorithm to perform TFMerging which

2π sp 2π sp+1 2π sp+1
reduces the number of multiplications in FFT architec- R = r + cos t + cos u + sin v
N N N
ture and increases hardware resource sharing to reduce

2π sp 2π sp+1 2π sp+1
final_cost. Moreover, a magnitude-response aware approxima- − j sin t + sin u + cos v . (9)
tion approach is proposed to further reduce final_cost while E N N N
is monitored to be no more than δ. The details of the algorithm Benefiting from the distributive operation of multiplication
are presented in the next section. in (6) and the TFMerging in (8), the computation of the FFT

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HAN et al.: NOVEL AREA-POWER EFFICIENT DESIGN FOR APPROXIMATED SMALL-POINT FFT ARCHITECTURE
output is finally re-expressed by the sum of terms where the
input is multiplied with nontrivial TFCs like (9). In such case, it
is highly possible that these addition terms in (9) can be shared
and the number of multiplications with nontrivial TFCs is
reduced correspondingly compared to the conventional radix-2
DIT-FFT architecture. For example, in stage 3 and 4 of Fig. 1,
the data path in red for computing X(1) corresponds to the
data path for computing R which is also marked in red in Fig. 3.
s cost[i] = FA_count(CS_Selected);
The parameters in Fig. 3 are specified as p = 3, WNp = W16 2 ,
sp+1
and WN = W16 . r, t, u, and v are computed as
1 CS_Final = Min_cost(cost);
r = (x(0) − x(8)) − j(x(4) − x(12))
t = (x(2) − x(10)) − j(x(6) − x(14))
u = (x(1) − x(9)) − j(x(5) − x(13))
v = (x(3) − x(11)) − j(x(7) − x(15)).
By using (9), the computation of X(1) is finally expressed as
X(1) = (x(0) − x(8))
2π
+ sin [(x(2) − x(10)) − (x(6) − x(14))]
8 operator is lower than the total hardware areas of one
π
− sin [(x(5) − x(13)) − (x(3) − x(11))]
8 adders and subtractors in the first stage of the proposed FFT
π
+ cos [(x(1) − x(9)) − (x(7) − x(15))]
8
− j (x(4) − x(12))
2π
+ sin [(x(2) − x(10)) + (x(6) − x(14))]
8 ial TFCs are multiplied with the same input as shown in (9)
π
+ cos [(x(5) − x(13)) + (x(3) − x(11))]
8 
π
+ sin [(x(1) − x(9)) + (x(7) − x(15))] .
8
Similar to the computation of X(1), other outputs with
k = 0, 2, 3, . . . , 15 can be computed by using the proposed
TFMerging method. It is obvious that only six multiplications
with nontrivial TFCs are required for computing X(1) using
the proposed TFMerging method while eight multiplications
are required for the nontrivial TFCs (i.e., 3 complex nontrivial
TFMs) in Fig. 1. In addition, among the six multiplications for
computing X(1), two multiplications with sin(2π /8) are com-
mon to X(3), X(5), and X(7), and the rest four multiplications
with sin(π /8) and cos(π /8) are common to X(7). Structures
for implementing these common terms can be reused in the
FFT architecture and therefore a large amount of hardware
resources can be saved.
A basic structure for implementing the above common terms
is the addition/subtraction of two input signals. We define the
elementary addition/subtraction term as the computation of the
sum/difference of two input signals. Let us take the 16-point
FFT as an example. By recursively using (2), the 16-point FFT
is expressed as
   
X(k) = x(0) + W2k x(8) + W4k x(4) + W2k x(12)
   
+ W8k x(2) + W2k x(10) + W4k x(6) + W2k x(14)
   
+ W16
k
x(1) + W2k x(9) + W4k x(5) + W2k x(13)
   
+ W8k x(3) + W2k x(11) + W4k x(7) + W2k x(15)
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4819
Algorithm 1 Pseudo Code of the CSSharing Algorithm
Input: C
Output: CS_Final
CS_Share = Find_CS(C);
n = Size(CS_Share);
for i from 1 to n
CS_Selected = CS_Share[i];
updated_C = Remove(CS_Share[i], C);
CS_Additional = Find_CS(updated_C);
CS_Selected = Insert(CS_Selected, CS_ Additional);
end for
where k is the kth frequency component of the input x. When
k is even, i.e., W2k = 1, elementary addition terms in X(k)
are x(0) + x(8), x(1) + x(9), and so on. While k is odd
(i.e., W2k = −1), elementary subtraction terms include x(0) −
x(8), x(1) − x(9), and so on. Since the TFMerging technique
is applied to nontrivial TFCs, elementary addition/subtraction
terms remain unchanged after merging. Because the hard-
ware area for implementing a unified adder-subtractor [31]
adder and one subtractor, we utilize the UAS to replace the
architecture.
B. Common Subexpression Sharing
Hardware resources sharing exists when different nontriv-
as well. In such case, multiplications of the input with these
nontrivial TFCs can be implemented simultaneously using
a merged structure. In this article, we transform all TFCs into
canonical signed digit (CSD) representation [37]. An M-bit
CSD representation cM−1 cM−2 · · · c0 of a decimal number C
is derived by

M−1
C= ci 2i (10)
i=0
− −
where ci ∈{ 1 , 0, 1}, 1 denotes −1. In CSD representation,
a weight-two subexpression is defined as a string of 0s starting
and ending with nonzero digits. If one subexpression appears
more than once, it is called CS. Structures to implement CS
in different TFCs can be merged into a single structure where
the hardware resources are reused. Therefore, we propose
a CS sharing (CSSharing) algorithm which is summarized in
Algorithm 1. In an N-point FFT, we denote nontrivial TFCs
which are multiplied with the same input as a set C. The algo-
rithm starts with generating all CSs that can be shared and
stores them into a set CS_Share using the function Find_CS.
The function Size counts the total number of CSs in CS_Share.
For each CS, the function Remove is used to remove it from C
before Find_CS finds whether there is another CS that can be
further shared. With the selected CSs, the hardware cost of the
corresponding FFT architecture is evaluated by the function
FA_count. At last, the CSs resulting in a minimum hardware
cost are chosen by the function Min_cost and returned by the
algorithm.
4820 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 12, DECEMBER 2020
C. Magnitude-Response Aware Approximation to Twiddle
Factor Coefficients
All the infinite-precision TFCs are first transformed into M-
bit CSD representations by cutting off the insignificant bits of
TFCs. If the precision of TFCs is specified as K-bit (K ≤ M),
the truncation operation directly cuts off the (M − K) least
significant bits (LSBs). The error E∗ caused by the trunca-
tion operation can be evaluated by (4). When a maximum
allowed transformation error δ is specified for certain appli-
cation, there is usually a small margin between E∗ and δ. To
better utilize the margin, the truncated TFCs can be further
approximated by changing some digits in the TFCs to reduce
total FA count as long as the error is not bigger than δ. The
challenge is how to develop an efficient measure to minimize
the total FA count during the approximation while the error
is being kept below δ. To address this, a novel magnitude-
response aware approximation approach is proposed in this
section.
Two methods are considered in the proposed approxima-
tion approach. The first one is to change less significant
nonzero digits of nontrivial TFCs to zero so that the num-
ber of adders used for implementing the corresponding TFMs
is reduced. The second method is to change less significant
nonzero digits to their complement so that opportunities for
sharing CSs between nontrivial TFCs are created. These two
methods are simultaneously applied to different nonzero digits
of TFCs which have different impacts on the total FA count
and transformation error. The effect on the total FA count by
approximating the ith TFC at the jth nonzero digit counting
from the most significant bit is
FAbe − FAaf
ci,j =
FAbe
where FAbe and FAaf are the total FA count of the correspond-
ing FFT implementation before and after one approximation
method is adopted, respectively. By evaluating the transforma-
tion error using (4), the sensitivity of the jth nonzero digit in
the ith TFC with respect to transformation error is defined as
Eaf − Ebe
si,j =
Ebe
where Ebe and Eaf are the transformation errors before and
after the nonzero digit is changed, respectively. It is obvious
that changing a nonzero digit with a larger c and a smaller
s leads to more effective improvement. To evaluate these two
measures by using one metric, we define the gain of changing
the jth nonzero digit in the ith TFC on the total FA count and
transformation error as
ci,j
gi,j = . (13)
si,j
It is evident that changing the nonzero digit with a larger gain
contributes more efficient solution. Since the approximation
to one nonzero digit can be done by either changing to zero
or the complement, the respective gains can be denoted as
i,j i,j
gzero and gcomp which are evaluated by (13). With the above
denotations and definitions, two approximated algorithms are
presented in the next sections.
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Algorithm 2 Pseudo Code of the AFFT_ECS Algorithm
Input: C, existing_CS, δ
Output: C
E = error(C);
while (E ≤ δ) {
updated_C = Remove(existing_CS, C);
D = Count_nonzerodigit(updated_C);
n = Size(D);
for i from 1 to n
(gcomp [i], gzero [i]) = Gain(updated_C[i]);
end for
final_C = Max_Gain(gcomp , gzero , C); E = error(final_C);
if E ≤ δ
C = final_C;
else
C_set = Rank_Gain(gcomp , gzero , C);
for j from 2 to n
E = error(C_set[j]);
if E ≤ δ
C = C_set[j];
break;
end if
end for
end if }
1) Approximation Based on Existing Common
Subexpressions: If CSs exist in different nontrivial TFCs, we
propose an approximated FFT algorithm based on existing
CSs (named as AFFT_ECS) in this article. First of all, an
optimal CSSharing solution is generated by the proposed
algorithm. With the optimal CSs unchanged, the AFFT_ECS
algorithm iteratively changes some of the remaining nonzero
digits in TFCs which do not exist in any CS yet. In each
i,j i,j
iteration, gzero and gcomp are computed for all nonzero digits
by (13). The approximation is performed to the nonzero digit
i,j i,j
which has the biggest gzero /gcomple , provided that the corre-
(11)
sponding transformation error Eaf is less than the maximally
allowed error δ. If Eaf is bigger than δ due to the change of
the nonzero digit with the biggest gain, the algorithm seeks
the digit with the second biggest gain. The approximation is
performed when the error caused by changing the digit with
the second biggest gain is smaller than δ. Otherwise, the
algorithm continues to seek the digit with the third biggest
gain. The iteration continues while Eaf is always evaluated to
(12)
decide if any nonzero digit should be changed. If Eaf caused
by the changing of the digit with the least gain is still bigger
than δ, the algorithm stops and the approximation to this set
of TFCs completes. The main steps of the AFFT_ECS are
summarized in Algorithm 2.
The function error computes the error of the FFT imple-
mentation using the approximated TFC set C. The function
Count_nonzerodigit counts the total number of nonzero digits
of updated_C after removing existing CSs. For each nonzero
digit in updated_C, the function Gain measures its gain.
The nonzero digit that has the biggest gain is selected and
the TFC set is changed by the function Max_Gain accord-
ingly. The function Rank_Gain ranks the gains in descending
order. Finally, the algorithm returns the TFC set where all the
qualified nonzero digits are approximated.
2) Approximation by Creating New Common
Subexpressions: For small size FFTs, the number of nontrivial
TFCs is limited. As a consequence, it is likely that no CS
HAN et al.: NOVEL AREA-POWER EFFICIENT DESIGN FOR APPROXIMATED SMALL-POINT FFT ARCHITECTURE
Algorithm 3 Pseudo Code of the Error Compensation
Technique
Input: C
Output: C, Einitial
Einitial = error(C);
while (true) {
D = Count_nonzerodigit(C);
n = Size(D);
for i from 1 to n
compensated_C[i] = Change_to_zero(C[i]);
E[i] = error(compensated_C[i]);
end for
(min_E, new_C) = Min_error(E, compensated_C);
if min_E ≤ Einitial
Einitial = min_E;
C = new_C;
else
break;
end if }
can be shared by TFCs at the beginning. Moreover, even CSs
exist initially, fixing them as in AFFT_ECS algorithm may
hinder the TFCs from being further approximated to achieve
a better solution. For example, if the existing CS is located
at less significant bit position in a TFC, we can only change
the rest nonzero digits at more significant bit positions which
causes bigger transformation error. In the above-mentioned
two circumstances, we propose to approximate TFCs with the
freedom of creating new CS by changing a nonzero digit to its
complement. Eaf caused by this approximation operation may
exceed the maximally allowed error δ. However, this does not
mean that the approximation cannot be performed because
the unacceptable error can be compensated by changing
other nonzero digits in the same TFCs. To achieve this, we
propose an error compensation technique to adapt TFCs for
compensating the error before it is compared with δ. The
algorithm starts with computing the initial transformation
error using the TFCs in which one nonzero digit is changed
to create new CS. For each of the remaining nontrivial digits
not appearing in the new CS, it is changed to zero and the Eaf
is recomputed correspondingly. The minimum Eaf is selected
and compared with the initial transformation error after the
new CS is generated. If the error decreases, the algorithm
moves on to change the next nonzero digit to zero until the
transformation error stops decreasing. The main steps of
the algorithm are summarized in Algorithm 3. The function
Change_to_zero changes a nonzero digit which does not
exist in CS and returns a new TFC set compensated_C. The
function Min_error selects the minimum error and returns the
approximated TFC set which produces this error.
With the error compensation, we propose an approximated
FFT algorithm by creating new CS (named as AFFT_NCS).
If there are CSs existing in TFCs initially, they are ignored
and all nonzero digits are considered equally when creating
new CS. For each nonzero digit in TFCs, the algorithm first
changes it to its complement. All the remaining nonzero dig-
its in the same TFC take turns to be examined. Once a new
CS is found, it is fixed and the algorithm stops creating more.
This is because of the limited number of nonzero digits exist-
ing in TFC. When one CS is fixed, there is little chance
that the remaining nonzero digits can form other CSs. The
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4821
Algorithm 4 Pseudo Code of the AFFT_NCS Algorithm
Input: C, δ
Output: final_C
D = Count_nonzerodigit(C);
n = Size(D);
for i from 1 to n
sharable_CS = ∅;
appro_C = ∅;
new_C = Change_to_complement(C[i]);
CS_set = Generate_CS(new_C);
sharable_CS = Select_CS(CS_set);
while (sharable_CS = ∅) {
new_CS = Shortest_CS(sharable_CS);
Einitial = error(new_C);
if Einitial ≥ δ
(adapt_C, Einitial ) = Error_Compensate(new_CS, new_C);
end if
if Einitial = δ
appro_C[i] = AFFT_ ECS (adapt_C, new_CS, δ);
cost[i] = FA_count(new_CS);
end if }
end for
if appro_C = ∅
(min_cost, final_C) = Min_cost(cost);
else
final_C = C;
end if
error compensation is applied when the corresponding trans-
formation error exceeds. After that, the AFFT_ECS algorithm
proposed in Section III-C1 is performed thereafter for further
approximation.
This process is applied to every nonzero digit in the same
way as described above. The total FA count is computed for
each implementation and the approximated TFC set which
results in the lowest FA count is returned as the final solution
by the AFFT_NCS. The main steps of the algorithm are sum-
marized in Algorithm 4. The function Change_to_complement
changes a particular nonzero digit to its complement and
returns the approximated TFC set. All the CSs are saved
in CS_set using the function Generate_CS. The function
Select_CS selects all CSs that can be shared and saves them
into sharable_CS. For each element in sharable_CS, the func-
tion Shortest_CS chooses the CS of the shortest length as the
newly created CS for further TFC approximation.
With the proposed TFMerging technique, CSSharing and
magnitude-response aware approximation algorithm, a com-
plete approximated FFT architecture design algorithm is estab-
lished. First of all, the proposed TFMerging technique is
applied to an N-point FFT to generate nontrivial TFCs to
be approximated. Next, we apply the CSSharing method and
magnitude-response aware approximation algorithm to further
reduce the hardware complexity, with the maximally allowed
transformation error δ. With the nontrivial TFCs, we first
check if there are existing CSs that can be shared. If no,
the AFFT_NCS algorithm is applied to approximate TFCs.
Otherwise, the CSSharing method is applied to provide a solu-
tion for resource sharing before the AFFT_ECS algorithm is
applied to further approximate nontrivial TFCs. Though a good
solution can be returned by the AFFT_ECS algorithm, the
fixed CSs create a barrier for further approximation. Therefore,
the AFFT_NCS algorithm is also applied in this situation to
provide an alternative even though CS exists initially. Two
4822 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 12, DECEMBER 2020

Algorithm 5 Pseudo Code of the TFC_Approximation

Algorithm
Input: coefficients, δ
Output: final_C, final_cost
Initialize final_cost = 8;
C = TF_merging(coefficients);
minimum_wordlength = Initialize_TFC(C, δ);
for w = minimum_wordlength ++
truncated_C = Truncate(C, w);
existing_CS = Find_CS(truncated_C);
if existing_CS  = ∅
fixed_CS = CSSharing(truncated_C);
approximated_CE = AFFT_ECS(truncated_C, fixed_CS, δ);
approximated_CN = AFFT_NCS(truncated_C, δ);
cost_ECS = FA_count(approximated_CE );
cost_NCS = FA_count(approximated_CN );
if cost_ECS<cost_NCS
approximated_C = approximated_CE ;
else
approximated_C = approximated_CN ;
end if
else
approximated_C = AFFT_NCS(truncated_C, δ);
end if
cost = FA_count(approximated_C);
if cost > final_cost
break;
else
final_cost = cost;
final_C = approximated_C;
end if
end for

solutions are compared at last in terms of total FA count

of the corresponding architectures. The final solution is the
one which is with the minimum cost. The main steps of the
overall algorithm (named as TFC_approximation) are sum-
marized in Algorithm 5. The function TF_merging performs
the TFMerging as presented in Section III-A and returns the
nontrivial TFCs. The function Initialize_TFC determines the
initial precision of nontrivial TFCs by truncating insignif-
Fig. 4. Flow chart of the proposed TFC_approximation algorithm.
icant bits with the constraint on transformation error. The
minimum wordlength of TFCs which makes the error to be
lower than δ is selected as initial precision. However, longer TABLE II
Q UANTITATIVE I MPROVEMENT OF E ACH P ROPOSED M ETHOD
TFC wordlength than the initial length does not necessarily
cause higher FA count because longer lengths can provide
more opportunities for such approximation. Therefore, after
applying the initial precision, the coefficient wordlength is
increased until further increment can no longer contribute to
FA count reduction. The function Find_CS searches CS in the
truncated TFCs.
With the proposed algorithm, we generate the approxi-
mated TFCs and the minimized cost for an FFT imple- A. Design Example
mentation. The problem formulated in (5) is then solved. We present the design flow of 16-point FFT architectures to
To clearly show the entire algorithm, the flow chart of demonstrate the proposed algorithm. Since the proposed algo-
the proposed TFC_approximation algorithm is presented rithm needs the maximum error allowed to run, we assume
in Fig. 4. four specific transformation error requirements. The first one
δ1 = 5.3e−5 is the transformation error of one competing
design in [14] where the precision of TFCs is 10-bit such that
IV. L OGIC S YNTHESIS R ESULTS AND D ISCUSSION the FFT implementation is virtually exact. If the maximum
In this section, 16- and 32-point approximated FFT archi- error allowed is relaxed to δ2 = 1.9e−3 and δ3 = 1.9e−2 ,
tectures are designed using the proposed algorithm. They are there is more freedom to approximate TFCs to achieve lower
compared with two recently published works and the results FA cost. The last one δ4 = 1.7e−1 is the transformation
by logic synthesis are presented and discussed. error of another competing design proposed in [28]. The TFCs

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HAN et al.: NOVEL AREA-POWER EFFICIENT DESIGN FOR APPROXIMATED SMALL-POINT FFT ARCHITECTURE
Fig. 5. (a) Unit impulse input in time domain. (b) Frequency magnitude
responses of the input by exact FFT. (c) Frequency magnitude responses of
the input by approximated FFT (transformation error is 5.3e−5 ). (d) Frequency
magnitude responses of the input by approximated FFT (transformation error
is 1.9e−3 ). (e) Frequency magnitude responses of the input by approximated
FFT (transformation error is 1.9e−2 ). (f) Frequency magnitude responses of
the input by approximated FFT (transformation error is 1.7e−1 ).
in [28] were approximated heavily so that the correspond-
ing error is much higher. Therefore, we set δ 4 as the biggest
error requirement in our experiment. For the ease of compar-
ing the four transformation errors, we assume a unit impulse
input in time domain [as shown in Fig. 5(a)] and transform
it into its frequency domain representations. The frequency
magnitude responses of exact FFT, approximated FFTs with
the maximum error allowed being 5.3e−5 , 1.9e−3 , 1.9e−2 ,
and 1.7e−1 are shown in Fig. 5(b)–(f), respectively. The four
transformation errors demonstrate examples of virtually exact,
moderately and excessively approximated FFTs. Because the
algorithmic flow is the same for different errors, we take
δ3 = 1.9e−2 as one example. The first step is to perform
the TFMerging. All the expressions for the computation of
FFT outputs are re-expressed by merging nontrivial TFCs.
The second step is approximation. All the nontrivial TFCs
are processed by the proposed approach under the constraint
that the transformation error is no more than 1.9e−2 . The
algorithm terminates when the wordlength of TFCs is 7-bit
along with the usage of CSSharing scheme and the final total
FA count is 1033. Table II shows the quantitative improve-
ment of each proposed method in our algorithm. The design
of [14] is chosen as a competing method. We first apply
the TFMerging technique to a radix-2 DIT-FFT architecture
which is with the same transformation error with the design
of [14]. The FA count saving by the merging technique is
472. Next, we apply the magnitude-response aware approx-
imation (TFC_approximation) algorithm to nontrivial TFCs
together with the CSSharing, which reduces the FA count
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4823
Fig. 6. CS-shared structure when the maximum error allowed is 1.9e−2 .
TABLE III
T OTAL FA C OUNT AND T RANSFORMATION E RROR OF THE FFT D ESIGNS
further by 179. The reason why we apply TFC_approximation
and CSSharing together is because that the objective of
approximation is to create more opportunity for sharing and
the benefit by the approximation must be realized by the subse-
quent sharing. From Table II, it is obvious that the TFMerging
technique brings significant improvement to FA count reduc-
tion. Moreover, the proposed TFC_approximation algorithm
creates opportunities for reusing hardware which can be
achieved by the CSSharing. An additional 179 FA count is
saved consequently.
With the approximated TFCs returned by Approx algo-
rithm, the CS-shared structure for implementing cos(π /8) and
sin(π /8) is shown in Fig. 6. The 16-point approximated FFT
architecture for this design example is depicted in Fig. 7.
The UAS operator performs addition and subtraction of two
input signals simultaneously. The RIC block combines real
and imaginary parts generated by the proposed architecture
and lists all the final outputs for 16-point FFT. It is obvious
that only 12 multiplications with nontrivial TFCs (one shared
structure performs two multiplications at a time) are required
in this design. This is much less than that of Fig. 1 where
40 multiplications with nontrivial TFCs are involved.
B. Results and Discussion
The above four 16-point approximated FFT architectures
by our algorithm are compared with three state-of-the-art
works proposed in [5], [14], and [28]. Since the FFT pro-
cesser in [14] is multiradix which supports a number of
transformation sizes, we extract the 16-point FFT design
by using its radix-16 core. The extracted 16-point FFT
core only involves necessary hardware to compute 16-point
FFT. Redundant resources which cause unfair comparison
are not included. Similarly, 32-point FFT architectures are
also designed using the proposed algorithm and compared
with [14]. As the design in [28] is for 16-point approximated
FFT implementation only, we do not compare our 32-point
architectures with [28]. The total FA count (#FAs) and the
error of the FFT designs are given in Table III. Among
4824 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 12, DECEMBER 2020

Fig. 7. Approximated 16-point FFT architecture.

TABLE IV
the proposed FFT designs, AFFT1 and AFFT5 are with the C OMPARISON B ETWEEN THE FFT D ESIGNS ON FPGA. (a) 16-P OINT
same ransformation errors as the 16- and 32-point designs FFT D ESIGNS . (b) 32-P OINT FFT D ESIGNS
in [14], respectively, while the others are less accurate. To
compare the hardware cost more accurately, all designs are
described in Verilog HDL and mapped to Xilinx Virtex7,
xc7s75fgga484 FPGA device. Xilinx Vivado Design Suite
v17.4 is used to synthesize the designs. The number of LUTs
(#LUTs), the utilization density of LUTs, the number of IOs
(#IOs), the utilization density of IOs and delays in ns of 16-
and 32-point FFT designs are shown in Table IV. At least
41.2% and 56.4% improvements are achieved by our 16- and
32-point designs, respectively, over the designs of [5] and [14]
in terms of #LUTs. Our designs have shorter delays com-
pared with [5] and [14]. The reason is that the merging
technique reduces the number of multiplications and there-
fore #FAs in the critical path is reduced. Design of [5] has
larger delays since the iteration operation in CORDIC scheme
lead to more adders in the critical path. The reason why
AFFT4 and AFFT8 reduce #LUTs dramatically over the 16-
and 32-point designs in [5] and [14] is because their high
transformation error tolerance cause excessively approximated
TFCs, with which all the multiplications in the FFT archi-
tecture can be implemented by direct hardwiring. Compared
with another excessively approximated 16-point FFT design The on-chip memory requirement of the designs are
proposed in [28], AFFT4 saves 8.4% FPGA area benefitting presented in Table V. The proposed FFT implementations have
from the proposed techniques. The FPGA areas of the 16- lower register cost, because the proposed merging technique
and 32-point approximated FFT designs are plotted in Fig. 8. reduces the number of temporary TFM partial products which
The FPGA areas of the 16- and 32-point FFT designed by requires storage.
using the conventional radix-2 DIT-FFT algorithm are used To verify the performance on ASIC, all the designs are also
as the baseline. All other areas of FFT architectures by our mapped to 45-nm standard cell library and synthesized by
algorithm, [5], [14], and [28] are normalized by the baseline. Synopsys design compiler. We choose the same cell library

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HAN et al.: NOVEL AREA-POWER EFFICIENT DESIGN FOR APPROXIMATED SMALL-POINT FFT ARCHITECTURE
Fig. 8. Normalized FPGA areas of 16- and 32-point FFT designs.
TABLE V
O N -C HIP M EMORY R EQUIREMENT OF THE FFT D ESIGNS
TABLE VI
C OMPARISON B ETWEEN THE FFT D ESIGNS ON ASIC
and synthesize all the designs using the same version of
DesignCompiler to make sure that the same FA cells are used
to implement different designs for fair comparison. The syn-
thesized areas in μm2 and delays in ns of the FFT designs
are shown in Table VI. The normalized ASIC areas of FFT
architectures designed by the proposed algorithm, [5], [14],
and [28] are plotted in Fig. 9. Similarly, the areas of the
designs by radix-2 DIT-FFT algorithm are used as the baseline.
From the comparison, AFFT1 and AFFT5 save ASIC area by
up to 65.7% and 58.8% compared with the 16- and 32-point
designs in [5] and [14], respectively. The result is consistent
with the hardware cost reduction on FPGA device.
In addition to hardware area and delay, total power dis-
sipation which includes dynamic power and static power is
another critical metric to evaluate hardware performance [38].
The power dissipations of all approximated FFT designs are
first implemented on FPGA device and synthesized by Xilinx
Vivado Design Suite v17.4. The same output rate of 25 MHz
and supply voltage of 1.0 V are set for all experiments to
have a fair comparison. Moreover, designs are mapped to
standard cell library for ASIC and simulated by Synopsys
PowerComplier version: J-2014.09-SP3. An output rate of
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4825
Fig. 9. Normalized ASIC areas of 16- and 32-point FFT designs.
TABLE VII
P OWER D ISSIPATIONS IN mW FOR FPGA AND ASIC I MPLEMENTATION
Fig. 10. Normalized power dissipations of 16-point FFT designs.
25 MHz and a supply voltage of 1.0 V are used. The power dis-
sipations in mW of all designs simulated on both FPGA device
and ASIC are listed in Table VII. To present the results visu-
ally, they are plotted in Figs. 10 and 11, respectively, for 16-
and 32-point FFTs, where the powers of designs by radix-2
DIT-FFT algorithm are used as the baseline. Our AFFT1 and
AFFT5 save ASIC power by up to 53.1% and 60.0% compared
with the 16- and 32-point designs in [5] and [14], respectively.
The power dissipation of AFFT4 on ASIC outperforms the
design in [28] by 5.3%.
For an N-point DIT-FFT architecture (N ≥ 32), the non-
trivial TFCs exist in (log2 N − 2) stages. The TFMerging
technique can be applied to more stages as N increases. We
have more chances to reduce the number of multiplications
in large-size FFTs because of the much more TFCs exist-
ing compared to small-size FFTs. The magnitude-response
aware approximation algorithm can be applied in the same way
because the errors evaluation and approximations to reduce
FA cost are not limited to small-size FFTs. Additionally, large-
size FFTs can also be decomposed into small-size FFTs and
4826 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 12, DECEMBER 2020
Fig. 11. Normalized power dissipations of 32-point FFT designs.
therefore be implemented by recursively adopting the small-
size FFT cores as presented in this article. In conclusion,
large-size FFTs can benefit from the proposed methods, sim-
ilarly as the small-size FFTs, and at least the same or even
better savings on hardware cost and power dissipation can be
achieved.
V. C ONCLUSION
A new hardware area-power efficient approximated FFT
design is presented in this article. The proposed TFMerging
technique and magnitude-response aware approximation algo-
rithm provide an efficient solution to approximate TFCs for
deriving a new architecture for N-point FFT implementa-
tion. Both 16- and 32-point FFT architectures are designed
by applying the proposed algorithm. In ASIC implementa-
tion using 45-nm standard cell library, our 16- and 32-point
designs save area by up to 65.7% and 58.8%, respectively, over
relevant designs published recently. Meanwhile, the power
simulations results show that the 16- and 32-point FFT archi-
tectures designed by our algorithm save power dissipation by
up to 53.1% and 60.0%, respectively, compared with recently
published solutions.
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Xueyu Han received the B.Eng. degree from
Northwestern Polytechnical University, Xi’an,
China, in 2017, where she is currently pursuing
the Ph.D. degree with the Center of Intelligent
Acoustics and Immersive Communications.
Her research interests include algorithms and
circuit design for digital signal processing.
Jiajia Chen received the B.Eng. (Hons.) and Ph.D.
degrees from Nanyang Technological University,
Singapore, in 2004 and 2010, respectively.
From April 2012 to March 2018, he was
a Faculty Member with the Singapore University
of Technology and Design, Singapore. Since
April 2018, he has been with the Nanjing University
of Aeronautics and Astronautics, Nanjing, China,
where he is currently a Professor. His research
interest includes computational transformations of
low-complexity digital circuits and digital signal
processing.
Prof. Chen served as the Web Chair of the Asia–Pacific Computer Systems
Architecture Conference in 2005, the Technical Program Committee Member
of European Signal Processing Conference in 2014, and the Third IEEE
International Conference on Multimedia Big Data in 2017, and has been serv-
ing as an Associate Editor for the EURASIP Journal on Embedded Systems
(Springer) since 2016.
Authorized licensed use limited to: GLA University. Downloaded on November 05,2022 at 07:27:50 UTC from IEEE Xplore. Restrictions apply.
4827
Boyu Qin is currently pursuing the B.Eng. degree
with the College of Electronic and Information
Engineering, Nanjing University of Aeronautics and
Astronautics, Nanjing, China.
His research interest includes digital circuits
design and implementation.
Susanto Rahardja (Fellow, IEEE) received the
B.Eng. degree from the National University of
Singapore, Singapore, and the M.Eng. and Ph.D.
degrees in electronic engineering from Nanyang
Technological University, Singapore.
He is currently the Chair Professor with
Northwestern Polytechnical University, Xi’an,
China, under the Thousand Talent Plan of People’s
Republic of China. He attended the Stanford
Executive Programme with the Graduate School
of Business, Stanford University, Stanford, CA,
USA. He contributed to the development of a series of audio compression
technologies, such as Audio Video Standards AVS-L, AVS-2 and ISO/IEC
14496-3:2005/Amd.2:2006, and ISO/IEC 14496-3:2005/Amd.3:2006 in
which some have been licensed to several companies. He has more than
15 years of experience in leading research team for media related research
that cover areas in signal processing (audio coding, video/image processing),
media analysis (text/speech, image, video), media security (biometrics,
computer vision, and surveillance), and sensor networks. He has published
more than 300 papers and has been granted more than 70 patents worldwide
out of which 15 are U.S. patents. His research interests are in multimedia,
signal processing, wireless communications, discrete transforms, machine
learning, and signal processing algorithms and implementation.
Dr. Rahardja was a recipient of several honors, including the IEE Hartree
Premium Award, the Tan Kah Kee Young Inventors’ Open Category Gold
Award, the Singapore National Technology Award, the A*STAR Most
Inspiring Mentor Award, the Finalist of the 2010 World Technology and
Summit Award, the Nokia Foundation Visiting Professor Award, and
the ACM Recognition of Service Award. He was an Associate Editor
of the IEEE T RANSACTIONS ON AUDIO , S PEECH AND L ANGUAGE
P ROCESSING and the IEEE T RANSACTIONS ON M ULTIMEDIA, and the
Senior Editor of the IEEE J OURNAL OF S ELECTED T OPICS IN S IGNAL
P ROCESSING. He is currently serving as an Associate Editor for the Journal
of Visual Communication and Image Representation (Elsevier) and the
IEEE T RANSACTIONS ON M ULTIMEDIA. He was the Conference Chair
of fifth ACM SIGGRAPHASIA in 2012 and APSIPA second Summit and
Conference in 2010 and 2018, as well as other conferences in ACM, SPIE,
and IEEE.