A B C D E

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SA0000C1620
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S IC FJ8068403999819 QQAT W 0 1.8G BGA 1528

HDMI LOGO LOGO@ QQAT@
RO0000003HM SA0000C1520

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X4EAD5BOL01 S IC FH8068403419526 QPHY D0 1.4G BGA

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Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
‘˜‡”Š‡‡–
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Monday, July 23, 2018 Sheet 1 of 57
A B C D E
 A B C D E

,D/ŽŶŶ͘ ĞW
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page 29 page 28 Memory BUS page 19

1
DDI1 Dual Channel 1

ϮϲϬƉŝŶZϰͲ^KͲ/DDyϭ
HDMI x 4 lanes
eDP /ŶƚĞůtŚŝƐŬĞLJůĂŬĞh 1.2V DDR4 2133/2400

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N17S-G0,G1,G2
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x2 21~27

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8GT/s
page 31
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8GT/s
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port 1-4 Base-U PCIE2.0
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page 35 page 35 page 28 page 34

SATA3.0 USBx8 48MHz

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t>E 2.5GT/s 2.5GT/s port 7
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HD Audio
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page 40

Security Classification Compal Secret Data Compal Electronics, Inc.

WŽǁĞƌŝƌĐƵŝƚͬ Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title
Block Diagrams
page 41~54 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Tuesday, January 22, 2019 Sheet 2 of 57
A B C D E
 A B C D E

Board ID Table for AD channel

Vcc 3.3V +/- 5%
Ra 100K +/- 1% Power State
Board ID Rb V BID min V BID typ V BID max EC AD3 PCB Revision SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
0 0 0 V 0 V 0.300 V 0x00 - 0x13 0.1(EVT)
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E 0.2(DVT) S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
2 15K +/- 1% 0.423 V 0.430 VVinafix.com 0.438 V 0x1F - 0x25 1.0(PVT) S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
1
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 1.A(MP) 1

4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64

Voltage Rails
Power Plane Description S0 S3 S4/S5
+19V_VIN Adapter power supply N/A N/A N/A
+12.6V_BATT Battery power supply N/A N/A N/A
BOM Structure Table

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+19VB AC or battery power rail for power circuit. N/A N/A N/A
+VCC_CORE Processor IA Cores Power Rail ON OFF OFF
BOM Option Table BOM Option Table
+VCC_GT Processor Graphics Power Rails ON OFF OFF
Item BOM Structure Item BOM Structure +VCC_SA ON OFF OFF
System Agent power rail

mp
hŶƉŽƉ Λ –ƒ‰‡ sdΛͬsdΛͬWsdΛͬDWΛ +0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON OFF OFF
ŽŶŶĞĐƚŽƌ KEEΛ Eϭϲ^'dZŽƌEϭϳ^'ϭ Eϭϲ^'dZΛͬEϭϳ^'ϭΛ +1.05VALW_PRIM +1.05V Always power rail ON ON ON*1
ĐĞƌ zK zKΛ ͬ EzKΛ
 ‡•‘” '^EΛ +1.05V_VCCSTU Sustain voltage for processor in Standby modes ON ON OFF
K ϮϱϱΛͬϮϱϲΛ ‘” ‘˜‡” ͵ …‡ŽŽ „ƒ––‡”› ϯ^Λ +VCCIO CPU IO power rail ON OFF OFF
2 ‘†‡‡Ž‡…– >WΛͬ^W/Λ ‡Ž‡…– yϳϲΛ 2

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+1.05VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST ON OFF OFF
&Žƌ/ŶƚĞůD DΛ ‡Ž‡…– yϳϲϬϰΛΕyϳϲϬϵΛ +1.2V_VDDQ DDR4 +1.2V Power Rail ON ON OFF
 ‘†‡ ‡Ž‡…– ^tZΛͬ>KΛ  sWZKΛ +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1
D/ƌĞƋƵŝƌĞŵĞŶƚ D/ΛͬΛD/Λ +1.8VS System +1.8V power rail ON OFF OFF

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^ ƌĞƋƵŝƌĞŵĞŶƚ ^ΛͬΛ^Λ +3VLP +19VB to +3VLP power rail for suspend power ON ON ON
Z&ƌĞƋƵŝƌĞŵĞŶƚ ΛZ&Λ +3VALW System +3VALW always on power rail ON ON ON*1
‡Ž‡…–‹‘ hϰϮΛͬhϮϮΛ +3VS System +3V power rail ON OFF OFF
'Wh^ĞƌŝĂů^ĞůĞĐƚ EϭϲyΛͬEϭϳ^Λ +5VALW +5V Always power rail ON ON ON

nfi
 dWDΛ +5VS System +5V power rail ON OFF OFF
‹‰‡””‹– &WΛͬ&WDΛͬdhΛ WhŽĚĞ ϴϭϰϱΛ +RTCVCC RTC Battery Power ON ON ON
&ŝŶŐĞƌƉƌŝŶƚƉŽǁĞƌ &WϯsΛͬ&WϱsΛ ϴϮϲϱΛ +1.05VS_1.0VSDGPU +1.05VS power rail for N16X/ +1.0VS power rail for N17S ON*2 OFF OFF
hDŽƌ'Wh hDΛͬs'Λ ϴϱϲϱΛ

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+1.35VSDGPU +1.35VS power rail for GPU ON*2 OFF OFF
+3VS_1.8VSDGPU_AON +3VS power rail for N16X/ +1.8VS power rail for N17S(AON) ON*2 OFF OFF
+3VS_1.8VSDGPU_MAIN +3VS power rail for N16X/ +1.8VS power rail for N17S(MAIN) ON*2 OFF OFF

+VGA_CORE Core power for descrete GPU ON*2 OFF OFF

nti 3

al Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.
ON*2 power plane is ON when DGPU turn on

43 level BOM table

43 Level Description BOM Structure
431AD5BOL18 SMT MB AG521 EH5AW I38145U UMA HDMI DAZ@/8145@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/UMA@/MP@/X4E@/RTC@

431AD5BOL19 SMT MB AG521 EH5AW I58265U UMA HDMI DAZ@/8265@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/UMA@/MP@/X4E@/RTC@

431AD5BOL20 SMT MB AG521 EH5AW I78565U UMA HDMI DAZ@/8565@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/UMA@/MP@/X4E@/RTC@

431AD5BOL21 SMT MB AG521 EH5AW I38145U N16 HDMI DAZ@/8145@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/VGA@/N16X@/N16SGTR@/X7605@/MP@/X4E@/RTC@

431AD5BOL22 SMT MB AG521 EH5AW I58265U N16 HDMI DAZ@/8265@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/VGA@/N16X@/N16SGTR@/X7605@/MP@/X4E@/RTC@

431AD5BOL23 SMT MB AG521 EH5AW I78565U N16 HDMI DAZ@/8565@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/VGA@/N16X@/N16SGTR@/X7605@/MP@/X4E@/RTC@

431AD5BOL24 SMT MB AG521 EH5AW I38145U N17 HDMI DAZ@/8145@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/VGA@/N17S@/N17SG1@/N17X76@/MP@/X4E@/RTC@

4 4
431AD5BOL25 SMT MB AG521 EH5AW I58265U N17 HDMI DAZ@/8265@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/VGA@/N17S@/N17SG1@/N17X76@/MP@/X4E@/RTC@

431AD5BOL26 SMT MB AG521 EH5AW I78565U N17 HDMI DAZ@/8565@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/VGA@/N17S@/N17SG1@/N17X76@/MP@/X4E@/RTC@

431AD5BOL27 SMT MB AG521 EH5AW I38145U N16 V6 HDMI DAZ@/8145@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/VGA@/N16X@/N16SGTR@/X76793BOL03@/MP@/X4E@/RTC@

431AD5BOL28 SMT MB AG521 EH5AW I58265U N16 V6 HDMI DAZ@/8265@/CNVI@/CHG@/3S@/LPC@/CMC@/255@/BYOC@/LDO@/VGA@/N16X@/N16SGTR@/X76793BOL03@/MP@/X4E@/RTC@

Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Friday, August 17, 2018 Sheet 3 of 57
A B C D E
 A B C D E

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4 4

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;WhϭϮϬϭͿ Eϭϳ^ͺs'Λ
EͺϭϮs^W ,ϮϬϭϮ<&
н/EsWtZͺн
;>yϭͿϯ^Λ

Security Classification Compal Secret Data Compal Electronics, Inc.

2018/01/10 2018/11/04 Title
Issued Date Deciphered Date Power Rail
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date : Thursday, July 12, 2018 Sheet 4 of 57
A B C D E
 A B C D E

2.2K 2.2K

2.2K
+3VALW_PRIM 2.2K
+3VS

CK14 SOC_SMBCLK Vinafix.com

SOC_SMBDATA 2N7002DW
1 SO-DIMM 1
CH15

Whiskeylake
SOC
SOC_SML0CLK 2.2K
CH14 G-Sensor

2.2K
+3VALW_PRIM
CF15 SOC_SML0DATA
1.8K
2.2K

Co
1.8K
+3VS_1.8VSDGPU_AON
2.2K
+3VALW_PRIM

CN15 SOC_SML1CLK I2CS_SCL

mp
D9
PJT138KA GPU
CM15 SOC_SML1DATA I2CS_SDA D8

2 2

al 2.2K

Co 2.2K
+3VLP_EC

77 EC_SMB_CK1 100 ohm EC_SMB_CK1-1 4

SCL1 BATTERY
78 EC_SMB_DA1 100 ohm

nfi
EC_SMB_DA1-1 3
SDA1 CONN

9
Charger

de
8

KBC SCL2 79 SOC_SML1CLK

nti
SDA2 80 SOC_SML1DATA

3
KB9022 3

al I2C Address Table

I2C_0 (+3VS)
BUS
Reserved
Device Address (8 bit)

TM-P2969-001 (TP) 0x2C

I2C_1 (+3VALW_PRIM)
SB8787-1200 (TP-ELAN) 0x15
SO-DIMM1 0xA0
SOC_SMBCLK (+3VS) SO-DIMM2 0xA4
G-Sensor 0x30
SOC_SML1CLK GPU 0x9E
(+3VALW_PRIM) EC
ISL88739 (Charger IC) 0x12
EC_SMB_CK1 (+3VLP)
4 BATTERY PACK 0x16 4

Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
̸‘—–‹‰̸ƒ„Ž‡
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 5 of 57
A B C D E
 A B C D E

PWR Sequence_WHL-U_DDR4_Value_NON CS

+RTCVCC
tPCH01_Min : 9 ms
SOC_RTCRST#
Vinafix.com
1
+19VB 1

+3VLP

EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW(+3VALW_DSW...)
tPCH34_Max : 50 ms (All PCH Primary Rails should ramp up within this window)
SPOK_3V_5V tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.05VALW_PRIM starting to ramp)

+1.8VALW_PRIM

Co
+1.8VALW_PG

+1.05VALW_PRIM
tPCH03_Min : 10 ms
EC_RSMRST#

2
AC_PRESENT

ON/OFF

PBTN_OUT#
mp
tPCH43_Min : 95 ms 2

al
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST#

PM_SLP_S4#

SYSON
Co
nfi
+1.05V_VCCSTU

+1.2V_VDDQ

PM_SLP_S3#

SUSP#

+1.05VS_VCCSTG
de tCPU04 Min : 0 ns

3
+VCCIO

+5VS/+3VS/+1.8VS/+1.05VS
nti tCPU00 Min : 1 ms
3

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.6VS_VTT
al tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms
+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK tPLT05 Min : Platform dependent

4
SYS_PWROK 4

PLT_RST#

Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
‘™‡”‡“—‡…‡
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Friday, August 17, 2018 Sheet 6 of 57
A B C D E
 A B C D E

UC1A
AL5 AG4
<29> SOC_DP1_N0 AL6 DDI1_TXN_0 EDP_TXN_0 AG3 EDP_TXN0 <28>
<29> SOC_DP1_P0 AJ5 DDI1_TXP_0 EDP_TXP_0 AG2 EDP_TXP0 <28>

Vinafix.com
<29> SOC_DP1_N1 AJ6 DDI1_TXN_1 EDP_TXN_1 AG1 EDP_TXN1 <28>
<29> SOC_DP1_P1 AF6 DDI1_TXP_1 EDP_TXP_1 AJ4 EDP_TXP1 <28>
,D/ <29> SOC_DP1_N2 AF5 DDI1_TXN_2 EDP EDP_TXN_2 AJ3 EDP_TXN2 <28>
<29> SOC_DP1_P2 AE5 DDI1_TXP_2 EDP_TXP_2 AJ2 EDP_TXP2 <28> ĞW
1 <29> SOC_DP1_N3 AE6 DDI1_TXN_3 EDP_TXN_3 AJ1 EDP_TXN3 <28> 1
<29> SOC_DP1_P3 DDI1_TXP_3 DDI EDP_TXP_3 EDP_TXP3 <28>
AC4
AC3 DDI2_TXN_0 AH4
DDI2_TXP_0 EDP_AUX_N EDP_AUXN <28>
AC1 AH3
DDI2_TXN_1 EDP_AUX_P EDP_AUXP <28>
AC2
AE4 DDI2_TXP_1 AM7
AE3 DDI2_TXN_2 DISP_UTILS
AE1 DDI2_TXP_2 AC7
AE2 DDI2_TXN_3 DDI1_AUX_N AC6
DDI2_TXP_3 DDI1_AUX_P AD4
DDI2_AUX_N AD3
DDI2_AUX_P AG7
DISPLAY SIDEBANDS DDI3_AUX_N AG6
EDP_COMP AM6 DDI3_AUX_P
,D/;WŽƌƚͿ DISP_RCOMP
ηϱϳϭϬϮϭ&>ͲhW'ZϬ͘ϳƉ͘ϭϬϰ SOC_DP1_CTRL_CLK CC8 CN6 SOC_DP1_HPD
&ƌŽŵ,D/

Co
<29> SOC_DP1_CTRL_CLK SOC_DP1_CTRL_DATA CC9 GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE# GPP_E13/DDPB_HPD0/DISP_MISC0 SOC_DP1_HPD <29>
CM6
<29> SOC_DP1_CTRL_DATA GPP_E19/DPPB_CTRLDATA GPP_E14/DDPC_HPD1/DISP_MISC1 CP7
CH4 GPP_E15/DPPD_HPD2/DISP_MISC2 CP6 EC_SCI#
CH3 GPP_E20/DPPC_CTRLCLK GPP_E16/DPPE_HPD3/DISP_MISC3 CM7 CPU_EDP_HPD EC_SCI# <36>
GPP_E21/DPPC_CTRLDATA GPP_E17/EDP_HPD/DISP_MISC4 CPU_EDP_HPD <28>&ƌŽŵ ĞW
CP4 CK11 ENBKL
CN4 GPP_E22/DPPD_CTRLCLK EDP_BKLTEN CG11 SOC_ENVDD ENBKL <36>
GPP_E23/DPPD_CTRLDATA EDP_VDDEN CH11 SOC_BKL_PWM SOC_ENVDD <28>

mp
CR26 EDP_BKLTCTL SOC_BKL_PWM <28>
CP26 GPP_H16/DDPF_CTRLCLK
GPP_H17/DDPF_CTRLDATA

RC212 +3VS
WHL-U42_BGA1528 10K_0402_5%
2 EC_SCI# 1 @ 2 2
@

al
1 of 20

EC_SCI# SOC internal PU

+VCCIO

1 2 24.9_0402_1% EDP_COMP ηϱϰϱϲϱϵ W, ^ϭ͘ϱϭ W͘ϭϯϭ

Co
RC1
^/ĐĂƉĂďŝůŝƚLJŝƐĂǀĂŝůĂďůĞŽŶĂůů'W/KƐ͕ǁŚŝůĞ
ED/ĂŶĚ^D/ĐĂƉĂďŝůŝƚLJŝƐĂǀĂŝůĂďůĞŽŶŽŶůLJ
ηϱϳϭϬϮϭ&>ͲhW'ZϬ͘ϳƉ͘ϯϵ ƐĞůĞĐƚ 'W/KƐ͘
WhϮϰ͘ϵŽŚŵĨŽƌĞW ĞůŽǁ ĂƌĞ ƚŚĞ W, 'W/KƐ ƚŚĂƚ ĐĂŶ ďĞ
ƌŽƵƚĞĚ ƚŽ ŐĞŶĞƌĂƚĞ ^D/η Žƌ ED/͗
Ʉ 'WWͺϭϰ͕  'WWͺϮϬ͕  'WWͺϮϯ

nfi
Ʉ 'WWͺ΀ Ϯϯ͗  ϮϮ΁
+1.05V_VCCST ηϱϳϭϬϮϭ&>ͲhW'ZϬ͘ϳƉ͘Ϯϰϴ Ʉ 'WWͺ ΀ ϰ͗  Ϭ΁
Whϭ<ŽŚŵƚŽs^d Ʉ 'WWͺ΀ ϴ͗  Ϭ΁͕  'WWͺ΀ ϭϲ͗  ϭϯ΁

RC2 1 2 1K_0402_5% H_THERMTRIP#

de
1 2 +1.05VS_VCCSTG @ESD@ CC81
CC132 ESD@ ZĞƐĞƌǀĞĚdZZη .1U_0402_16V7K
1000P_0402_50V7K SOC_XDP_TRST# 1 2
ĨŽƌ  ƐŝŐŚƚ ŝ ŶŐƐŝ ƐƐ ƵĞ
1

RC3 ĐŚĞĐŬ

nti
1K_0402_5% UC1D
RC4 H_CATERR# AA4 T6 CPU_XDP_TCK0
@ T166 H_PECI CATERR# PROC_TCK SOC_XDP_TDI
499_0402_1% <36> AR1 U6
H_PECI
2

1 2 H_PROCHOT#_R Y4 PECI CPU MISC JTAG

PROC_TDI Y5 SOC_XDP_TDO
3 <36,43> H_PROCHOT# H_THERMTRIP# PROCHOT# PROC_TDO SOC_XDP_TMS 3
BJ1 T5
THRMTRIP# PROC_TMS AB6 SOC_XDP_TRST#
XDP_BPM#0 U1 PROC_TRST#
@ T160

al
CC52 @ESD@ XDP_BPM#1 U2 BPM#_0
@ T161 BPM#_1 PCH_JTAG_TCK1
.1U_0402_16V7K U3 W6 T280 @
2 1 H_PECI U4 BPM#_2 PCH_TCK U5 SOC_XDP_TDI
BPM#_3 PCH_TDI W5 SOC_XDP_TDO UC1
PCH_TDO P5 SOC_XDP_TMS
CE9 PCH_TMS Y6 SOC_XDP_TRST#
2 1 H_PROCHOT#_R CN3 GPP_E3/CPU_GP0 PCH_TRST# P6 CPU_XDP_TCK0 S IC FJ8068404000016 QQAU W0 1.6G BGA
ESD@ CC53 RC137 2 @ 1 0_0402_5% TP_INT# CB34 GPP_E7/CPU_GP1 PCH_JTAGX QQAU@
<36,37> EC_TP_INT# CC35 GPP_B3/CPU_GP2
1000P_0402_50V7K SA0000C1620
GPP_B4/CPU_GP3 W2 XDP_PREQ#
PROC_PREQ# XDP_PRDY# T197 @
W1 T196 @
RC5 2 1 49.9_0402_1% CPU_POPIRCOMP BP27 PROC_PRDY#
RC6 2 1 49.9_0402_1% PCH_OPIRCOMP BW25 PROC_POPIRCOMP UC1
PCH_OPIRCOMP

RC7 2 @ 1 49.9_0402_1% EDRAM_OPIO_RCOMP L5 S IC FJ8068403999819 QQAT W0 1.8G BGA 1528

+1.05VS_VCCSTG &Žƌ/ŶƚĞůĚĞďƵŐ͕ƉůĂĐĞƚŽWhƐŝĚĞ͘ RC8 2 @ 1 49.9_0402_1% EOPIO_RCOMP N5 RSVD70 QQAT@
ηϱϳϱϰϭϮt,>ͲhW'ZϬ͘ϴ&ŝŐƵƌĞ͘ϭϯͲϲ RSVD71
SA0000C1520
RC11 2 CMC@ 1 51_0402_5% SOC_XDP_TMS WHL-U42_BGA1528
ηϱϳϱϰϭϮt,>ͲhW'ZϬ͘ϴ
SOC_XDP_TDI &Žƌ &> hϰϯĞ͕ WŝŶƐ >ϱ ĂŶĚ Eϱ ĂƌĞ KWͺZKDW ĂŶĚ  KWͺZKDW ƌĞƐƉĞĐƚ ŝ ǀĞů LJ ǁŚŝů Ğŝ Ŷ @ 4 of 20
RC13 2 CMC@ 1 51_0402_5%
 t,>͕ E> ^ŽƐ ƚŚĞƐĞ ƉŝŶƐ ĂƌĞ Z^s

RC15 2 CMC@ 1 51_0402_5% SOC_XDP_TDO UC1

S IC FH8068403419526 QPHY D0 1.4G BGA

RC35 2 CMC@ 1 51_0402_5% CPU_XDP_TCK0 QPHY@
SA0000BX100
4 4

^ϭ

Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ǦȋͷȀͷ͸Ȍǡǡǡ
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 7 of 57
A B C D E
 A B C D E

/ŶƚĞƌůĞĂǀĞĚ DĞŵŽƌLJ
UC1B UC1C
<19> DDR_A_D[0..15] DDR_A_D0 A26 Interleave / Non-Interleaved <20> DDR_B_D[0..15] DDR_B_D0 J22
lnterleave /
Non-lnterleav e d
LPDDR3 / DDR4
AF28 DDR_B_CLK#0
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 LPDDR3 / DDR4 DDR_A_CLK#0 DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKN_0/DDR1_CKN_0 DDR_B_CLK0 DDR_B_CLK#0 <20>
D26 V32 H25 AF29
DDR_A_D2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR_A_CLK0 DDR_A_CLK#0 <19> DDR_B_D2 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK#1 DDR_B_CLK0 <20>
D28 V31 G22 AE28
DDR_A_CLK0 <19> DDR_B_CLK#1 <20>
DDR_A_D3
DDR_A_D4
DDR_A_D5
C28
B26
C26
DDR0_DQ_2/DDR0_DQ_2
DDR0_DQ_3/DDR0_DQ_3
DDR0_DQ_4/DDR0_DQ_4
Vinafix.com DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_1/DDR0_CKN_1
DDR0_CKP_1/DDR0_CKP_1
T32
T31
DDR_A_CLK#1
DDR_A_CLK1 DDR_A_CLK#1
DDR_A_CLK1
<19>
<19>
DDR_B_D3
DDR_B_D4
DDR_B_D5
H22
F25
J25
DDR1_DQ_2/DDR0_DQ_18
DDR1_DQ_3/DDR0_DQ_19
DDR1_DQ_4/DDR0_DQ_20
DDR1_CKN_1/DDR1_CKN_1
DDR1_CKP_1/DDR1_CKP_1
AE29

T28
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CLK1

DDR_B_CKE0
<20>

<20>
DDR_A_D6 B28 DDR0_DQ_5/DDR0_DQ_5 U36 DDR_A_CKE0 DDR_B_D6 G25 DDR1_DQ_5/DDR0_DQ_21 DDR1_CKE_0/DDR1_CKE_0 T29 DDR_B_CKE1
1 DDR_A_D7 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <19> DDR_B_D7 DDR1_DQ_6/DDR0_DQ_22 DDR1_CKE_1/DDR1_CKE_1 DDR_B_CKE1 <20> 1
A28 U37 F22 V28
DDR_A_D8 DDR0_DQ_7/DDR0_DQ_7 DDR0_CKE_1/DDR0_CKE_1 DDR_A_CKE1 <19> DDR_B_D8 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC
B30 U34 D22 V29
DDR_A_D9 D30 DDR0_DQ_8/DDR0_DQ_8 DDR0_CKE_2/NC U35 DDR_B_D9 C22 DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC
DDR_A_D10 B33 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_3/NC DDR_B_D10 C24 DDR1_DQ_9/DDR0_DQ_25 AL37 DDR_B_CS#0
DDR_A_D11 DDR0_DQ_10/DDR0_DQ_10 DDR_A_CS#0 DDR_B_D11 DDR1_DQ_10/DDR0_DQ_26 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#1 DDR_B_CS#0 <20>
D32 AE32 D24 AL35
DDR_A_D12 DDR0_DQ_11/DDR0_DQ_11 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#1 DDR_A_CS#0 <19> DDR_B_D12 DDR1_DQ_11/DDR0_DQ_27 DDR1_CS#_1/DDR1_CS#_1 DDR_B_ODT0 DDR_B_CS#1 <20>
A30 AF32 A22 AL36
DDR_A_D13 DDR0_DQ_12/DDR0_DQ_12 DDR0_CS#_1/DDR0_CS#_1 DDR_A_ODT0 DDR_A_CS#1 <19> DDR_B_D13 DDR1_DQ_12/DDR0_DQ_28 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT1 DDR_B_ODT0 <20>
C30 AE31 B22 AL34
DDR_A_D14 DDR0_DQ_13/DDR0_DQ_13 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <19> DDR_B_D14 DDR1_DQ_13/DDR0_DQ_29 NC/DDR1_ODT_1 DDR_B_MA0 DDR_B_ODT1 <20>
B32 AF31 A24 AG36
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 NC/DDR0_ODT_1 DDR_A_ODT1 <19> DDR_B_D15 DDR1_DQ_14/DDR0_DQ_30 DDR1_CAB_9/DDR1_MA_0 DDR_B_MA1 DDR_B_MA0 <20>
C32 B24 AG35
<19> DDR_A_D[16..31] DDR_A_D16 DDR0_DQ_15/DDR0_DQ_15 DDR_A_MA0 <20> DDR_B_D[16..31] DDR_B_D16 DDR1_DQ_15/DDR0_DQ_31 DDR1_CAB_8/DDR1_MA_1 DDR_B_MA2 DDR_B_MA1 <20>
H37 AC37 G31 AF34
DDR_A_D17 DDR0_DQ_16/DDR0_DQ_32 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA1 DDR_A_MA0 <19> DDR_B_D17 DDR1_DQ_16/DDR0_DQ_48 DDR1_CAB_5/DDR1_MA_2 DDR_B_MA3 DDR_B_MA2 <20>
H34 AC36 G32 AG37
DDR_A_D18 DDR0_DQ_17/DDR0_DQ_33 DDR0_CAB_8/DDR0_MA_1 DDR_A_MA2 DDR_A_MA1 <19> DDR_B_D18 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3 DDR_B_MA4 DDR_B_MA3 <20>
K34 AC34 H29 AE35
DDR_A_D19 DDR0_DQ_18/DDR0_DQ_34 DDR0_CAB_5/DDR0_MA_2 DDR_A_MA3 DDR_A_MA2 <19> DDR_B_D19 DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4 DDR_B_MA5 DDR_B_MA4 <20>
K35 AC35 H28 AF35
DDR_A_D20 DDR0_DQ_19/DDR0_DQ_35 NC/DDR0_MA_3 DDR_A_MA4 DDR_A_MA3 <19> DDR_B_D20 DDR1_DQ_19/DDR0_DQ_51 DDR1_CAA_0/DDR1_MA_5 DDR_B_MA6 DDR_B_MA5 <20>
H36 AA35 G28 AE37
DDR_A_D21 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_MA_4 DDR_A_MA5 DDR_A_MA4 <19> DDR_B_D21 DDR1_DQ_20/DDR0_DQ_52 DDR1_CAA_2/DDR1_MA_6 DDR_B_MA7 DDR_B_MA6 <20>
H35 AB35 G29 AC29
DDR_A_D22 DDR0_DQ_21/DDR0_DQ_37 DDR0_CAA_0/DDR0_MA_5 DDR_A_MA6 DDR_A_MA5 <19> DDR_B_D22 DDR1_DQ_21/DDR0_DQ_53 DDR1_CAA_4/DDR1_MA_7 DDR_B_MA8 DDR_B_MA7 <20>
K36 AA37 H31 AE36
DDR_A_D23 DDR0_DQ_22/DDR0_DQ_38 DDR0_CAA_2/DDR0_MA_6 DDR_A_MA7 DDR_A_MA6 <19> DDR_B_D23 DDR1_DQ_22/DDR0_DQ_54 DDR1_CAA_3/DDR1_MA_8 DDR_B_MA9 DDR_B_MA8 <20>
K37 AA36 H32 AB29

Co
DDR_A_D24 DDR0_DQ_23/DDR0_DQ_39 DDR0_CAA_4/DDR0_MA_7 DDR_A_MA8 DDR_A_MA7 <19> DDR_B_D24 DDR1_DQ_23/DDR0_DQ_55 DDR1_CAA_1/DDR1_MA_9 DDR_B_MA10 DDR_B_MA9 <20>
N36 AB34 L31 AG34
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAA_3/DDR0_MA_8 DDR_A_MA9 DDR_A_MA8 <19> DDR_B_D25 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_7/DDR1_MA_10 DDR_B_MA11 DDR_B_MA10 <20>
N34 W36 L32 AC28
DDR_A_D26 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAA_1/DDR0_MA_9 DDR_A_MA10 DDR_A_MA9 <19> DDR_B_D26 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAA_7/DDR1_MA_11 DDR_B_MA12 DDR_B_MA11 <20>
R37 Y31 N29 AB28
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAB_7/DDR0_MA_10 DDR_A_MA11 DDR_A_MA10 <19> DDR_B_D27 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAA_6/DDR1_MA_12 DDR_B_MA13 DDR_B_MA12 <20>
R34 W34 N28 AK35
DDR_A_D28 DDR0_DQ_27/DDR0_DQ_43 DDR0_CAA_7/DDR0_MA_11 DDR_A_MA12 DDR_A_MA11 <19> DDR_B_D28 DDR1_DQ_27/DDR0_DQ_59 DDR1_CAB_0/DDR1_MA_13 DDR_B_MA13 <20>
N37 AA34 L28
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAA_6/DDR0_MA_12 DDR_A_MA13 DDR_A_MA12 <19> DDR_B_D29 DDR1_DQ_28/DDR0_DQ_60 DDR_B_MA14
N35 AC32 L29 AJ35
DDR_A_D30 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_0/DDR0_MA_13 DDR_A_MA13 <19> DDR_B_D30 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_2/DDR1_MA_14 DDR_B_MA15 DDR_B_MA14 <20>
R36 N31 AK34
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR_A_MA14 DDR_B_D31 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA16 DDR_B_MA15 <20>
R35 AC31 N32 AJ34

mp
<19> DDR_A_D[32..47] DDR_A_D32 DDR0_DQ_31/DDR0_DQ_47 DDR0_CAB_2/DDR0_MA_14 DDR_A_MA15 DDR_A_MA14 <19>
<20> DDR_B_D[32..47] DDR_B_D32 DDR1_DQ_31/DDR0_DQ_63 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA16 <20>
AN35 AB32 AJ29
DDR_A_D33 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA16 DDR_A_MA15 <19> DDR_B_D33 DDR1_DQ_32/DDR1_DQ_16 DDR_B_BA0
AN34 Y32 AJ30 AJ37
DDR_A_D34 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA16 <19> DDR_B_D34 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <20>
AR35 AM32 AJ36
DDR_A_D35 DDR0_DQ_34/DDR1_DQ_2 DDR_A_BA0 DDR_B_D35 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_6/DDR1_BA_1 DDR_B_BG0 DDR_B_BA1 <20>
AR34 W32 AM31 W29
DDR_A_D36 DDR0_DQ_35/DDR1_DQ_3 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <19> DDR_B_D36 DDR1_DQ_35/DDR1_DQ_19 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <20>
AN37 AB31 AM30
DDR_A_D37 DDR0_DQ_36/DDR1_DQ_4 DDR0_CAB_6/DDR0_BA_1 DDR_A_BG0 DDR_A_BA1 <19> DDR_B_D37 DDR1_DQ_36/DDR1_DQ_20 DDR_B_BG1
AN36 V34 AM29 Y28
DDR_A_D38 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <19> DDR_B_D38 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <20>
AR36 AJ31 W28
2 DDR_A_D39 DDR0_DQ_38/DDR1_DQ_6 DDR_A_ACT# DDR_B_D39 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <20> 2
AR37 V35 AJ32
DDR_A_ACT# <19>

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DDR_A_D40 AU35 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_8/DDR0_ACT# W35 DDR_A_BG1 DDR_B_D40 AR31 DDR1_DQ_39/DDR1_DQ_23 lnterleave / Non-lnterleaved
H24 DDR_B_DQS#0
DDR_A_D41 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_9/DDR0_BG_1 DDR_A_BG1 <19> DDR_B_D41 DDR1_DQ_40/DDR1_DQ_24 DDR1_DQSN_0/DDR0_DQSN_2 DDR_B_DQS0 DDR_B_DQS#0 <20>
AU34 AR32 G24
DDR_A_D42 DDR0_DQ_41/DDR1_DQ_9 Interleave / Non-Interleaved DDR_A_DQS#0 DDR_B_D42 DDR1_DQ_41/DDR1_DQ_25 DDR1_DQSP_0/DDR0_DQSP_2 DDR_B_DQS#1 DDR_B_DQS0 <20>
AW35 C27 AV30 C23
DDR_A_D43 DDR0_DQ_42/DDR1_DQ_10 DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS0 DDR_A_DQS#0 <19> DDR_B_D43 DDR1_DQ_42/DDR1_DQ_26 DDR1_DQSN_1/DDR0_DQSN_3 DDR_B_DQS1 DDR_B_DQS#1 <20>
AW34 D27 AV29 D23
DDR_A_D44 DDR0_DQ_43/DDR1_DQ_11 DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS#1 DDR_A_DQS0 <19> DDR_B_D44 DDR1_DQ_43/DDR1_DQ_27 DDR1_DQSP_1/DDR0_DQSP_3 DDR_B_DQS#2 DDR_B_DQS1 <20>
AU37 D31 AR30 G30
DDR_A_D45 DDR0_DQ_44/DDR1_DQ_12 DDR0_DQSN_1/DDR0_DQSN_1 DDR_A_DQS1 DDR_A_DQS#1 <19> DDR_B_D45 DDR1_DQ_44/DDR1_DQ_28 DDR1_DQSN_2/DDR0_DQSN_6 DDR_B_DQS2 DDR_B_DQS#2 <20>
AU36 C31 AR29 H30
DDR_A_D46 DDR0_DQ_45/DDR1_DQ_13 DDR0_DQSP_1/DDR0_DQSP_1 DDR_A_DQS#2 DDR_A_DQS1 <19> DDR_B_D46 DDR1_DQ_45/DDR1_DQ_29 DDR1_DQSP_2/DDR0_DQSP_6 DDR_B_DQS#3 DDR_B_DQS2 <20>
AW36 J35 AV32 L30

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DDR_A_D47 DDR0_DQ_46/DDR1_DQ_14 DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS2 DDR_A_DQS#2 <19> DDR_B_D47 DDR1_DQ_46/DDR1_DQ_30 DDR1_DQSN_3/DDR0_DQSN_7 DDR_B_DQS3 DDR_B_DQS#3 <20>
AW37 J34 AV31 N30
<19> DDR_A_D[48..63] DDR_A_D48 DDR0_DQ_47/DDR1_DQ_15 DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS#3 DDR_A_DQS2 <19>
<20> DDR_B_D[48..63] DDR_B_D48 DDR1_DQ_47/DDR1_DQ_31 DDR1_DQSP_3/DDR0_DQSP_7 DDR_B_DQS#4 DDR_B_DQS3 <20>
BA35 P34 BA32 AL31
DDR_A_D49 DDR0_DQ_48/DDR1_DQ_32 DDR0_DQSN_3/DDR0_DQSN_5 DDR_A_DQS3 DDR_A_DQS#3 <19> DDR_B_D49 DDR1_DQ_48/DDR1_DQ_48 DDR1_DQSN_4/DDR1_DQSN_2 DDR_B_DQS4 DDR_B_DQS#4 <20>
BA34 P35 BA31 AL30
DDR_A_D50 DDR0_DQ_49/DDR1_DQ_33 DDR0_DQSP_3/DDR0_DQSP_5 DDR_A_DQS#4 DDR_A_DQS3 <19> DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 DDR1_DQSP_4/DDR1_DQSP_2 DDR_B_DQS#5 DDR_B_DQS4 <20>
BC35 AP35 BD31 AU31
DDR_A_D51 DDR0_DQ_50/DDR1_DQ_34 DDR0_DQSN_4/DDR1_DQSN_0 DDR_A_DQS4 DDR_A_DQS#4 <19> DDR_B_D51 DDR1_DQ_50/DDR1_DQ_50 DDR1_DQSN_5/DDR1_DQSN_3 DDR_B_DQS5 DDR_B_DQS#5 <20>
BC34 AP34 BD32 AU30
DDR_A_D52 DDR0_DQ_51/DDR1_DQ_35 DDR0_DQSP_4/DDR1_DQSP_0 DDR_A_DQS#5 DDR_A_DQS4 <19> DDR_B_D52 DDR1_DQ_51/DDR1_DQ_51 DDR1_DQSP_5/DDR1_DQSP_3 DDR_B_DQS#6 DDR_B_DQS5 <20>
BA37 AV34 BA30 BC31
DDR_A_D53 DDR0_DQ_52/DDR1_DQ_36 DDR0_DQSN_5/DDR1_DQSN_1 DDR_A_DQS5 DDR_A_DQS#5 <19> DDR_B_D53 DDR1_DQ_52/DDR1_DQ_52 DDR1_DQSN_6/DDR1_DQSN_6 DDR_B_DQS6 DDR_B_DQS#6 <20>
BA36 AV35 BA29 BC30
DDR_A_D54 DDR0_DQ_53/DDR1_DQ_37 DDR0_DQSP_5/DDR1_DQSP_1 DDR_A_DQS#6 DDR_A_DQS5 <19> DDR_B_D54 DDR1_DQ_53/DDR1_DQ_53 DDR1_DQSP_6/DDR1_DQSP_6 DDR_B_DQS#7 DDR_B_DQS6 <20>

nfi
BC36 BB35 BD29 BH31
DDR_A_D55 DDR0_DQ_54/DDR1_DQ_38 DDR0_DQSN_6/DDR1_DQSN_4 DDR_A_DQS6 DDR_A_DQS#6 <19> DDR_B_D55 DDR1_DQ_54/DDR1_DQ_54 DDR1_DQSN_7/DDR1_DQSN_7 DDR_B_DQS7 DDR_B_DQS#7 <20>
BC37 BB34 BD30 BH30
DDR_A_D56 DDR0_DQ_55/DDR1_DQ_39 DDR0_DQSP_6/DDR1_DQSP_4 DDR_A_DQS#7 DDR_A_DQS6 <19> DDR_B_D56 DDR1_DQ_55/DDR1_DQ_55 DDR1_DQSP_7/DDR1_DQSP_7 DDR_B_DQS7 <20>
BE35 BF34 BG31
DDR_A_D57 DDR0_DQ_56/DDR1_DQ_40 DDR0_DQSN_7/DDR1_DQSN_5 DDR_A_DQS7 DDR_A_DQS#7 <19> DDR_B_D57 DDR1_DQ_56/DDR1_DQ_56 DDR_B_ALERT#
BE34 BF35 BG32 Y29
DDR_A_D58 DDR0_DQ_57/DDR1_DQ_41 DDR0_DQSP_7/DDR1_DQSP_5 DDR_A_DQS7 <19> DDR_B_D58 DDR1_DQ_57/DDR1_DQ_57 NC/DDR1_ALERT# DDR_B_PAR DDR_B_ALERT# <20>
BG35 BK32 AE34
DDR_A_D59 DDR0_DQ_58/DDR1_DQ_42 LPDDR3 / DDR4 DDR_A_ALERT# DDR_B_D59 DDR1_DQ_58/DDR1_DQ_58 NC/DDR1_PAR DDR_B_PAR <20>
BG34 W37 BK31 BU31
DDR_A_D60 DDR0_DQ_59/DDR1_DQ_43 NC/DDR0_ALERT# DDR_A_PAR DDR_A_ALERT# <19> DDR_B_D60 DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET# DDR_DRAMRST# <19,20>
BE37 W31 BG29

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DDR_A_D61 DDR0_DQ_60/DDR1_DQ_44 NC/DDR0_PAR DDR_A_PAR <19> DDR_B_D61 DDR1_DQ_60/DDR1_DQ_60 SM_RCOMP0
BE36 BG30 BN28
DDR_A_D62 BG36 DDR0_DQ_61/DDR1_DQ_45 F36 +0.6V_A_VREFCA DDR_B_D62 BK30 DDR1_DQ_61/DDR1_DQ_61 DDR_RCOMP_0 BN27 SM_RCOMP1
DDR_A_D63 DDR0_DQ_62/DDR1_DQ_46 DDR_VREF_CA +0.6V_A_VREFCA DDR_B_D63 DDR1_DQ_62/DDR1_DQ_62 DDR_RCOMP_1 SM_RCOMP2
BG37 D35 BK29 BN29
DDR0_DQ_63/DDR1_DQ_47 DDR0_VREF_DQ_0 D37 DDR1_DQ_63/DDR1_DQ_63 DDR_RCOMP_2
DDR0_VREF_DQ_1 E36 +0.6V_B_VREFCA
DDR1_VREF_DQ DDR_PG_CTRL +0.6V_B_VREFCA
C35 WHL-U42_BGA1528
DDR_VTT_CTL

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WHL-U42_BGA1528
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3 3

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+1.2V_VDDQ

+3VS #571021 CFL PDG R0.7 p.39 SM_RCOMP0 RC38 1 2 121_0402_1%

SM_RCOMP1 RC39 1 2 80.6_0402_1%
0.1U_0201_10V6K 2 1 CC57 SM_RCOMP2 RC40 1 2 100_0402_1%
2

UC7 RC10
1 5
NC VCC 100K_0402_5% ηϱϳϭϬϮϭ W' W͘ϲϰ
DDR_PG_CTRL 2 tсϭϱ^ƉĂĐĞсϮϬͬϮϱ >сϱϬϬŵŝů
1

A 4
3 Y SM_PG_CTRL <45>
@ESD@
GND DDR_DRAMRST# CC70 1 2 .1U_0402_16V7K
2

74AUP1G07SE-7_SOT353_5P ZͺsddͺEd>ƚŽZ
RC16
@ 1M_0402_5% sddƐƵƉƉůŝĞĚ ƌĂŵƉĞĚ
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4 4

Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(2/12)DDR4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 8 of 57
A B C D E
 A B C D E

+3VS

SOC_SMBCLK_1 RC222 1 2 2.2K_0402_5%

SOC_SMBDATA_1RC223 1 2 2.2K_0402_5%

+3VALW_PRIM

Vinafix.com SOC_SML0CLK

SOC_SML0DATA RC50
RC49 1

1
2 2.2K_0402_5%

2 2.2K_0402_5%
#571021 CFL-U PDG R0.7 p.290
1 change RC49,RC50 to 2.2K 1

SOC_SML1CLK RC267 1 2 2.2K_0402_5%

SOC_SML1DATA RC268 1 2 2.2K_0402_5%
SOC_SMBCLK RC269 1 2 2.2K_0402_5%
SOC_SMBDATA RC270 1 2 2.2K_0402_5%
SPI ROM UC1E
SOC_SPI_CLK CH37 CK14 SOC_SMBCLK +3VS
<37> SOC_SPI_CLK SOC_SPI_SO CF37 SPI0_CLK GPP_C0/SMBCLK CH15 SOC_SMBDATA SMB ;ƚŽZ͕'ƐĞŶƐŽƌͿ
<37> SOC_SPI_SO SOC_SPI_SI SPI0_MISO GPP_C1/SMBDATA SOC_SMBALERT#
CF36 CJ15
<37> SOC_SPI_SI SOC_SPI_IO2 SPI0_MOSI GPP_C2/SMBALERT# @ T239
CF34
SPI0_IO2

5
SOC_SPI_IO3 CG34 SPI - FLASH CH14 SOC_SML0CLK +3VALW_PRIM
^ƚƌĂƉWŝŶ SML0 ;ZĞƐĞƌǀĞͿ

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SOC_SPI_CS#0 CG36 SPI0_IO3 SMBUS , SMLINK GPP_C3/SML0CLK CF15 SOC_SML0DATA QC2B
CG35 SPI0_CS0# GPP_C4/SML0DATA CG15 SOC_SML0ALERT# 4.7K_0402_5% 2 ESPI@ 1 RC202 2N7002KDW_SOT363-6
SOC_SPI_CS#2 CH34 SPI0_CS1# GPP_C5/SML0ALERT#

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<37> SOC_SPI_CS#2 SPI0_CS2# SOC_SML1CLK SOC_SMBCLK SOC_SMBCLK_1
CN15 3 4
SOC_SML1CLK <21,36>

S
#575412 WHL-U schchecklist R0.8 SPI0_CS2# GPP_C6/SML1CLK CM15 SOC_SML1DATA SOC_SMBCLK_1 <19,20,33>
<21,36>SML1

D
GPP_C7/SML1DATA SOC_SML1DATA ;ƚŽ͕dŚĞƌŵĂůƐĞŶƐŽƌͿ

2
Used to select TPM device if it connected to SPI interface CF20 CC34 SOC_SML1ALERT#

G
GPP_D1/SPI1_CLK/BK1/SBK1 GPP_B23/SML1ALERT#/PCHHOT# @ T234
CG22 QC2A
CF22 GPP_D2/SPI1_MISO_IO1/BK2/SBK2 2N7002KDW_SOT363-6
CG23 GPP_D3/SPI1_MOSI_IO0/BK3/SBK3 CA29 LPC_AD0 RC144 1 @ 2 0_0402_5%
^W/ͬ>WƵƐ
SPI Touch CH23 GPP_D21/SPI1_IO2 SPI - TOUCH GPP_A1/LAD0/ESPI_IO0 BY29 LPC_AD1 1 2 LPC_AD0_R <36> SOC_SMBDATA 6 1 SOC_SMBDATA_1
RC145 @ 0_0402_5% ^W/͗нϭ͘ϴs SOC_SMBDATA_1 <19,20,33>

S
CG20 GPP_D22/SPI1_IO3 GPP_A2/LAD1/ESPI_IO1 BY27 LPC_AD2 1 2 LPC_AD1_R <36>
RC146 @ 0_0402_5%

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D
GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
BV27
CA28
LPC_AD3
LPC_FRAME#
RC147 1 @ 2 0_0402_5%
LPC_AD2_R
LPC_AD3_R
<36>
<36> * >W͗нϯ͘ϯs
GPP_A5/LFRAME#/ESPI_CS# CA27 ESPI_RST# LPC_FRAME# <36>
CH7 LPC , ESPI GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <36>
CH8 CL_CLK
CL_DATA C LINK
CH9 BV32 CLKOUT_LPC0 RC45 2 LPC@ 1 22_0402_5%
CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK BV30 CLK_LPC_TPM_R CLK_LPC_EC <36> To EC
RC46 2 TPM@ 1 22_0402_5% +1.8VS_3VS_PGPPA
2 BV29 GPP_A10/CLKOUT_LPC1 BY30 PM_CLKRUN# CLK_LPC_TPM 2
PM_CLKRUN# ηϱϳϬϵϵϬ&>ͲhZZϭ͘ϬƉ͘ϭϯϰ

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EC_SERIRQ BV28 GPP_A0/RCIN#/TIME_SYNC1 GPP_A8/CLKRUN# ŚĂŶŐĞWDͺ><ZhEηWhϴ͘Ϯ<
<36> EC_SERIRQ GPP_A6/SERIRQ PM_CLKRUN#
#575412 WHL-U Schchk R0.8 1 2
LPC Mode change RC45 to 15ohm when use ESPI RC107 8.2K_0402_5%
WHL-U42_BGA1528 EC_SERIRQ 1 2
@ RC112 8.2K_0402_5%
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RC45 ESPI@ ηϱϳϭϬϮϭ&>Ͳh^ĐŚĐŚŬZϬ͘ϳƉ͘ϯϳ

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15_0402_5% ŚĂŶŐĞdWDͺ^Z/ZYWhϴ͘Ϯ<
SD028150A80

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Ğ^W/Žƌ >W
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#575412 WHL-U schchk R0. ϭсĞ^W/ŝƐƐĞůĞĐƚĞĚĨŽƌͲͲх&Žƌ<ϵϬϯϮKŶůLJ͘
50ȍ series resistor: 3.3V UC2
33ȍ series resistor: 1.8V
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VPRO@
SPI ROM ( 16MByte ) +3VALW_SPI CC8 SA0000AV400 d>^ ŽŶĨ ŝ ĚĞŶƚ ŝĂů ŝ ƚLJ
ĐůŽƐĞhϮ 0.1U_0201_10V6K
SOC_SPI_SO RC263 2 1 SOC_SPI_SO_0_R SOC_SPI_CS#0 1
UC2
8
1 2 * Ϭ с ŝƐĂďůĞ /ŶƚĞů D ƌLJƉƚŽ dƌĂŶƐƉŽƌƚ >ĂLJĞƌ ^ĞĐƵƌŝƚLJ

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51_0402_5%
SOC_SPI_SI RC264 2 1 51_0402_5% SOC_SPI_SI_0_R SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R ;d>^Ϳ ĐŝƉŚĞƌ ƐƵŝƚĞ ;ŶŽ ĐŽŶĨ ŝ ĚĞŶƚ ŝĂů ŝ ƚLJͿ͘
SOC_SPI_CLK RC265 SOC_SPI_CLK_0_R SOC_SPI_IO2_0_R DO(IO1) /HOLD(IO3) SOC_SPI_CLK_0_R
SOC_SPI_IO3 RC266
2
2
1
1
51_0402_5%
SOC_SPI_IO3_0_R
3
4 /WP(IO2) CLK
6
5 SOC_SPI_SI_0_R
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51_0402_5%
3 GND DI(IO0) DƵƐƚ ďĞ ƉƵůůĞĚ ƵƉ ƚŽ ƐƵƉƉŽƌƚ /ŶƚĞů Dd ǁŝƚŚ d>^ ĂŶĚ /ŶƚĞů 3
128M XM25QH128AHIG SOP 8P
SA0000B8400 Main
ϮϬϭϱDKtϬϲŶŽŶĞĞĚWhϭ<ŽŶ^W/ͺ/KϮͬ/Kϯ ^ ;^ŵĂůů ƵƐŝŶĞƐƐ ĚǀĂŶƚĂŐĞͿ ǁŝƚŚ d>^͘
source: XMC

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+3VALW_SPI

SOC_SPI_CLK_0_R 1 @EMI@ 2 1 2
RC24 0_0402_5% CC9 @EMI@ SOC_SPI_IO2 RC47 1 @ 2 1K_0402_1%
10P_0402_50V8J
SOC_SPI_IO3 RC48 1 @ 2 1K_0402_1%
SOC_SPI_IO2 2 1 SOC_SPI_IO2_0_R
RC52 51_0402_5%

4 4

Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(3/12)SPI,ESPI,SMB,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 9 of 57
A B C D E
 A B C D E

ĨŽƌW,ůĞĂŬĂŐĞǀŽůƚĂŐĞŝƐƐƵĞ
HDA_SDIN0
ME_EN
HDA_SYNC_R

Vinafix.com
2

2
RC304 RC303 RC305
499_0402_1% 499_0402_1% 499_0402_1%
1 @ @ @ 1
1

1
UC1G
,ĨŽƌh/K HDA_SYNC
HDA_BIT_CLK
BN34
HDA_SYNC/I2S0_SFRM
BN37 CH36
HDA_SDOUT BN36 HDA_BCLK/I2S0_SCLK AUDIO SDIO / SDXC GPP_G0/SD_CMD CL35
HDA_SDIN0 HDA_SDIN0 BN35 HDA_SDO/I2S0_TXD GPP_G1/SD_DATA0 CL36
<32> HDA_SDIN0 HDA_SDI0/I2S0_RXD GPP_G2/SD_DATA1
BL36 CM35
HDA_RST# BL35 HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G3/SD_DATA2 CN35
RC271 1 2 33_0402_5% HDA_BIT_CLK CK23 HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G4/SD_DATA3 CH35

Co
<32> HDA_BIT_CLK_R HDA_SDOUT GPP_D23/I2S_MCLK GPP_G5/SD_CD#
RC272 1 2 33_0402_5% /Ϯ^ͺD>< ŝŶƚĞƌŶĂů ƉƵͲĚŽǁŶ CK36
<32> HDA_SDOUT_R HDA_SYNC GPP_G6/SD_CLK
RC273 1 2 33_0402_5% BL37 CK34
<32> HDA_SYNC_R HDA_RST# I2S1_SFRM/SNDW2_CLK GPP_G7/SD_WP
RC274 1 2 33_0402_5% BL34
<32> HDA_RST#_R I2S1_TXD/SNDW2_DATA

CNV_RF_RESET# CJ32
2 1 <31> CNV_RF_RESET# CH32 GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
<36> ME_EN @
RC77 0_0402_5% CLKREQ_CNV# CH29 GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

mp
<31> CLKREQ_CNV# CH30 GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ BW36
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7 BY31
,ͺ^Kͬ/Ϯ^ͺdyϬ;/ŶƚĞƌŶĂůWƵůůŽǁŶͿ͗ PCH_DMIC_CLK CP24 GPP_A16/SD_1P8_SEL
;^ĂŵƉůĞĚ͗ZŝƐŝŶŐĞĚŐĞŽĨW,ͺWtZK<Ϳ <32> PCH_DMIC_CLK PCH_DMIC_DATA GPP_D19/DMIC_CLK0/SNDW4_CLK
CN24 RC76
<32> PCH_DMIC_DATA GPP_D20/DMIC_DATA0/SNDW4_DATA
&ůĂƐŚĞƐĐƌŝƉƚŽƌ^ĞĐƵƌŝƚLJKǀĞƌƌŝĚĞ SD_1P8_RCOMP
CK33 200_0402_1%
PCH_DMIC_CLK1 CK25 CM34 RCOMP 2 1
ϬсŶĂďůĞƐĞĐƵƌŝƚLJŵĞĂƐƵƌĞƐĚĞĨ ŝ ŶĞĚŝ Ŷ ƚ ŚĞ &ů ĂƐ Ś <32> PCH_DMIC_CLK1 PCH_DMIC_DATA1CJ25 GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
2 ĞƐĐƌŝƉƚŽƌ͘ <32> PCH_DMIC_DATA1 GPP_D18/DMIC_DATA1/SNDW3_DATA 2
ηϱϳϭϬϮϭ&>ͲhW'Zϭ͘ϬƉ͘ϯϵ

al
ϭсŝƐĂďůĞ&ůĂƐŚĞƐĐƌŝƉƚŽƌ^ĞĐƵƌŝƚLJ;ŽǀĞƌƌŝĚĞͿ͘dŚŝƐ <32> PCH_SPKR
PCH_SPKR CF35
ƐƚƌĂƉƐŚŽƵůĚŽŶůLJďĞĂƐƐĞƌƚĞĚŚŝŐŚƵƐŝŶŐĞdžƚĞƌŶĂů GPP_B14/SPKR ^ͺϭWϴͺZKDW͕ ^ͺϯWϯͺZKWD͕ DDͺZKDW
WHL-U42_BGA1528 ĐĂŶďĞŵĂƌŐĞĚŝŶƚŽŽŶĞϮϬϬŽŚŵнͬͲϭй
@
ƉƵůůͲƵƉ ŝŶ ŵĂŶƵĨĂĐƚƵƌŝŶŐͬĚĞďƵŐ ĞŶǀŝƌŽŶŵĞŶƚƐ KE>z͘ 7 of 20

^W<Z ͬ 'WWͺϭϰ ;/ŶƚĞƌŶĂů WƵůů ŽǁŶͿ͗

;^ĂŵƉůĞĚ͗ZŝƐŝŶŐ ĞĚŐĞ ŽĨ W,ͺWtZK<Ϳ
Co +3VALW_PRIM

1
UC1I
dKW ^ǁĂƉ KǀĞƌƌŝĚĞ CNV_PRX_DTX_N0 CPU_C10_GATE#
RC133

nfi
CR30 CNVio CN27 UMA@ 10K_0402_5%
* ϬсŝƐĂďůĞdKW^ǁĂƉŵŽĚĞ͘ <31>
<31>
CNV_PRX_DTX_N0
CNV_PRX_DTX_P0
CNV_PRX_DTX_P0 CP30 CNV_WR_D0N
CNV_WR_D0P
GPP_H18/CPU_C10_GATE#
CM27
@ T275

ϭсŶĂďůĞdKW ^ǁĂƉ DŽĚĞ͘

2
CNV_PRX_DTX_N1 CM30 GPP_H19/TIMESYNC_0
<31> CNV_PRX_DTX_N1 CNV_PRX_DTX_P1 CN30 CNV_WR_D1N CF25 XTAL_FREQ_SELECT DGPU_PRSNT#
<31> CNV_PRX_DTX_P1 CNV_PTX_DRX_N0 CN32 CNV_WR_D1P GPP_H21/XTAL_FREQ_SELECT CN26
<31> CNV_PTX_DRX_N0 CNV_PTX_DRX_P0 CNV_WT_D0N GPP_H22 GPP_H23
CM32 CM26

de
<31> CNV_PTX_DRX_P0 CNV_WT_D0P GPP_H23 @ T276 +3VALW_DSW
CK17
/ŶƚĞů,ƵĚŝŽůŝŶŬĐĂƉĂďŝůŝƚ ŝ ĞƐ GPP_F10

1
CNV_PTX_DRX_N1 CP33
хdǁŽ^/ƐŝŐŶĂůƐƚŽƐƵƉƉŽƌƚƚǁŽĞdžƚĞƌŶĂůĐŽĚĞĐƐ͘ <31> CNV_PTX_DRX_N1 CNV_PTX_DRX_P1 CN33 CNV_WT_D1N BV35 GPD7 1 2 RC134
<31> CNV_PTX_DRX_P1 CNV_WT_D1P GPD7
хƌŝǀĞƌƐǀĂƌŝĂďůĞƌĞƋƵĞŶĐLJ;ϱD,njƚŽ ϮϰD,njͿ >< ƚŽ ƐƵƉƉŽƌƚ͗ CN20 RC259 100K_0402_5% VGA@ 10K_0402_5%
CLK_CNV_PRX_DTX_N CN31 GPP_F3
ͲͲ^KĚŽƵďůĞƉƵŵƉĞĚƵƉƚŽϰϴDďͬƐ <31> CLK_CNV_PRX_DTX_N CLK_CNV_PRX_DTX_P CNV_WR_CLKN DGPU_PRSNT#
ηϱϳϬϵϵϬ&>ͲhZZϭ͘Ϭ
'Wϳ ;džƚĞƌŶĂů ƉƵůůͲƵƉ ŝƐ ƌĞƋƵŝƌĞĚͿ
CP31 CG25
ͲͲ^/ΖƐƐŝŶŐůĞƉƵŵƉĞĚƵƉƚŽϮϰDďͬƐ <31> CLK_CNV_PRX_DTX_P

2
CLK_CNV_PTX_DRX_N CNV_WR_CLKP GPP_D4/IMGCLKOUT0/BK4/SBK4 yd> /EWhd DK
CP34 CH25

nti
<31> CLK_CNV_PTX_DRX_N ,/',͗yd> ŝƐ Ăƚ ƚ ĂĐŚĞĚ
хWƌŽǀŝĚĞƐĐĂĚĞŶĐĞĨŽƌϰϰ͘ϭŬ,njďĂƐĞĚƐĂŵƉůĞƌĂƚĞŽƵƚƉƵƚ͘ CLK_CNV_PTX_DRX_P CN34 CNV_WT_CLKN GPP_H20/IMGCLKOUT_1
<31> CLK_CNV_PTX_DRX_P CNV_WT_CLKP
х ^ƵƉƉŽƌƚ ϭ͘ϱs͕ ϭ͘ϴs͕ ĂŶĚ ϯ͘ϯs ŵŽĚĞƐ͘ GPP_F12/EMMC_DATA0
CR20
1 2 CNV_WT_RCOMP CP32 CM20
3 RC254 150_0402_1% CR32 CNV_WT_RCOMP_0 GPP_F13/EMMC_DATA1 CN19 3
CP20 CNV_WT_RCOMP_1 EMMC GPP_F14/EMMC_DATA2 CM19
GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3
DGPU_PRSNT#
CN18

al
CK19 GPP_F16/EMMC_DATA4 CR18
CG17 GPP_F1 GPP_F17/EMMC_DATA5 CP18
DIS,Optimus 0
GPP_F2 GPP_F18/EMMC_DATA6 CM18
0_0402_5%2 @ 1 RC230 CR14 GPP_F19/EMMC_DATA7 UMA 1
<21,36,43> DGPU_AC_DETECT CP14 GPP_C8/UART0_RXD
GPU_EVENT# 2 @ 1 GPU_EVENT_R# CN14 GPP_C9/UART0_TXD CM16
<21> GPU_EVENT# CM14 GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK CP16
0_0402_5% RC204
GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK CR16
CJ17 GPP_F11/EMMC_CMD CN16
CH17 GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET# +3VALW_PRIM
GPP_F9/CNV_MFUART2_TXD CK15 RCOMP
1 2 A4WP_PRESENT CF17 EMMC_RCOMP
GPP_F23/A4WP_PRESENT

1
RC262 10K_0402_5% ηϱϳϭϬϮϭ&>ͲhW'Zϭ͘ϬƉ͘ϯϵ
/Ed>ͺDy ƌĞĐŽŵŵĞŶĚ ƚŽ ŵŽƵŶƚ W ϭϬ<
WHL-U42_BGA1528 ^ͺϭWϴͺZKDW͕ ^ͺϯWϯͺZKWD͕ DDͺZKDW RC256
@ ĐĂŶďĞŵĂƌŐĞĚŝŶƚŽŽŶĞϮϬϬŽŚŵϭй 4.7K_0402_5%
9 of 20

2
XTAL_FREQ_SELECT

2
RC258
@ 20K_0402_5%

1
ηϱϳϬϵϵϬ&>ͲhZZϭ͘Ϭ
yd>ͺ&ZYͺ^>d
>Kt͗ ϯϴ͘ϰͬϭϵ͘ϮD,nj
4
,/',͗ ϮϰD,nj 4

Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(4/12)HDA,EMMC,SDIO,CNVI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 10 of 57
A B C D E
 A B C D E

#571021 CFL-U PDG R0.7 p.256 SOC_XTAL24_IN RC235 1 2 33_0402_1% SOC_XTAL24_IN_R

+RTCVCC

RC91 1

1 2
2 20K_0402_5% SOC_SRTCRST#
Vinafix.com SOC_XTAL24_OUT RC236 1

563377 Intel MOW 33

2 33_0402_1% SOC_XTAL24_OUT_R 1
RC92
2
1M_0402_5%

CC10 1U_0201_6.3V6M YC1

1 RC93 1 2 20K_0402_5% SOC_RTCRST# 24MHZ_18PF_XRCGB24M000F2P51R0 1
SOC_RTCRST# <36>
1 2 UC1J 3 1
CC11 1U_0201_6.3V6M 3 1
CLK_PCIE_N0 CLOCK SINGNALS CLK_CPU_ITP# NC NC
JCMOS1 1 @ 2 0_0603_5% CLR CMOS AW2 AU1 T164 @ 1 1
<21> CLK_PCIE_N0 CLK_PCIE_P0 AY3 CLKOUT_PCIE_N_0 CLKOUT_ITPXDP_N AU2 CLK_CPU_ITP
DGPU <21> CLK_PCIE_P0 CLKREQ_PCIE#0 CLKOUT_PCIE_P_0 CLKOUT_ITPXDP_P T165 @ 4 2
Place at RAM DOOR CF32
<21> CLKREQ_PCIE#0 GPP_B5/SRCCLKREQ0# BT32 SUSCLK CC12 CC13
CLK_PCIE_N1 BC1 GPD8/SUSCLK SUSCLK <31> 2 2
<30,38> CLK_PCIE_N1 CLK_PCIE_P1 BC2 CLKOUT_PCIE_N_1 CK3 SOC_XTAL24_IN
GLAN <30,38> CLK_PCIE_P1 CLKREQ_PCIE#1 CLKOUT_PCIE_P_1 XTAL_IN SOC_XTAL24_OUT
27P_0402_50V8J 27P_0402_50V8J
CE32 CK2
SM_INTRUDER# <30,38> CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# XTAL_OUT
RC941 2 1M_0402_5%
CLK_PCIE_N2 BD3 CJ1 XCLK_BIASREF
<31> CLK_PCIE_N2 CLK_PCIE_P2 BC3 CLKOUT_PCIE_N_2 XCLK_BIASREF CM3
WLAN <31> CLK_PCIE_P2 CLKREQ_PCIE#2 CLKOUT_PCIE_P_2 CLKIN_XTAL REFCLK_CNV <31>
CF30
+3VS <31> CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# SOC_RTCX1
BN31
CLK_PCIE_N3 BH3 RTCX1 BN32 SOC_RTCX2

Co
<31> CLK_PCIE_N3 CLKOUT_PCIE_N_3 RTCX2

1
1 2 10K_0402_5% CLKREQ_PCIE#1 CLK_PCIE_P3 BH4
RC121 M.2/SSD <31> CLK_PCIE_P3 CLKREQ_PCIE#3 CLKOUT_PCIE_P_3 SOC_SRTCRST# &ŽůůŽǁ ϮϬϭϰDKtϰϴ
CE31 BR37 RC255
CLKREQ_PCIE#0 <31> CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3# SRTCRST# SOC_RTCRST# ^ŬLJůĂŬĞhWhϮ͘ϳŬŽŚŵƚŽϭs
R115 1 2 10K_0402_5% BR34 10K_0402_5%
BA1 RTCRST# ĂŶŶŽŶůĂŬĞhWϲϬ͘ϰŽŚŵ
BA2 CLKOUT_PCIE_N_4 +1.05VALW_CLK5_F24NS

2
CLKREQ_PCIE#4 CE30 CLKOUT_PCIE_P_4
RC282 2 1 10K_0402_5% CLKREQ_PCIE#5 GPP_B9/SRCCLKREQ4# XCLK_BIASREF RC96 1 @ 2 2.7K_0402_1%
RC281 2 1 10K_0402_5% CLKREQ_PCIE#4 BE1

mp
RC280 2 1 10K_0402_5% CLKREQ_PCIE#3 BE2 CLKOUT_PCIE_N_5
RC279 2 1 10K_0402_5% CLKREQ_PCIE#2 CLKREQ_PCIE#5 CF31 CLKOUT_PCIE_P_5 RC136 1 2 60.4_0402_1%
GPP_B10/SRCCLKREQ5#
WHL-U42_BGA1528
10 of 20
@
+3VALW_PRIM y><ͺ/^Z&
+1.05V_VCCST d͗ϱϬŽŚŵ ^͗ϭϮͬϭϱ >͗ϭϬϬϬ sŝĂ͗Ϯ
2 EXT_PWR_GATE# 100K_0402_5% 1 2 RC295 2

al
PM_SLP_S0# 100K_0402_5% 1 2 RC296
&ƌŽŵ ;ŽƉĞŶͲĚƌĂŝŶͿ
1

RC113
1K_0402_5% PM_SLP_S3# 100K_0402_5% 1 2 RC297
PM_SLP_S4# 100K_0402_5% 1 2 RC298
RC116 PM_SLP_A# 100K_0402_5% 1 2 RC299
ϮϬϭϰDKtϰϴ͗
60.4_0402_1% SLP_WLAN# 100K_0402_5% 1 2 RC300 ^ŬLJůĂŬĞͲhƵƐĞϮϰDϱϬŽŚŵ^Z
2

1 2 EC_VCCST_PG SLP_SUS# 1 2 ĂŶŶŽŶůĂŬĞhƵƐĞϯϴ͘ϰDϯϬŽŚŵ^Z

Co
100K_0402_5% RC301
<36,40> EC_VCCST_PG_R SLP_LAN# 1 2
100K_0402_5% RC302
SOC_RTCX2
/Ed>t,>Ͳh ^ĐŚĐŚĞĐŬůŝƐƚ ZϬ͘ϵ

UC1K SOC_RTCX1 1 2
RC98 10M_0402_5%
PM_SLP_S0#

nfi
SYSTEM POWER MANAGEMENT BJ37
PLT_RST# BJ35 GPP_B12/SLP_S0# BU36 PM_SLP_S3# PM_SLP_S0# <36,37>
<36,37> PLT_RST# SYS_RESET# CN10 GPP_B13/PLTRST# GPD4/SLP_S3# BU27 PM_SLP_S4# PM_SLP_S3# <36,40>
+3VALW_PRIM EC_RSMRST# BR36 SYS_RESET# GPD5/SLP_S4# BT29 PM_SLP_S5# PM_SLP_S4# <36,40>
<36> EC_RSMRST# @ T84 YC2
RSMRST# GPD10/SLP_S5# 1 2
+3VALW_DSW RC277 2 1 10K_0402_5% SYS_RESET# H_CPUPWRGD AR2 BU29 SLP_SUS#
T95 @ EC_VCCST_PG PROCPWRGD SLP_SUS# SLP_LAN# @ T90
BJ2 BT31 32.768KHZ_9PF_X1A000141000200

de
LAN_WAKE# VCCST_PWRGOOD SLP_LAN# SLP_WLAN# @ T87
RC278 2 1 10K_0402_5% BT30 Change PN to SJ10000Q400
T89 @ SYS_PWROK GPD9/SPL_WLAN# PM_SLP_A# SLP_WLAN# <36>
CR10 BU37 1 1
<36,40> SYS_PWROK PCH_PWROK_R SYS_PWROK GPD6/SLP_A# PM_SLP_A# <36>
1 2 BP31 CC15 CC16
PCH_PWROK <36,40> PCH_PWROK PCH_DPWROK PCH_PWROK PBTN_OUT#_R
RC275 2 1 10K_0402_5% RC20 BP30 BU28 8.2P_50V_0402 8.2P_ 50V_0402
10_0402_5% DSW_PWROK GPD3/PWRBTN# BU35 AC_PRESENT
EC_RSMRST# GPD1/ACPRESENT PM_BATLOW# AC_PRESENT <36> 2 2
RC276 2 1 10K_0402_5% SUSPWRDNACK BV34 BV36
<36> SUSPWRDNACK BY32 GPP_A13/SUSWARN#/SUSPWRDACK GPD0/BATLOW#
SUSACK#

nti
T92 @ GPP_A15/SUSACK#
WAKE# BU30 BR35 SM_INTRUDER#
RC110 2 1 10K_0402_5% SYS_PWROK LAN_WAKE# BU32 WAKE# INTRUDER#
3 BU34 GPD2/LAN_WAKE# CC37 EXT_PWR_GATE# 3
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# SOC_VRALERT# @ T93
CC36
GPP_B2/VRALERT#

al
BT27 INPUT3VSEL +3VALW_DSW
INPUT3VSEL
PBTN_OUT#_R RC111
W,ŝŶƚĞƌŶĂůWh
1 @ 2 100K_0402_5%

+3VALW_DSW WHL-U42_BGA1528
AC_PRESENT RC106
ŝŶƚĞƌŶĂůWh
1 @ 2 10K_0402_5%
@ 11 of 20
RC104 1 2 1K_0402_5% WAKE#

ηϱϳϱϰϭϮ t,>Ͳh ƐĐŚĐŚĞĐŬůŝƐƚ ZϬ͘ϴ PM_BATLOW# RC103 1 2 10K_0402_5%

ϭ<ŽŚŵƉƵůůͲƵƉƚŽs^tͺϯƉϯ͘
dŚĞƉƵůůͲƵƉŝƐƌĞƋƵŝƌĞĚĞǀĞŶŝĨW/ĞΎŝŶƚĞƌĨĂĐĞ
ŝƐŶŽƚƵƐĞĚŽŶƚŚĞƉůĂƚ Ĩ Žƌ ŵ
͘
+3VALW_PRIM

  —ˆˆ‡” SOC_VRALERT# RC115

ĞĨĂƵůƚ͗'W/
2 @ 1 10K_0402_5%

ESD@ 1000P_0402_50V7K +3VS

2 1 CC131 EC_VCCST_PG
+3VALW_DSW
@ESD@ 5
CC51 2 1 .1U_0402_16V7K SYS_RESET# 2 @ 1 PBTN_OUT#_R PLT_RST# 2 P
<36> PBTN_OUT# B

1
RC109 0_0402_5% 4 PLT_RST_BUF#
1 Y PLT_RST_BUF# <21,30,31,38>
ESD@ 1000P_0402_50V7K
A
G

1
2 1 CC50 H_CPUPWRGD EC_RSMRST# 2 @ 1 PCH_DPWROK @ @ RC260
RC114 0_0402_5% UC3 RC118 4.7K_0402_5%
3

ESD@ MC74VHC1G08DFT2G_SC70-5 100K_0402_5%

2
CC66 2 1 .1U_0402_16V7K SYS_PWROK SYS_PWROK 2 @ 1 PCH_PWROK PLT_RST_BUF# INPUT3VSEL
RC122 0_0402_5% 1
2

1
ESD@ 1000P_0402_50V7K 2 @ 1
4 2 1 CC65 PCH_PWROK_R RC125 0_0402_5% CC130 ηϱϳϬϵϵϬ&>ͲhZZϭ͘Ϭ 4
100P_0402_50V8J /EWhdϯs^> RC261
2 ESD@ >͗ƐƵƉƉůLJŝƐϯ͘ϯsнͲϱй
ESD@ ,͗ƐƵƉƉůLJŝƐϯ͘ϬsнͲ ϱй 4.7K_0402_5%
CC69 2 1 .1U_0402_16V7K EC_RSMRST#

2
Reserved for ESD place near UC2.1

ηϱϰϯϬϭϲ W'Ϯ͘Ϭ W͘ϱϵϵ

Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
WZKWtZ'ŝƐƵƐĞĚŽŶůLJĨŽƌƉŽǁĞƌƐĞƋƵĞŶĐĞ Issued Date Deciphered Date
ĚĞďƵŐĂŶĚŝƐŶŽƚƌĞƋƵŝƌĞĚƚŽďĞĐŽŶŶĞĐƚĞĚƚŽ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(5/12)CLK,GPIO
ĂŶLJƚŚŝŶŐŽŶƚŚĞƉůĂƚ Ĩ Žƌ ŵ
͘ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 11 of 57
A B C D E
 A B C D E

+3VALW_PRIM

1
RC215
10K_0402_5%
UC1F
+3VS
Vinafix.com

2
TS_EN CC27
<28,36> TS_EN 2 1 PIRQA# CC32 GPP_B15/GSPI0_CS0# CN22 CPU_ID
#575412 WHL-U schchecklist R0.8 RC135 10K_0402_5% CE28 GPP_A7/PIRQA#/GSPI0_CS1# GPP_D9/ISH_SPI_CS#/GSPI2_CS0# CR22 CPU_ID
GPP_B16/GSPI0_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK

1
1 PIRQA# PU 8.2K~10K to +3.3VS GC6_FB_EN CE27 CM22 PROJECT_ID0 1

@ T111
GSPI0_MOSI CE29 GPP_B17/GSPI0_MISO ISH GPP_D11/ISH_SPI_MISO/GSPI2_MISO CP22 PROJECT_ID1 CPU_ID RC214
GPP_B18/GSPI0_MOSI GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
CA31 CK22 WHL 1 10K_0402_5%
@
CA32 GPP_B19/GSPI1_CS0# GPP_D5/ISH_I2C0_SDA CH20
reserved 0

2
CC29 GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN# GPP_D6/ISH_I2C0_SCL
CC30 GPP_B20/GSPI1_CLK CH22
GSPI1_MOSI CA30 GPP_B21/GSPI1_MISO GPP_D7/ISH_I2C1_SDA CJ22
@ T112 GPP_B22/GSPI1_MOSI GPP_D8/ISH_I2C1_SCL
CNV_BRI_PRX_DTX CK20 +3VALW_PRIM
<31> CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX CG19 GPP_F5/CNV_BRI_RSP CJ27 I2C_5_SDA
<31> CNV_RGI_PTX_DRX CNV_BRI_PTX_DRX GPP_F6/CNV_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA I2C_5_SCL T105 @
CJ20 CJ29
<31> CNV_BRI_PTX_DRX CNV_RGI_PRX_DTX CH19 GPP_F4/CNV_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL T106 @ no use PROJECT_ID0 RC207 2 @ 1 10K_0402_5%
<31> CNV_RGI_PRX_DTX GPP_F7/CNV_RGI_RSP CM24 1 2 10K_0402_5%
RC210
GPP_D13/ISH_UART0_RXD CN23
UART_2_CRXD_DTXD CR12 GPP_D14/ISH_UART0_TXD CM23
<31> UART_2_CRXD_DTXD UART_2_CTXD_DRXD CP12 GPP_C20/UART2_RXD GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# CR24 PROJECT_ID1 2 1 10K_0402_5%
RC211 @

Co
<31> UART_2_CTXD_DRXD UART_2_CRTS_DCTS CN12 GPP_C21/UART2_TXD GPP_D16/ISH_UART0_CTS#/SML0BALERT# 1 2 10K_0402_5%
RC213
UART_2_CCTS_DRTS CM12 GPP_C22/UART2_RTS# CG12 DGPU_PWR_EN
GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD CH12 DGPU_HOLD_RST# DGPU_PWR_EN <22,40>
I2C_0_SDA CM11 I2C , UART GPP_C13/UART1_TXD/ISH_UART1_TXD CF12 DGPU_HOLD_RST# <21>
I2C_0_SCL CN11 GPP_C16/I2C0_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS# CG14
GPP_C17/I2C0_SCL GPP_C15/UART1_CTS#/ISH_UART1_CTS#
I2C_1_SDA CK12 BW35
<37> I2C_1_SDA I2C_1_SCL CJ12 GPP_C18/I2C1_SDA GPP_A18/ISH_GP0 BW34

mp
фdŽƵĐŚWх <37> I2C_1_SCL GPP_C19/I2C1_SCL GPP_A19/ISH_GP1 CA37 G_INT# Project_ID1 Project_ID0
no use
I2C_2_SDA CF27 GPP_A20/ISH_GP2 CA36 TPM_PIRQ# G_INT# <33> Project ID
T135
T134
@
@
I2C_2_SCL CF29 GPP_H4/I2C2_SDA GPP_A21/ISH_GP3 CA35
TPM_PIRQ# <37> GPP_D12 GPP_D11
GPP_H5/I2C2_SCL GPP_A22/ISH_GP4 CA34
I2C_3_SDA CH27 GPP_A23/ISH_GP5 BW37 GPP_A12 * EH5AW 0 0
no use T131 @ I2C_3_SCL CH28 GPP_H6/I2C3_SDA GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF# T277 @
T130 @ GPP_H7/I2C3_SCL Reserved 0 1
2 I2C_4_SDA CJ30 2
no use T128 @ Reserved 1 0

al
I2C_4_SCL CJ31 GPP_H8/I2C4_SDA
T129 @ GPP_H9/I2C4_SCL
WHL-U42_BGA1528 Reserved 1 1
@
6 of 20
+3VS

Co
+1.8VALW_PRIM
1 2 UART_2_CRXD_DTXD
RC62 49.9K_0402_1%
1 2 UART_2_CTXD_DRXD RC2501 CNVI@ 2 20K_0402_1% CNV_BRI_PRX_DTX
RC63 49.9K_0402_1%
1 @ 2 UART_2_CRTS_DCTS RC2511 CNVI@ 2 20K_0402_1% CNV_RGI_PRX_DTX
RC64 49.9K_0402_1%
2 UART_2_CCTS_DRTS

nfi
1 @ #570990 CFL U ORB R1.0 p.114
PU 20K
RC65 49.9K_0402_1%

+3VS
+1.8VALW_PRIM Voltage level – 1.8V only

de
M.2 CNV Mode Select +1.8VS_3VS_PGPPA +1.8VS
+3VALW_PRIM
RC177
RC252 2 1 20K_0402_5% CNV_RGI_PTX_DRX 0_0402_5%2 ESPI@ 1
+3VS

I2C_0_SDA
STRAP
1 2 1K_0402_5% 2 1 4.7K_0402_5% 2 LPC@ 1

nti
RC126 @ RC253
RC127 1 @ 2 1K_0402_5% I2C_0_SCL @ RC178 0_0402_5%

RC128 1 2 2.2K_0402_5% I2C_1_SDA An external pull-up or pull-down is required.

3 RC129 1 2 2.2K_0402_5% I2C_1_SCL 0 = Integrated CNVi enable. 3
1 = Integrated CNVi disable.
Note: When a RF companion chip is connected to the

al
PCH CNVi interface, the device internal pulldown
resistor will pull the strap load to enable
CNVi interface.

+3VS

DGPU_PWR_EN RC231 1 VGA@ 2 10K_0402_5%

DGPU_HOLD_RST# RC219 1 VGA@ 2 10K_0402_5%

—…–‹‘ƒŽ–”ƒ’‡ˆ‹‹–‹‘• GC6_FB_EN GC6_FB_EN3V3

2 @ 1

Ͳ̴Ȁ
̴ͳͺȋ–‡”ƒŽ—ŽŽ‘™Ȍǣ RC195 0_0402_5%
GC6_FB_EN3V3 <21>

ȋ‹•‹‰‡†‰‡‘ˆ̴Ȍ
‘‡„‘‘–

* Ͳα‹•ƒ„Ž‡‘‡„‘‘–‘†‡ǤǦǦεͲͷ•‡
ͳᐃ„Ž‡‘‡„‘‘–‘†‡Ǥȋ™‹ŽŽ†‹•ƒ„Ž‡–Š‡
4
‹‡”•›•–‡”‡„‘‘–ˆ‡ƒ–—”‡ȌǤŠ‹•ˆ—…–‹‘‹•—•‡ˆ—Ž 4

™Š‡”—‹‰ȀǤ
'^W/ϭͺDK^/ ͬ 'WWͺϮϮ ;/ŶƚĞƌŶĂů WƵůů ŽǁŶͿ͗
;ZŝƐŝŶŐ ĞĚŐĞ ŽĨ W,ͺWtZK<Ϳ
Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
ŽŽƚ /K^ ^ƚƌĂƉ ŝƚ Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

* Ϭс^W/DŽĚĞͲͲхyϬϱhƐĞ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(6/12)GPIO
Size Document Number R ev
ϭс>WDŽĚĞ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 12 of 57
A B C D E
 A B C D E

for RTS5227
PCIE_CTX_DRX_P5
<38> PCIE_CTX_DRX_P5 PCIE_CTX_DRX_N5
<38> PCIE_CTX_DRX_N5

<21> PCIE_CRX_GTX_N1
Vinafix.com PCIE_CRX_GTX_N1 BW9
UC1H
PCIE1_RXN/USB31_1_RXN
CB5
CB6
USB3_CRX_DTX_N1
USB3_CRX_DTX_P1
<35>
<35>
PCIE_CRX_GTX_P1 BW8 PCIE5_RXN/USB31_5_RXN PCIE1_RXP/USB31_1_RXP CA4
1 <21> PCIE_CRX_GTX_P1
2 0.22U_0402_16V7K PCIE_CTX_GRX_N1 BW4 PCIE5_RXP/USB31_5_RXP PCIE / USB3.1 / SATA PCIE1_TXN/USB31_1_TXN CA3 USB3_CTX_DRX_N1 <35> USB3 MB 1
<21> PCIE_CTX_C_GRX_N1 CC17 VGA@1
2 0.22U_0402_16V7K PCIE_CTX_GRX_P1 BW3 PCIE5_TXN/USB31_5_TXN PCIE1_TXP/USB31_1_TXP USB3_CTX_DRX_P1 <35>
<21> PCIE_CTX_C_GRX_P1 CC21 VGA@1
PCIE5_TXP/USB31_5_TXP BY8
PCIE_CRX_GTX_N2 PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN USB3_CRX_DTX_N2 <34>
BU6 BY9
<21> PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE6_RXN/USB31_6_RXN PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP USB3_CRX_DTX_P2 <34>
BU5 CA2
<21> PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE6_RXP/USB31_6_RXP PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN USB3_CTX_DRX_N2 <34>
CC18 VGA@1 2 0.22U_0402_16V7K BU4 CA1
<21> PCIE_CTX_C_GRX_N2 PCIE_CTX_GRX_P2 PCIE6_TXN/USB31_6_TXN PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP USB3_CTX_DRX_P2 <34>
CC19 VGA@1 2 0.22U_0402_16V7K BU3
<21> PCIE_CTX_C_GRX_P2 PCIE6_TXP/USB31_6_TXP BY7
USB TypeC
DGPU PCIE_CRX_GTX_N3 PCIE3_RXN/USB31_3_RXN USB3_CRX_DTX_N3 <34>
BT7 BY6
<21> PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE7_RXN PCIE3_RXP/USB31_3_RXP USB3_CRX_DTX_P3 <34>
BT6 BY4
<21> PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE7_RXP PCIE3_TXN/USB31_3_TXN USB3_CTX_DRX_N3 <34>
CC20 VGA@1 2 0.22U_0402_16V7K BU2 BY3
<21> PCIE_CTX_C_GRX_N3 2 0.22U_0402_16V7K PCIE_CTX_GRX_P3 BU1 PCIE7_TXN PCIE3_TXP/USB31_3_TXP USB3_CTX_DRX_P3 <34>
CC22 VGA@1
<21> PCIE_CTX_C_GRX_P3 PCIE7_TXP BW6
PCIE_CRX_GTX_N4 BU9 PCIE4_RXN/USB31_4_RXN BW5
<21> PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 PCIE8_RXN PCIE4_RXP/USB31_4_RXP
BU8 BW2
<21> PCIE_CRX_GTX_P4 PCIE_CTX_GRX_N4 PCIE8_RXP PCIE4_TXN/USB31_4_TXN
CC23 VGA@1 2 0.22U_0402_16V7K BT4 BW1
<21> PCIE_CTX_C_GRX_N4 2 0.22U_0402_16V7K PCIE_CTX_GRX_P4 BT3 PCIE8_TXN PCIE4_TXP/USB31_4_TXP
CC24 VGA@1

Co
<21> PCIE_CTX_C_GRX_P4 PCIE8_TXP CE3 USB20_N1
PCIE_CRX_DTX_N5 BP5 USB2_1N CE4 USB20_P1 USB20_N1 <35>
<30,38> PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 BP6 PCIE9_RXN USB2_1P USB20_P1 <35> USB3 MB
<30,38> PCIE_CRX_DTX_P5 CC25 2 1 .1U_0402_16V7K PCIE_CTX_DRX_N5 BR2 PCIE9_RXP USB2.0 CE1 USB20_N2
GLAN <30> PCIE_CTX_C_DRX_N5 PCIE_CTX_DRX_P5 PCIE9_TXN USB2_2N USB20_P2 USB20_N2 <34>
CC26 2 1 .1U_0402_16V7K BR1 CE2
USB TypeC
<30> PCIE_CTX_C_DRX_P5 PCIE9_TXP USB2_2P USB20_P2 <34>
PCIE_CRX_DTX_N6 BN6 CG3 USB20_N3
<31> PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 BN5 PCIE10_RXN USB2_3N CG4 USB20_P3 USB20_N3 <35>

mp
<31> PCIE_CRX_DTX_P6 1 2 .1U_0402_16V7K PCIE_CTX_DRX_N6 BR4 PCIE10_RXP USB2_3P USB20_P3 <35>
NGFF WLAN+BT(Key E) <31> PCIE_CTX_C_DRX_N6
CC60
PCIE_CTX_DRX_P6 PCIE10_TXN USB20_N4 TO D/B USB2
CC62 1 2 .1U_0402_16V7K BR3 CD3
<31> PCIE_CTX_C_DRX_P6 PCIE10_TXP USB2_4N CD4 USB20_P4 USB20_N4 <35>
BN10 USB2_4P USB20_P4 <35>
<33> SATA_CRX_DTX_N0 BN8 PCIE11_RXN/SATA0_RXN CG5 USB20_N5
<33> SATA_CRX_DTX_P0 BN4 PCIE11_RXP/SATA0_RXP USB2_5N CG6 USB20_P5 USB20_N5 <37>
HDD <33> SATA_CTX_DRX_N0 PCIE11_TXN/SATA0_TXN USB2_5P USB20_P5 <37> FP
BN3
2 <33> SATA_CTX_DRX_P0 PCIE11_TXP/SATA0_TXP CC1 2

al
BL6 USB2_6N CC2
BL5 PCIE12_RXN/SATA1A_RXN USB2_6P
BN2 PCIE12_RXP/SATA1A_RXP CG8 USB20_N7
BN1 PCIE12_TXN/SATA1A_TXN USB2_7N CG9 USB20_P7 USB20_N7 <28>
PCIE12_TXP/SATA1A_TXP USB2_7P USB20_P7 <28> Camera
BK6 CB8
<31> PCIE_CRX_DTX_N9 BK5 PCIE13_RXN USB2_8N CB9

Co
<31> PCIE_CRX_DTX_P9 BM4 PCIE13_RXP USB2_8P
<31> PCIE_CTX_DRX_N9 BM3 PCIE13_TXN CH5 USB20_N9
<31> PCIE_CTX_DRX_P9 PCIE13_TXP USB2_9N CH6 USB20_P9 USB20_N9 <28>
BJ6 USB2_9P USB20_P9 <28> TS
<31> PCIE_CRX_DTX_N10 BJ5 PCIE14_RXN CC3 USB20_N10 ηϱϳϭϵϬϲĐŚĂŶŐĞƚŽh^ƉŽƌƚϭϬĨŽƌEsŝ
<31> PCIE_CRX_DTX_P10 BL2 PCIE14_RXP USB2_10N CC4 USB20_P10 USB20_N10 <31>
<31> PCIE_CTX_DRX_N10 BL1 PCIE14_TXN USB2_10P USB20_P10 <31> BT
<31> PCIE_CTX_DRX_P10 PCIE14_TXP USB2_COMP

nfi
CC5 RC119 1 2 113_0402_1%
BG5 USB2_COMP CE8 USB2_ID RC130 1 @ 2 0_0402_5%
<31> PCIE_CRX_DTX_N11 BG6 PCIE15_RXN/SATA1B_RXN USB2_ID CC6 USB2_VBUSSENSE 1 2 0_0402_5%
NGFF SSD(Key M) <31> PCIE_CRX_DTX_P11 PCIE15_RXP/SATA1B_RXP USB2_VBUSSENSE
RC131 @
BL4
<31> PCIE_CTX_DRX_N11 BL3 PCIE15_TXN/SATA1B_TXN CK6 USB_OC0# h^Ϯͺ/͕ h^Ϯͺsh^^E^
(Need Lane Reversal) <31> PCIE_CTX_DRX_P11 PCIE15_TXP/SATA1B_TXP GPP_E9/USB2_OC0#/GP_BSSB_CLK USB_OC1# USB_OC0# <35> /Ed>ͺĂůǀŝŶ ƌĞĐŽŵŵĞŶĚ ƌĞƐĞƌǀŝŶŐ ƚŚĞ W ƌĞƐŝƐƚĞƌƐ
CK5
BE5 GPP_E10/USB2_OC1#/GP_BSSB_DI CK8 USB_OC2#
hŶƵƐĞĚKƉŝŶŶĞĞĚƐĞƚƚŽ'W/͘

de
<31> PCIE_CRX_DTX_N12 BE6 PCIE16_RXN/SATA2_RXN GPP_E11/USB2_OC2# CK9 USB_OC3#
<31> PCIE_CRX_DTX_P12 BJ4 PCIE16_RXP/SATA2_RXP GPP_E12/USB2_OC3#
<31> PCIE_CTX_DRX_N12 BJ3 PCIE16_TXN/SATA2_TXN CP8
<31> PCIE_CTX_DRX_P12 PCIE16_TXP/SATA2_TXP GPP_E4/DEVSLP0 CR8
RC1201 2 100_0402_1% PCIE_RCOMPN CE6 GPP_E5/DEVSLP1 CM8 SSD_DEVSLP2
PCIE_RCOMPP PCIE_RCOMP_N GPP_E6/DEVSLP2 SSD_DEVSLP2 <31> +3VALW_PRIM
CE5
PCIE_RCOMP_P CN8 GPP_E0

nti
GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1 @ T278
CR28 CM10
ηϱϳϭϬϮϭ&>ͲhW'ZϬ͘ϳƉ͘ϯϵ CP28 GPP_H12/M2_SKT2_CFG_0 GPP_E1/SATAXPCIE1/SATAGP1 CP10 SATAXPCIE2
@ T279
W/ͺZKDWEͬW/ͺZKDWW CN28 GPP_H13/M2_SKT2_CFG_1 GPP_E2/SATAXPCIE2/SATAGP2 SATAXPCIE2 <31>
3 ZсϭϬϬŽŚŵ CM28 GPP_H14/M2_SKT2_CFG_2 CN7 1 2 3
GPP_H15/M2_SKT2_CFG_3 GPP_E8/SATALED#/SPI1_CS1# +3VS
AR3 RH16

al
RSVD_69 10K_0402_5%
WHL-U42_BGA1528 M.2 SSD PCIE/SATA select pin USB_OC3# RC283 2 1 10K_0402_5%
USB_OC2# RC284 2 1 10K_0402_5%
@
8 of 20
SSD_DET# (SATA_GP0) USB_OC1# RC285 2 1 10K_0402_5%
SATA Device 0 USB_OC0# RC286 2 1 10K_0402_5%

0.1U_0201_10V6K
ESD@ CC321
PCIE Device 1 1
GPIO DEVICE CONTROL
For MB field lesson learnt
USB_OC0# USB2 Port 1 2

USB_OC1# NA
USB_OC2# NA ȏʹǣͲȐ ’Ž‡‡–ƒ–‹‘
‹•ƒŠ‘•–Ǧ…‘–”‘ŽŽ‡†Šƒ”†™ƒ”‡•‹‰ƒŽ™Š‹…Š‡ƒ„Ž‡•ƒŠ‘•–ƒ††‡˜‹…‡–‘
USB_OC3# NA ‡–‡”ƒ—Ž–”ƒǦŽ‘™‹–‡”ˆƒ…‡’‘™‡”•–ƒ–‡ǡ‹…Ž—†‹‰–Š‡’‘••‹„‹Ž‹–›–‘…‘’Ž‡–‡Ž›’‘™‡”
DEVSLP0 NA †‘™Š‘•–ƒ††‡˜‹…‡•Ǥ
Š‡’”‘…‡••‘”’”‘˜‹†‡•–Š”‡‡•‹‰ƒŽ•ǡȏʹǣͲȐˆ‘”Ǥ
DEVSLP1 NA ɄŠ‡ Š‹ ‰Šǡ  ”‡“—‡•–• – Š‡  †‡˜‹ …‡ – ‘ ‡– ‡”‹ – ‘ – Š‡  ’‘ ™‡” •– ƒ– ‡Ǥ 
ɄŠ‡Ž ‘ ™ǡ   ”‡“—‡•–• – Š‡  †‡˜‹ …‡ – ‘ ‡š‹– ˆ ” ‘ 
 – Š‡  ’‘ ™‡” •– ƒ– ‡
DEVSLP2 NA ƒ†–”ƒ•‹–‹‘–‘ƒ…–‹˜‡•–ƒ–‡Ǥ
SATA_GP0 NA

‡‡”ƒŽ —”’‘•‡ ȋ
ȏʹǣͲȐȌ ‹‰ƒŽ•
SATA_GP1 NA ɄŠ‡ ’” ‘…‡•• ‘” ’”‘˜‹ †‡• – Š”‡‡  ‰‡‡”ƒŽ ’—” ’‘•‡‹ ’—– •‹ ‰ƒŽ •ǡ 
ȏ ʹǣ ͲȐ ˆ ‘”   Ǥ
4 Š‡•‡•‹‰ƒŽ•…ƒ„‡…‘ˆ‹‰—”‡†ƒ•‹–‡”Ž‘…•™‹–…Š‹’—–•…‘””‡•’‘†‹‰–‘ƒ‰‹˜‡’‘”–Ǥ 4

SATA_GP2 NA ɄŠ‡ —•‡† ƒ• ƒ‹ – ‡”Ž ‘…  • ™‹– … Š •– ƒ– —•‹ †‹ …ƒ–‹ ‘ǡ – Š‹ • •‹ ‰ƒŽ • Š‘—Ž † „‡ †”‹ ˜‡ – ‘ Ͳ
–‘‹†‹…ƒ–‡–Šƒ––Š‡•™‹–…Š‹•…Ž‘•‡†ƒ†–‘ƒͳ–‘‹†‹…ƒ–‡–Šƒ––Š‡•™‹–…Š‹•‘’‡Ǥ
Ʉˆ ‡… Šƒ‹ …ƒŽ ’”‡•‡…‡ • ™‹– … Š‡• ™‹ŽŽ ‘– „‡ —•‡† ‘ – Š‡ ’Ž ƒ–ˆ ‘”  ǡ  
ȏ ʹǣ ͲȐ
•‹‰ƒŽ•…ƒ„‡…‘ˆ‹‰—”‡†ƒ•
̴ȏʹǣͲȐ
••‹‰ƒŽ•Ǥ
Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(7/12)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 13 of 57
A B C D E
 A B C D E

+1.2V_VDDQ +1.2V_VDDQ_CPU
+VCCIO
нϭ͘Ϭϱs>tͺWZ/DdKнϭ͘Ϭϱsͺs^dh ͬ нϭ͘Ϭϱs^d JPC1
UC1N
AK24
+5VALW +1.05VALW_PRIM +1.05V_VCCSTU 1 2
ϯ͘ϯ AD36
CPU POWER 3 OF 4 VCCIO1 AK26
@ AH32 VDDQ1 VCCIO2 AL24
ϰ͘Ϭϲϲ
JUMP_43X118 AH36 VDDQ2 VCCIO3 AL25
AM36 VDDQ3 VCCIO4 AL26
JPC2 AN32 VDDQ4 VCCIO5 AL27
1 1 VDDQ5 VCCIO6

1U_0201_6.3V6M

1U_0201_6.3V6M
CC98

CC97
1 1 2 AW32 AM25
@ AY36 VDDQ6 VCCIO7 AM27
2 2 Vinafix.com 2
CC96
0.1U_0201_10V6K
JUMP_43X118 BE32
BH36
R32
VDDQ7
VDDQ8
VDDQ9
VCCIO8
VCCIO9
VCCIO10
BH24
BH25
BH26
Y36 VDDQ10 VCCIO11 BH27
1 UC5 VDDQ11 VCCIO12 BJ24 1
CC105 2 1 .1U_0402_16V7K 1 14 VCCIO13 BJ26
2 VIN1 VOUT1 13 VCCIO14 BP16
VIN1 VOUT1 BC28 VCCIO15 BP18
RC142 1 2 20K_0402_5% EN_1.0V_VCCSTU 3 12 1 2 RSVD1 VCCIO16
<36,40,45> SYSON ON1 CT1 CC95
Ϭ͘Ϭϲ BP11 BG8
+1.05V_VCCST VCCST1 VCCSA2 +VCC_SA
4 11 1000P_0402_50V7K BP2 BG10
VBIAS GND VCCST2 VCCSA1 BH9
RC168 1 2 49.9K_0402_1% EN_1.8VS 5 10 1 2 VCCSA3 BJ8
ϬΕϭ͘ϱϮs
<36,40,43,45,47> SUSP# ON2 CT2 CC94
Ϭ͘ϬϮ BG1 VCCSA5 BJ9 ϲ
+1.05VS_VCCSTG VCCSTG1 VCCSA6
2 1 CC104 6 9 1000P_0402_50V7K BG2 BJ10
.1U_0402_16V7K +1.8VALW_VS 7 VIN2 VOUT2 8 VCCSTG2 VCCSA4 BK8
VIN2 VOUT2 +1.8VS Ϭ͘ϭϮ BL27 VCCSA9 BK25
+1.2V_VCCSFR_OC VCCPLL_OC1 VCCSA7
15 BM26 BK27
1 2 GPAD VCCPLL_OC2 VCCSA8 BL8
+1.8VALW_PRIM 1 2 AOZ1331DI_DFN14_2X3
Ϭ͘ϭϯ BR11 VCCSA13 BL9
+1.05V_VCCSFR VCCPLL1 VCCSA14
JPC8 BT11 BL10

Co
1 1 VCCPLL2 VCCSA10

1U_0201_6.3V6M
CC99
JUMP_43X39 BL24
@ CC100 VCCSA11 BL26
0.1U_0201_10V6K VCCSA12 BM24
2
нϭ͘ϴs>tͺWZ/D dK нϭ͘ϴs^ 2 VCCSA15
VCCSA16
BN25

BP28 VCCIO_SENSE
VCCIO_SENSE VSSIO_SENSE T124 @
BP29 T125 @
VSSIO_SENSE

mp
BE7 VSSSA_SENSE
VSSSA_SENSE BG7 VCCSA_SENSE VSSSA_SENSE <48>
VCCSA_SENSE VCCSA_SENSE <48>
нϭ͘Ϭϱs>tͺWZ/D dK нϭ͘Ϭϱs^ͺs^d' WHL-U42_BGA1528
@
+1.05VALW_PRIM 14 of 20
+1.05VALW_PRIM_JP
2 2
JPC4

al
1 2
1 2 +1.05VS_VCCSTG +1.05V_VCCSTU +1.05V_VCCST
Imax : 3.44 AJUMP_43X79 1
1U_0201_6.3V6M
CC117

@ 2 @ 1 CC322 1 2 10U_0402_6.3V6M reserve for ripple

For Power consumption UC6 RC188 0_0402_5%
Measurement 1 PSC Side
2 2 VIN1 +VCCIO ηϱϳϱϰϭϮͺt,>ͺhͺW'ͺZϬ͘ϳ ƚĂďůĞϭϭͲϮ

Co
VIN2 Ϭ͘ϭϵ
CC107 @
+5VALW
7 6 +1.05VS_VCCSTG_IO 1
@ JPC5
2
2
RC140
@ 1
0_0402_5%
CC48 1 2 1U_0201_6.3V6M нϭ͘Ϭϱsͺs^d͗ϭdžϭƵ&
0.1U_0201_10V6K VIN thermal VOUT 1 2
2 1 3 1 JUMP_43X79 Imax : 4.066A +1.05V_VCCSFR
VBIAS
SUSP# 2 @ 1 SUSP#_R1 4 5 CC127 CC323 1 2 10U_0402_6.3V6M reserve for ripple
RC186 0_0402_5% ON GND 0.1U_0201_10V6K
2

nfi
PSC Side
1 ηϱϳϱϵϲϮt,>ͺZϰͺZsWͺ^,ZϬ͘ϳ
1U_0201_6.3V6M
CC106

AOZ1334DI-02_DFN8-7_3X3
нϭ͘Ϭϱsͺs^&Z͗ϭdžϭƵ&
@

2 @ 1 CC55 1 2 1U_0201_6.3V6M
Rds_on 3.6m ohm RC143 0_0402_5%
2 Rise time 0.5ms
+1.2V_VDDQ_CPU +1.2V_VCCSFR_OC PSC Side

de
ηϱϳϱϰϭϮͺt,>ͺhͺW'ͺZϬ͘ϳ ƚĂďůĞϭϭͲϮ
2
RC141
@ 1
0_0402_5%
CC49 1 2 1U_0201_6.3V6M нϭ͘Ϯsͺs^&ZͺK͗ϭdžϭƵ&
PSC Side

nti
+1.05VS_VCCSTG CC56 1 2 1U_0201_6.3V6M ηϱϳϱϰϭϮͺt,>ͺhͺW'ͺZϬ͘ϳ ƚĂďůĞϭϭͲϮ
нϭ͘Ϭϱsͺs^d'͗ϭdžϭƵ&
3 3

+VCCIO
al +1.2V_VDDQ_CPU
PSC Side BSC Side
PSC Side BSC Side
22U_0603_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1
1

1
CC58

CC150

CC37

CC149

CC148

CC147

CC146

CC38

CC39

CC40

CC42

CC145
CC151

CC152

CC27

CC28

CC33

CC34

CC35

CC36

CC43

CC44

CC45

CC46
2

2
2 2 2 2 2 2 2 2 2 2 2 2 2

ηϱϳϱϰϭϮͺt,>ͺhͺW'ͺZϬ͘ϳ ƚĂďůĞϭϭͲϮ
4 ηϱϳϱϵϲϮt,>ͺZϰͺZsWͺ^,ZϬ͘ϳ нϭ͘ϮsͺsYͺWh͗ 4

нs/K͗ ϵdžϭϬƵ&ϬϰϬϮ
ϴdžϭƵ& ϭdžϮϮƵ&ϬϲϬϯ
ϮdžϭϬƵ& ϰdžϭƵ&ϬϰϬϮ
Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(8/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 14 of 57
A B C D E
 A B C D E

+1.05VALW_PRIM +1.05VALW_MPHY UC1P

CPU POWER 4 OF 4
BP20 CB16
RC243 1 @ 2 0_0603_5% 1 2 CC136
ůŽƐĞƚŽsϭϮ +1.05VALW_PRIM
BW16 VCCPRIM_1P05_1 VCCPRIM_3P3_3 +3VALW_PRIM
22U_0603_6.3V6M
Ϯ͘ϭϬϰ BW18 VCCPRIM_1P05_9
BW19 VCCPRIM_1P05_10
BY16 VCCPRIM_1P05_11 BR23
VCCPRIM_1P05_12 VCCRTC +RTCVCC
CA14
VCCPRIM_1P05_14 BY20
Ϭ͘ϬϬϮ
+1.05VALW_PRIM
+1.05VALW_PRIM +1.05VALW_MPHYPLL

ůŽƐĞƚŽsϮ
Vinafix.com +1.8VALW_PRIM
Ϭ͘ϳϬϮ
CC15
CD15
CD16
VCCPRIM_1P8_1
VCCPRIM_1P8_4
VCCPRIM_1P05_13
DCPRTC
BP24
+DCPRTC /ŶƚĞŶĂůsZD

RC244 1 2 0_0603_5% 1 2 CC135 CP17 VCCPRIM_1P8_5 BR20

1 1U_0201_6.3V6M VCCPRIM_1P8_8 VCCPRIM_1P05_3 +1.05VALW_PRIM +VCCA_XTAL_1.05V +DCPRTC 1
CB22 BT12
+3VALW_PRIM VCCPRIM_3P3_4 VCCAPLL_1P05_3
1 2 CC320 CB23 2 @ 1
22U_0603_6.3V6M
Ϭ͘ϮϬϳ CC22 VCCPRIM_3P3_5 BP14 0_0402_5% RC169
VCCPRIM_3P3_6 VCCA_BCLK_1P05

22U_0603_6.3V6M
ηϱϳϱϰϭϮͺt,>ͺhͺW'ͺZϬ͘ϳ ƚĂďůĞϭϭͲϭϮ CC23
ĚĚ ϰϳƵ& Λ CD22 VCCPRIM_3P3_7 BR14
ϴͬϭϱ͕ϯϭϵƵƐĞ ϮϮh& ĨŽƌ KD ĐŽŶǀĞŶŝĞŶĐĞ VCCPRIM_3P3_8 VCCAPLL_1P05_1 1 1 2

CC319
CD23 ηϱϳϱϰϭϮͺt,>ͺhͺW'ͺZϬ͘ϳ ƚĂďůĞϭϭͲϭϮ
+3VALW +3VALW_DSW CP29 VCCPRIM_3P3_9 ĚĚ ϰϳƵ& Λ CC86 CC71
VCCPRIM_3P3_10 ϴͬϭϱ͕ϯϭϵƵƐĞ ϮϮh& ĨŽƌ KD ĐŽŶǀĞŶŝĞŶĐĞ
BU12 1U_0201_6.3V6M 1U_0201_6.3V6M
BU15 VCCA_SRC_1P05 2 2 1
2 @ 1 1 2 CC137
ůŽƐĞƚŽZϮϰ +1.05VALW_PRIM
BU22 VCCPRIM_CORE1 CP5
ϰ͘Ϯϲ VCCPRIM_CORE2 VCCA_XTAL_1P05 +VCCA_XTAL_1.05V ůŽƐĞƚŽWϱ ůŽƐĞƚŽWϮϰ
@

RC173 0_0402_5% 1U_0201_6.3V6M BV15

BV16 VCCPRIM_CORE3 BY24
BV18 VCCPRIM_CORE4 VCCDPHY_1P24_2 CA24
BV19 VCCPRIM_CORE5 VCCDPHY_1P24_4
BV20 VCCPRIM_CORE6 BY23
+3VALW_PRIM +3VALW_HDA BV22 VCCPRIM_CORE7 VCCDPHY_1P24_1 CA23

Co
BW20 VCCPRIM_CORE8 VCCDPHY_1P24_3 CP25
BW22 VCCPRIM_CORE9 VCCDPHY_1P24_5 +VCCDPHY_1.24V /ŶƚĞŶĂůsZD
2 @ 1 1 2 CC63 CA12 VCCPRIM_CORE10 BT23
VCCPRIM_CORE11 VCCDSW_3P3_2 +3VALW_DSW
RC198 0_0402_5% 1U_0201_6.3V6M CA16
VCCPRIM_CORE12
@

CA18 BR12
VCCPRIM_CORE13 VCCA_19P2_1P05 +1.05VALW_PRIM
+3VALW_SPI CA19
CA20 VCCPRIM_CORE14
CB12 VCCPRIM_CORE15

mp
2 @ 1 CB14 VCCPRIM_CORE16
RC154 0_0402_5% CB15 VCCPRIM_CORE17 CC18
VCCPRIM_CORE18 VCCPRIM_1P8_2 +1.8VALW_PRIM
CC19
BT24 VCCPRIM_1P8_3 CD18
/ŶƚĞŶĂůsZD +VCCDSW_1P05 VCCDSW_1P05 VCCPRIM_1P8_6 CD19
BU14 VCCPRIM_1P8_7 CP23
+1.05VALW_PRIM VCCAPLL_1P05_4 VCCPRIM_1P8_9 +1.8VALW_PRIM
2 BV12 BW23 2
+1.05VALW_MPHY +3VALW_PRIM

al
BW12 VCCPRIM_MPHY_1P05_1 VCCPRIM_3P3_2
+1.05VALW_PRIM +3VALW_PRIM Ϯ͘ϴϳϴ BW14 VCCPRIM_MPHY_1P05_3
BY12 VCCPRIM_MPHY_1P05_4
BY14 VCCPRIM_MPHY_1P05_5 BP23
VCCPRIM_MPHY_1P05_6 VCCPRIM_3P3_1 1 1
PRIMCORE_VID0

@
BV2 CB36 CC72 CC144
2 2 1 +1.05VALW_MPHYPLL VCCAMPHYPLL_1P05 GPP_B0/CORE_VID0 PRIMCORE_VID1 T136 @
CB35

Co
T138 @ 1U_0201_6.3V6M 1U_0201_6.3V6M
CC138 CC139 CC140 BR15 GPP_B1/CORE_VID1 2 2
1U_0201_6.3V6M 0.1U_0201_10V6K VCCAPLL_1P05_2
1U_0201_6.3V6M
1 1 2 CC12
ůŽƐĞƚŽWϮϯ ůŽƐĞƚŽWϭϳ
@

@ VCCDUSB_1P05
BR24
ůŽƐĞƚŽWϮϬ ůŽƐĞƚŽWϮϵ +3VALW_DSW VCCDSW_3P3_1
Ϭ͘ϬϬϰ BT20
+3VALW_HDA VCCHDA

nfi
BV23
+3VALW_SPI VCCSPI
BT18
BT19 VCCPRIM_1P05_4
BU18 VCCPRIM_1P05_5
+1.05VALW_PRIM +VCCDSW_1P05 BU19 VCCPRIM_1P05_7 +VCCDPHY_1.24V
VCCPRIM_1P05_8

de
BT22
BP22 VCCPRIM_1P05_6
VCCPRIM_1P05_2
1 1 2
CC141 CC134 BV14
+1.05VALW_MPHY VCCPRIM_MPHY_1P05_2
@

1U_0201_6.3V6M 1U_0201_6.3V6M CC142

WHL-U42_BGA1528 4.7U_0402_6.3V6M
2 2 16 of 20 1

nti
@

ůŽƐĞƚŽsϭϴ ůŽƐĞƚŽdϮϰ ůŽƐĞƚŽWϮϱ

3 3
UC1O

al
RESERVED SIGNALS
K12 AA24
K14 RSVD48 RSVD38 AA26
K15 RSVD49 RSVD39 AB25
K17
K18
RSVD50
RSVD51
RSVD40
RSVD41
AC24
AC25
Support charger
K20 RSVD52 RSVD42 AC26 +CHGRTC
L25 RSVD53 RSVD43 AD24
M24 RSVD54 RSVD44 AD26 DC2
M26 RSVD55 RSVD45 V25 +RTCBATT_CHG 2 +1.05VALW_CLK5_F24NS +1.05VALW_PRIM
P24 RSVD56 RSVD46 T25
+3VALW +3VALW_PRIM P26 RSVD57 RSVD47 1 +RTCVCC RC152 1 @ 2 0_0603_5%
JPC7 R24 RSVD58
1 2 R25 RSVD59 3
1 2 R26 RSVD60
JUMP_43X39 RSVD61 BAS40-04_SOT23-3
@ RTC_CHG@

W25
RTC Battery
V24 RSVD62
Y25 RSVD63 +RTCBATT
Y24 RSVD64 RH163 +RTCBATT
RSVD65 1K_0402_5% DC1 +RTCVCC
1 2 3 JRTC1
ηϱϰϯϬϭϲ W'Ϯ͘Ϭ W͘ϰϳϬ 1
sZdĚŽĞƐŶŽƚĞdžĐĞĞĚϯ͘Ϯs͘ WHL-U42_BGA1528 RTC@ 1 2 1
2
@ 1 2

2.2U_0201_6.3V6M
15 of 20 2 CC143 3
+CHGRTC GND
CC84 @ CC324 4
WŽǁĞƌZĂŝů sŽůƚĂŐĞ sKWĂŶĚsKW/KĨŽƌ&>hϰϯĞ ŽŶůLJ 0.1U_0201_10V6K GND
4.7U_0402_6.3V6M

2
4 CHN202UPT_SC70-3 2 1 4
ACES_50271-0020N-001
н,'Zd RTC@
ϯ͘ϯϴϯs;DyͿ CONN@
ηϱϳϱϰϭϮͺt,>ͺhͺW'ͺZϬ͘ϳ ƚĂďůĞϭϭͲϭϭ
ůŽƐĞƚŽZϮϯ &ŽƌĨĂĐƚŽƌLJZdƌĞƋƵĞƐƚ SP02000RO00
dϱϰ;s&Ϳ ϮϰϬ ŵs

нZds ϯ͘ϭϰϯs Security Classification

2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
ZĞƐƵůƚ͗WĂƐƐ WHL-U(9/12)Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, August 16, 2018 Sheet 15 of 57
A B C D E
 A B C D E

+VCC_CORE +VCC_CORE +VCC_GT +VCC_GT

UC1L UC1M
ϬΕϭ͘ϱϮs
ϯϭ
AN9
CPU POWER 1 OF 4
AW24
ϬΕϭ͘ϱϮs A5
CPU POWER 2 OF 4
D15
AN10 VCCCORE5 VCCCORE35 AW25 ϳϬ A6 VCCGT8 VCCGT58 D17
AN24
AN26
AN27
VCCCORE1
VCCCORE2
VCCCORE3
Vinafix.com
VCCCORE36
VCCCORE37
VCCCORE38
AW26
AW27
AY24
+VCC_GT_VCORE A8
A11
A12
VCCGT9
VCCGT10
VCCGT1
VCCGT59
VCCGT60
VCCGT61
D18
D20
E4
AP2 VCCCORE4 VCCCORE44 AY26 A14 VCCGT2 VCCGT64 F5
1 AP9 VCCCORE6 VCCCORE45 BA5 A15 VCCGT3 VCCGT69 F6 1
AP24 VCCCORE9 VCCCORE48 BA7 A17 VCCGT4 VCCGT70 F7
AP26 VCCCORE7 VCCCORE49 BA8 A18 VCCGT5 VCCGT71 F8
AR5 VCCCORE8 VCCCORE50 BA25 A20 VCCGT6 VCCGT72 F11
AR6 VCCCORE13 VCCCORE46 BA27 VCCGT7 VCCGT65 F14
AR7 VCCCORE14 VCCCORE47 BB2 AA9 ES1/ES2 VCCGT66 F17
AR8 VCCCORE15 VCCCORE51 BB26 AB2 VCCGT11/VCCCORE75 VCCGT67 F20
AR10 VCCCORE16 VCCCORE52 BC5 AB8 VCCGT13/VCCCORE76 VCCGT68 G11
AR25 VCCCORE10 VCCCORE56 BC6 AB9 VCCGT14/VCCCORE77 VCCGT73 G12
AR27 VCCCORE11 VCCCORE57 BC7 AB10 VCCGT15/VCCCORE78 VCCGT74 G14
AT9 VCCCORE12 VCCCORE58 BC9 AC8 VCCGT12/VCCCORE79 VCCGT75 G15
AT24 VCCCORE19 VCCCORE59 BC10 AD9 VCCGT16/VCCCORE80 VCCGT76 G17
AT26 VCCCORE17 VCCCORE53 BC26 AE8 VCCGT17/VCCCORE81 VCCGT77 G18
AU5 VCCCORE18 VCCCORE54 BC27 AE9 VCCGT19/VCCCORE82 VCCGT78 G20
AU6 VCCCORE24 VCCCORE55 BD5 AE10 VCCGT20/VCCCORE83 VCCGT79 H5
AU7 VCCCORE25 VCCCORE63 BD8 AF2 VCCGT18/VCCCORE84 VCCGT87 H6
AU8 VCCCORE26 VCCCORE64 BD10 AF8 VCCGT22/VCCCORE85 VCCGT88 H7

Co
AU9 VCCCORE27 VCCCORE60 BD25 AF10 VCCGT23/VCCCORE86 VCCGT89 H8
AU24 VCCCORE28 VCCCORE61 BD27 AG8 VCCGT21/VCCCORE87 VCCGT90 H11
AU25 VCCCORE20 VCCCORE62 BE9 AG9 VCCGT24/VCCCORE88 VCCGT80 H12
AU26 VCCCORE21 VCCCORE69 BE24 AH9 VCCGT25/VCCCORE89 VCCGT81 H14
AU27 VCCCORE22 VCCCORE65 BE25 AJ8 VCCGT26/VCCCORE90 VCCGT82 H15
AV2 VCCCORE23 VCCCORE66 BE26 AJ10 VCCGT28/VCCCORE91 VCCGT83 H17
AV5 VCCCORE30 VCCCORE67 BE27 AK2 VCCGT27/VCCCORE92 VCCGT84 H18
AV7 VCCCORE32 VCCCORE68 BF2 AK9 VCCGT29//VCCCORE93 VCCGT85 H20

mp
AV10 VCCCORE33 VCCCORE70 BF9 AL8 VCCGT30/VCCCORE94 VCCGT86 J7
AV27 VCCCORE29 VCCCORE73 BF24 AL9 VCCGT32/VCCCORE95 VCCGT95 J8
AW5 VCCCORE31 VCCCORE71 BF26 AL10 VCCGT33/VCCCORE96 VCCGT96 J11
AW6 VCCCORE39 VCCCORE72 BG27 AM8 VCCGT31/VCCCORE97 VCCGT91 J14
AW7 VCCCORE40 VCCCORE74 V2 VCCGT34/VCCCORE98 VCCGT92 J17
AW8 VCCCORE41 AN6
dƌĂĐĞ>ĞŶŐƚŚфϮϱŵŝůƐ Y10 VCCGT115/VCCCORE99 VCCGT93 J20
AW9 VCCCORE42 VCC_SENSE AN5 VCCSENSE <48> Y8 VCCGT119/VCCCORE100 VCCGT94 K2
2 AW10 VCCCORE43 VSS_SENSE VSSSENSE <48> VCCGT120/VCCCORE101 VCCGT98 K11 2

al
VCCCORE34 AA3 SOC_SVID_ALERT# B3 VCCGT97 L7
VIDALERT# B4 VCCGT39 VCCGT100 L8
BB9 AA1 SOC_SVID_CLK B6 VCCGT40 VCCGT101 L10
BC24 RSVD3 VIDSCK SOC_SVID_CLK <48> B8 VCCGT41 VCCGT99 M9
AY9 RSVD4 AA2 SOC_SVID_DAT B11 VCCGT42 VCCGT102 N7
BB24 RSVD1 VIDSOUT B14 VCCGT35 VCCGT104 N8
RSVD2 Y3 B17 VCCGT36 VCCGT105 N9

Co
+1.05VS_VCCSTG
RSVD5 B20 VCCGT37 VCCGT106 N10
BG3 C2 VCCGT38 VCCGT103 P2
VCCSTG1 C3 VCCGT49 VCCGT107 P8
WHL-U42_BGA1528 C6 VCCGT51 VCCGT108 R9
C7 VCCGT52 VCCGT109 T8
@ 12 of 20 VCCGT53 VCCGT111
C8 T9
C11 VCCGT54 VCCGT112 T10
VCCGT43 VCCGT110

nfi
C12 U8
C14 VCCGT44 VCCGT114 U10
C15 VCCGT45 VCCGT113
C17 VCCGT46 V9
C18 VCCGT47 VCCGT116 W8
C20 VCCGT48 VCCGT117 W9
D4 VCCGT50 VCCGT118

de
D7 VCCGT62
D11 VCCGT63 E3 VCCGT_SENSE
D12 VCCGT55 VCCGT_SENSE D2 VSSGT_SENSE VCCGT_SENSE <48>
D14 VCCGT56 VSSGT_SENSE VSSGT_SENSE <48>
VCCGT57

nti
WHL-U42_BGA1528
13 of 20
@
dƌĂĐĞ>ĞŶŐƚŚфϮϱŵŝůƐ
3 3

al
+1.05V_VCCST
ηϱϰϯϬϭϲ W'Ϯ͘Ϭ W͘Ϯϳϯ
1

RC179 RC181
56_0402_5% 100_0402_1%

WůĂĐĞƚŚĞWh
ƌĞƐŝƐƚŽƌƐĐůŽƐĞƚŽWh
2

RC180
220_0402_5%
SOC_SVID_ALERT# 1 2
SOC_SVID_ALERT#_R <48>
SOC_SVID_DAT dŽsZ
4 SOC_SVID_DAT <48> 4

Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(10/12)Power,SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 16 of 57
A B C D E
 A B C D E

Vinafix.com
1 1

UC1R UC1S UC1T

GND 1 OF 3
BT35 GND 2 OF 3 BY25 GND 3 OF 3
CR34 BL7 D6 VSS_145 VSS_217 J18 N6 CF23
BT5 VSS_1 VSS_73 AE25 AL32 VSS_146 VSS_218 AU32 B37 VSS_290 VSS_362 V4
BY5 VSS_2 VSS_74 BM33 BT36 VSS_147 VSS_219 BY28 CB3 VSS_291 VSS_363 BE30
CP35 VSS_3 VSS_75 CM5 D8 VSS_148 VSS_220 J21 P10 VSS_292 VSS_364 CF28
CM37 VSS_4 VSS_76 AE27 AL7 VSS_149 VSS_221 AV25 B5 VSS_293 VSS_365 W10
CK37 VSS_5 VSS_77 BM35 D9 VSS_150 VSS_222 BY33 CB33 VSS_294 VSS_366 BE31
AW1 VSS_6 VSS_78 CM9 AM10 VSS_151 VSS_223 J24 P3 VSS_295 VSS_367 CF3
CM1 VSS_7 VSS_79 AE30 BU11 VSS_152 VSS_224 AV28 B7 VSS_296 VSS_368 W27
BD6 VSS_8 VSS_80 BM36 E23 VSS_153 VSS_225 BY35 CB4 VSS_297 VSS_369 CF4
AY4 VSS_9 VSS_81 CN13 AM28 VSS_154 VSS_226 J33 P33 VSS_298 VSS_370 W30
VSS_10 VSS_82 VSS_155 VSS_227 VSS_299 VSS_371

Co
B34 AE7 E27 AV3 B9 BF3
E35 VSS_11 VSS_83 BM9 AM33 VSS_156 VSS_228 BY36 CB7 VSS_300 VSS_372 CG33
A4 VSS_12 VSS_84 CN17 BU23 VSS_157 VSS_229 J36 P36 VSS_301 VSS_373 W7
AE24 VSS_13 VSS_85 AF27 E29 VSS_158 VSS_230 AV33 BA10 VSS_302 VSS_374 BF33
AE26 VSS_14 VSS_86 BN30 AM35 VSS_159 VSS_231 J6 CC11 VSS_303 VSS_375 CG7
AF25 VSS_15 VSS_87 CN21 BU24 VSS_160 VSS_232 AV36 P4 VSS_304 VSS_376 BF36
AG24 VSS_16 VSS_88 AF3 E31 VSS_161 VSS_233 C1 BA28 VSS_305 VSS_377 Y26
VSS_17 VSS_89 VSS_162 VSS_234 VSS_306 VSS_378

mp
AG26 BN7 BU25 K21 P7 BF4
AH24 VSS_18 VSS_90 CN25 E33 VSS_163 VSS_235 AV4 BA3 VSS_307 VSS_379 CH31
AH25 VSS_19 VSS_91 AF30 AN25 VSS_164 VSS_236 C21 CC20 VSS_308 VSS_380 Y27
B2 VSS_20 VSS_92 CN29 BU7 VSS_165 VSS_237 K22 R27 VSS_309 VSS_381 BG25
B36 VSS_21 VSS_93 AF33 E9 VSS_166 VSS_238 AV6 BB3 VSS_310 VSS_382 Y30
C36 VSS_22 VSS_94 BP15 AN28 VSS_167 VSS_239 C25 CC25 VSS_311 VSS_383 BG28
C37 VSS_23 VSS_95 AF36 BV11 VSS_168 VSS_240 K24 R28 VSS_312 VSS_384 CJ11
2 CN1 VSS_24 VSS_96 AF4 F12 VSS_169 VSS_241 AV8 BB33 VSS_313 VSS_385 Y33 2

al
CN2 VSS_25 VSS_97 CN5 AN29 VSS_170 VSS_242 C29 CC28 VSS_314 VSS_386 CJ14
CN37 VSS_26 VSS_98 AF7 F15 VSS_171 VSS_243 K25 R29 VSS_315 VSS_387 Y35
CP2 VSS_27 VSS_99 BP25 AN30 VSS_172 VSS_244 AW28 BB36 VSS_316 VSS_388 BH28
D1 VSS_28 VSS_100 CN9 F18 VSS_173 VSS_245 C33 CC31 VSS_317 VSS_389 CJ19
A32 VSS_29 VSS_101 AG10 AN31 VSS_174 VSS_246 K27 R30 VSS_318 VSS_390 Y7
F33 VSS_30 VSS_102 BP3 BV3 VSS_175 VSS_247 AW29 BB4 VSS_319 VSS_391 BH29

Co
A3 VSS_31 VSS_103 CP1 F2 VSS_176 VSS_248 C4 CC7 VSS_320 VSS_392 CJ23
BJ7 VSS_32 VSS_104 BP32 AN7 VSS_177 VSS_249 K28 R31 VSS_321 VSS_393 BH32
CJ36 VSS_33 VSS_105 CP11 BV31 VSS_178 VSS_250 AW3 BC25 VSS_322 VSS_394 CJ28
A36 VSS_34 VSS_106 AH27 F21 VSS_179 VSS_251 C9 CD11 VSS_323 VSS_395 BH33
BK10 VSS_35 VSS_107 BP33 AN8 VSS_180 VSS_252 K29 T27 VSS_324 VSS_396 CJ33
CJ4 VSS_36 VSS_108 CP13 BV33 VSS_181 VSS_253 AW30 CD12 VSS_325 VSS_397 BH35
AB27 VSS_37 VSS_109 AH28 F24 VSS_182 VSS_254 CA11 T30 VSS_326 VSS_398 CJ35

nfi
BK2 VSS_38 VSS_110 BP4 BV4 VSS_183 VSS_255 K3 BC29 VSS_327 VSS_399 BP19
CK1 VSS_39 VSS_111 CP15 F3 VSS_184 VSS_256 AW31 CD14 VSS_328 VSS_400 BR16
AB3 VSS_40 VSS_112 AH29 AP3 VSS_185 VSS_257 CA15 T33 VSS_329 VSS_401 BY18
BK28 VSS_41 VSS_113 BP7 BW11 VSS_186 VSS_258 K30 T35 VSS_330 VSS_402 BY19
AB30 VSS_42 VSS_114 CP19 F4 VSS_187 VSS_259 AY33 BC32 VSS_331 VSS_403 CC16
BK3 VSS_43 VSS_115 AH30 AP33 VSS_188 VSS_260 CA22 CD24 VSS_332 VSS_404 BU16

de
CK4 VSS_44 VSS_116 CP21 BW15 VSS_189 VSS_261 K31 T36 VSS_333 VSS_405 CC14
AB33 VSS_45 VSS_117 AH31 G21 VSS_190 VSS_262 AY35 CD25 VSS_334 VSS_406 BR22
BK33 VSS_46 VSS_118 BR19 AP36 VSS_191 VSS_263 K32 T7 VSS_335 VSS_407 BU20
CK7 VSS_47 VSS_119 CP27 G27 VSS_192 VSS_264 B12 BC8 VSS_336 VSS_408 CD20
AB36 VSS_48 VSS_120 AH33 AP4 VSS_193 VSS_265 K4 CE33 VSS_337 VSS_409 BT14
BK4 VSS_49 VSS_121 BR25 G33 VSS_194 VSS_266 B15 U26 VSS_338 VSS_410 BP12

nti
CL2 VSS_50 VSS_122 AH35 AR28 VSS_195 VSS_267 CA25 BD28 VSS_339 VSS_411 CB24
AB4 VSS_51 VSS_123 CP37 G35 VSS_196 VSS_268 K9 CE35 VSS_340 VSS_412 CC24
BK7 VSS_52 VSS_124 AJ25 G36 VSS_197 VSS_269 B18 U7 VSS_341 VSS_413 J5
3 CM13 VSS_53 VSS_125 BT15 AT33 VSS_198 VSS_270 CB11 BD33 VSS_342 VSS_414 U24 3
AB7 VSS_54 VSS_126 AJ28 BW24 VSS_199 VSS_271 L27 CE36 VSS_343 VSS_415 BD7
BL25 VSS_55 VSS_127 BT16 G9 VSS_200 VSS_272 B21 V26 VSS_344 VSS_416 AR4

al
CM17 VSS_56 VSS_128 CP9 AT35 VSS_201 VSS_273 L33 BD35 VSS_345 VSS_417 AU4
AC10 VSS_57 VSS_129 AJ7 H21 VSS_202 VSS_274 B23 CE7 VSS_346 VSS_418 AW4
BL28 VSS_58 VSS_130 CR2 AT36 VSS_203 VSS_275 L35 V27 VSS_347 VSS_419 BA6
CM21 VSS_59 VSS_131 AK3 BW7 VSS_204 VSS_276 B25 BD36 VSS_348 VSS_420 BC4
AC27 VSS_60 VSS_132 CR36 H27 VSS_205 VSS_277 CB18 CF11 VSS_349 VSS_421 BE4
BL29 VSS_61 VSS_133 AK33 AT4 VSS_206 VSS_278 L36 V3 VSS_350 VSS_422 BE8
CM25 VSS_62 VSS_134 D21 BY11 VSS_207 VSS_279 B27 BE10 VSS_351 VSS_423 BA4
AC30 VSS_63 VSS_135 AK36 AU10 VSS_208 VSS_280 CB19 CF14 VSS_352 VSS_424 BD4
BL30 VSS_64 VSS_136 BT25 BY15 VSS_209 VSS_281 L6 V30 VSS_353 VSS_425 BG4
CM29 VSS_65 VSS_137 D25 H9 VSS_210 VSS_282 B29 BE28 VSS_354 VSS_426 CJ2
BL31 VSS_66 VSS_138 AK4 AU28 VSS_211 VSS_283 CB2 CF19 VSS_355 VSS_427 CJ3
CM31 VSS_67 VSS_139 BT28 BY22 VSS_212 VSS_284 N25 V33 VSS_356 VSS_428 AM5
AD33 VSS_68 VSS_140 AL28 J12 VSS_213 VSS_285 B31 BE29 VSS_357 VSS_429 CM4
BL32 VSS_69 VSS_141 BT33 AU29 VSS_214 VSS_286 CB20 CF2 VSS_358 VSS_430 AC5
CM33 VSS_70 VSS_142 D5 J15 VSS_215 VSS_287 N27 V36 VSS_359 VSS_431 AG5
AD35 VSS_71 VSS_143 AL29 VSS_216 VSS_288 CB25 BE3 VSS_360 VSS_432 CR6
VSS_72 VSS_144 VSS_289 VSS_361 VSS_433

W HL-U42_BGA1528 W HL-U42_BGA1528 W HL-U42_BGA1528

@ @ 18 of 20 @ 19 of 20
17 of 20

4 4

Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(11/12)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 17 of 57
A B C D E
 A B C D E

UC1Q

Vinafix.com
RESERVED SIGNALS
F37
CFG0 T4 RSVD_TP5 F34 &ϯϳ͕&ϯϰ͕EϯϲĂƌĞZ^sŽŶt,>Ͳh
@ T167 CFG_0 RSVD_TP4
@ T168 CFG1 R4
CFG2 T3 CFG_1 CP36
@ T169 CFG_2 IST_TRIG T162 @
1 CFG3 R3 CN36 1
@ T170 CFG_3 RSVD_TP3
@ T171 CFG4 J4
CFG5 M4 CFG_4 BJ36
@ T172 CFG_5 RSVD15
@ T173 CFG6 J3 BJ34
CFG7 M3 CFG_6 RSVD14
@ T174 CFG_7
@ T175 CFG8 R2 BK34 T273 @
CFG9 N2 CFG_8 TP_1 BR18
@ T176 CFG_9 TP_2 T272 @
@ T177 CFG10 R1
CFG11 N1 CFG_10
@ T178 CFG_11
@ T179 CFG12 J2
CFG13 L2 CFG_12 BT9
@ T180 CFG_13 RSVD21
@ T181 CFG14 J1 BT8
CFG15 L1 CFG_14 RSVD20
@ T182 CFG_15 BP8
CFG16 L3 RSVD18 BP9
@ T183 CFG_16 RSVD19
@ T186 CFG18 N3
CFG17 L4 CFG_18 CR4

Co
@ T184 CFG_17 RSVD29
@ T188 CFG19 N4
CFG_19 CP3
RSVD26 CR3
CFG_RCOMP AB5 RSVD27
CFG_RCOMP
XDP_ITP_PMODE W4 ηϱϳϱϰϭϰt,> DĞĐŚ^ƉĞĐ Zϭ͘Ϯ
@ T189 ITP_PMODE WϯϲͲх s^^Ͳх 'E
BP36
CG2 VSS_434

mp
CG1 RSVD25
RSVD24
AT3
RSVD12 AU3
RSVD13
H4
H3 RSVD34
2 RSVD33 AN1 2

al
BV24 RSVD8 AN2
BV25 RSVD22 RSVD9
RSVD23 AN4
RSVD11 AN3
RSVD10
AL2
G3 RSVD72 AL1

Co
'ϯ͕'ϰĂƌĞZ^sŽŶt,>Ͳh G4 RSVD66 RSVD73
RSVD67
AL4
RSVD74 AL3
BK36 RSVD75
BK35 RSVD17 BP34
RSVD16 TP_4 T214 @
BP35 T216 @
TP_3

nfi
W3
AM4 RSVD35
RSVD7 C34
AM3 RSVD68
RSVD6 A34
RSVD_TP1 B35 ϯϰ͕ϯϰ͕ϯϱ͕,Ϯϲ͕:ϮϳĂƌĞZ^sŽŶ t,>Ͳh
RSVD_TP2

de
CR35 T281 @ /Ed>Z&>ŝŶĚĂƐƵŐŐĞƐƚĂĚĚƚĞƐƚƉŽŝŶƚĨŽƌŵŽŶŝƚŽƌEsŝŽ
A35 RSVD28
2 1 CFG_RCOMP D34 RSVD1
49.9_0402_1% RC185 RSVD30 AH26
G2 RSVD36 AJ27 +1.05V_VCCST
2 1 CFG4 G1 RSVD32 RSVD37
RSVD31 E1 SKL_CNL# 1 2

nti
1K_0402_1% RC193 @
SKTOCC# RC184 100K_0402_5%

WHL-U42_BGA1528
3 3
@ 20 of 20
͓ͷͶͶ͸͸ͻ ͳǤͳ ǤͷͶ

al
͓ͷͶͶͻʹͶ  ͳǤʹ Ǥͳʹͷ
̴͓
Š‹•’‹‹•ˆ‘”…‘’ƒ–‹„‹Ž‹–›™‹–Šˆ—–—”‡
ŝƐƉůĂLJ WŽƌƚ WƌĞƐĞŶĐĞ ^ƚƌĂƉ ’Žƒ–ˆ‘”•Ǥ–•Š‘—Ž†„‡—…‘‡…–‡†ˆ‘”
–Š‡ ’”‘…‡••‘”Ǥ
ϭ͗ŝƐĂďůĞĚ͖EŽWŚLJƐŝĐĂůŝƐƉůĂLJWŽƌƚ
&'ϰ Ăƚ ƚ ĂĐ ŚĞĚ ƚ Ž  ŵďĞĚĚĞĚ ŝƐ Ɖů ĂLJ WŽƌƚ
Ϭ͗ŶĂďůĞĚ͖ŶĞdžƚĞƌŶĂůŝƐƉůĂLJWŽƌƚĚĞǀŝĐĞ ŝƐ
ĐŽŶŶĞĐƚĞĚ ƚŽ ƚŚĞ ŵďĞĚĚĞĚ ŝƐƉůĂLJ WŽƌƚ

4 4

Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(12/12)RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 18 of 57
A B C D E
 A B C D E

<8> DDR_A_DQS#[0..7]
JDIMM1A
<8> DDR_A_D[0..63]
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
137
139 CK0(T)
CK0#(C)
REVERSE
DQ0
DQ1
8
7
DDR_A_D8
DDR_A_D13
DDR_A_D14
REVERSE TYPE
138 20
<8> DDR_A_DQS[0..7] DDR_A_CLK#1 140 CK1(T) DQ2 21 DDR_A_D15
CK1#(C) DQ3 4 DDR_A_D12 2-3A to 1 DIMMs/channel
DDR_A_CKE0 109 DQ4 3 DDR_A_D10
<8> DDR_A_MA[0..16] DDR_A_CKE1 110 CKE0 DQ5 16 DDR_A_D11

<8>
<8>
DDR_A_BA0
DDR_A_BA1
DDR_A_BA0
DDR_A_BA1
DDR_A_BG0
Vinafix.com DDR_A_CS#0
DDR_A_CS#1
149
157
CKE1

S0#
DQ6
DQ7
DQS0(T)
17
13
11
DDR_A_D9
DDR_A_DQS1
DDR_A_DQS#1
<8> DDR_A_BG0 DDR_A_BG1 162 S1# DQS0#(C) +1.2V_VDDQ +1.2V_VDDQ
1 <8> DDR_A_BG1 DDR_A_ACT# 165 S2#/C0 28 DDR_A_D3 1
JDIMM1B
<8> DDR_A_ACT# DDR_A_ALERT# S3#/C1 DQ8 29 DDR_A_D6 REVERSE
<8> DDR_A_ALERT# DDR_A_PAR DDR_A_ODT0 155 DQ9 41 DDR_A_D4 111 141
<8> DDR_A_PAR DDR_A_ODT1 161 ODT0 DQ10 42 DDR_A_D5 112 VDD1 VDD11 142
ODT1 DQ11 24 DDR_A_D2 117 VDD2 VDD12 147
DDR_A_BG0 115 DQ12 25 DDR_A_D7 118 VDD3 VDD13 148
DDR_A_CLK0 DDR_A_BG1 113 BG0 DQ13 38 DDR_A_D1 +1.2V_VDDQ 123 VDD4 VDD14 153
<8> DDR_A_CLK0 DDR_A_CLK#0 DDR_A_SA2 DDR_A_BA0 150 BG1 DQ14 37 DDR_A_D0 124 VDD5 VDD15 154
<8> DDR_A_CLK#0 DDR_A_CLK1 DDR_A_SA1 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS0 +0.6V_A_VREFCA 129 VDD6 VDD16 159
<8> DDR_A_CLK1 BA1 DQS1(T) VDD7 VDD17

1
DDR_A_CLK#1 DDR_A_SA0 32 DDR_A_DQS#0 130 160
<8> DDR_A_CLK#1 DDR_A_MA0 144 DQS1#(C) RD65 135 VDD8 VDD18 163
A0 VDD9 VDD19

1
DDR_A_MA1 133 50 DDR_A_D20 1K_0402_1% 136
DDR_A_CKE0 RD66 RD64 RD67 DDR_A_MA2 132 A1 DQ16 49 DDR_A_D16 +0.6V_DDRA_VREFCA VDD10
<8> DDR_A_CKE0 DDR_A_CKE1 DDR_A_MA3 131 A2 DQ17 62 DDR_A_D19 255 258
0_0402_5% @ @ @ RD68 +3VS +0.6VS_VTT
<8> DDR_A_CKE1

2
DDR_A_CS#0 DDR_A_MA4 A3 DQ18 DDR_A_D23 VDDSPD VTT

0_0402_5%

0_0402_5%
128 63 2_0402_1% 10mils
<8> DDR_A_CS#0 DDR_A_CS#1 DDR_A_MA5 126 A4 DQ19 46 DDR_A_D17 2 1 164 257
<8> DDR_A_CS#1 +2.5V

2
DDR_A_MA6 127 A5 DQ20 45 DDR_A_D21 VREFCA VPP1 259

Co
DDR_A_MA7 A6 DQ21 DDR_A_D18 1 VPP2
122 58
SOC_SMBDATA_1 DDR_A_MA8 125 A7 DQ22 59 DDR_A_D22 CD71 1 99
<9,20,33> SOC_SMBDATA_1 A8 DQ23 1 VSS VSS

1
SOC_SMBCLK_1 DDR_A_MA9 121 55 DDR_A_DQS2 0.022U_0402_16V7K 2 102
<9,20,33> SOC_SMBCLK_1 DDR_A_MA10 146 A9 DQS2(T) 53 DDR_A_DQS#2 2 5 VSS VSS 103
RD69 CD72
DDR_A_MA11 120 A10_AP DQS2#(C) 1K_0402_1% 0.1U_0201_10V6K 6 VSS VSS 106
A11 VSS VSS

1
DDR_A_ODT0 DDR_A_MA12 119 70 DDR_A_D25 2 9 107
<8> DDR_A_ODT0 DDR_A_ODT1 DDR_A_MA13 158 A12 DQ24 71 DDR_A_D28 10 VSS VSS 167
RD70
<8> DDR_A_ODT1

2
DDR_A_MA14 151 A13 DQ25 83 DDR_A_D31 14 VSS VSS 168

mp
A14_WE# DQ26 24.9_0402_1% VSS VSS
DDR_A_MA15 156 84 DDR_A_D27 15 171
DDR_A_MA16 152 A15_CAS# DQ27 66 DDR_A_D24 18 VSS VSS 172

2
A16_RAS# DQ28 67 DDR_A_D29 19 VSS VSS 175
DDR_A_ACT# 114 DQ29 79 DDR_A_D30 22 VSS VSS 176
ACT# DQ30 80 DDR_A_D26 23 VSS VSS 180
DDR_A_PAR 143 DQ31 76 DDR_A_DQS3 26 VSS VSS 181
DDR_A_ALERT# 116 PARITY DQS3(T) 74 DDR_A_DQS#3 27 VSS VSS 184
Layout Note:
2
Place near JDIMM1 +1.2V_VDDQ RD71 2 1 240_0402_1% DDR_A_EVENT# 134 ALERT# DQS3#(C) WůĂĐĞŶĞĂƌƚŽ^KͲ/DDĐŽŶŶĞĐƚŽƌ͘ 30 VSS VSS 185 2

al
DDR_DRAMRST# 108 EVENT# 174 DDR_A_D37 31 VSS VSS 188
<8,20> DDR_DRAMRST# RESET# DQ32 173 DDR_A_D32 35 VSS VSS 189
RD72 1 @ 2 470_0402_5% DQ33 187 DDR_A_D39 36 VSS VSS 192
+1.2V_VDDQ SOC_SMBDATA_1 254 DQ34 DDR_A_D38 VSS VSS
186 39 193
CD73 2 1 .1U_0402_16V7K SOC_SMBCLK_1 253 SDA DQ35 170 DDR_A_D36 40 VSS VSS 196
@ESD@ SCL DQ36 169 DDR_A_D33 43 VSS VSS 197
+1.2V_VDDQ DDR_A_SA2 166 DQ37 183 DDR_A_D34 44 VSS VSS 201

Co
DDR_A_SA1 260 SA2 DQ38 182 DDR_A_D35 47 VSS VSS 202
DDR_A_SA0 256 SA1 DQ39 179 DDR_A_DQS4 48 VSS VSS 205
SA0 DQS4(T) DDR_A_DQS#4 VSS VSS
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

177 51 206
DQS4#(C) 52 VSS VSS 209
1 1 1 1 1 1 1 1 DDR_A_D43 VSS VSS
CD74

CD75

CD76

CD77

CD78

CD79

CD80

CD81

92 195 56 210
91 CB0_NC DQ40 194 DDR_A_D41 57 VSS VSS 213
101 CB1_NC DQ41 207 DDR_A_D47 60 VSS VSS 214
2 2 2 2 2 2 2 2 CB2_NC DQ42 DDR_A_D44 VSS VSS

nfi
105 208 61 217
88 CB3_NC DQ43 191 DDR_A_D40 64 VSS VSS 218
87 CB4_NC DQ44 190 DDR_A_D45 65 VSS VSS 222
100 CB5_NC DQ45 203 DDR_A_D46 68 VSS VSS 223
104 CB6_NC DQ46 204 DDR_A_D42 69 VSS VSS 226
RD73 2 1 240_0402_1% DDR_A_DQS8 97 CB7_NC DQ47 200 DDR_A_DQS5 72 VSS VSS 227
+1.2V_VDDQ DDR_A_DQS#8 DQS8(T) DQS5(T) DDR_A_DQS#5 VSS VSS
RD74 2 1 240_0402_1% 95 198 73 230

de
DQS8#(C) DQS5#(C) 77 VSS VSS 231
+1.2V_VDDQ 216 DDR_A_D53 78 VSS VSS 234
12 DQ48 215 DDR_A_D48 81 VSS VSS 235
+1.2V_VDDQ DM0#/DBI0# DQ49 DDR_A_D50 VSS VSS
33 228 82 238
54 DM1#/DBI1# DQ50 229 DDR_A_D51 85 VSS VSS 239
75 DM2#/DBI2# DQ51 211 DDR_A_D52 86 VSS VSS 243
DM3#/DBI3# DQ52 DDR_A_D49 VSS VSS
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

178 212 89 244

nti
199 DM4#/DBI4# DQ53 224 DDR_A_D54 90 VSS VSS 247
DM5#/DBI5# DQ54 VSS VSS
1

DDR_A_D55
CD82

CD83

CD84

CD85

CD86

CD87

CD88

CD89

220 225 93 248

241 DM6#/DBI6# DQ55 221 DDR_A_DQS6 94 VSS VSS 251
3 96 DM7#/DBI7# DQS6(T) 219 DDR_A_DQS#6 98 VSS VSS 252 3
2

DM8#/DBI8# DQS6#(C) VSS VSS

262 261

al
GND GND
237 DDR_A_D63
DQ56 236 DDR_A_D61 DEREN_40-42271-26001RHF
DQ57 249 DDR_A_D56
DQ58 DDR_A_D62 CONN@
250
DQ59 232 DDR_A_D57
DQ60 233 DDR_A_D60
DQ61 245 DDR_A_D58
DQ62 246 DDR_A_D59
DQ63 242 DDR_A_DQS7
DQS7(T) 240 DDR_A_DQS#7
DQS7#(C)
Layout Note:
Place near JDIMM1.258
DEREN_40-42271-26001RHF
CONN@
SP07001EZ00
Layout Note: Layout Note: ^LJŵďŽů͗^WϬϳϬϬϭ'Ϭ;,сϱ͘ϮͿ +0.6VS_VTT
Place near JDIMM1.257,259 Place near JDIMM1.255
+1.2V_VDDQ

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
#575412 WHL-U PDG R0.7 Table 4-23
add 0.1UF 1 1

CD90

CD91

CD92
+2.5V +3VS &ŽůůŽǁ Dϱϭ

2
2 2
4 4

1
1U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

CD241 CD93 + CD237

1 1
1

1
CD243

330U_D2_2V_Y
CD94

CD95

CD238
10U_0402_6.3V6M

10U_0402_6.3V6M

@ SGA00009S00
2
.1U_0402_16V7K

330U 2V H1.9
2

2 2
9mohm POLY Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ͺ̸
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Wednesday, August 15, 2018 Sheet 19 of 57
A B C D E
 A B C D E

<8> DDR_B_DQS#[0..7]
JDIMM2A
<8> DDR_B_D[0..63]
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
137
139 CK0(T)
CK0#(C)
STD
DQ0
DQ1
8
7
DDR_B_D12
DDR_B_D8
DDR_B_D15
Standard Type
138 20
<8> DDR_B_DQS[0..7] DDR_B_CLK#1 140 CK1(T) DQ2 21 DDR_B_D11
CK1#(C) DQ3 4 DDR_B_D13 2-3A to 1 DIMMs/channel
DDR_B_CKE0 109 DQ4 3 DDR_B_D9
<8> DDR_B_MA[0..16] DDR_B_CKE1 110 CKE0 DQ5 16 DDR_B_D10

<8>
<8>
DDR_B_BA0
DDR_B_BA1
DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
+3VS
Vinafix.com DDR_B_CS#0
DDR_B_CS#1
149
157
CKE1

S0#
DQ6
DQ7
DQS0(T)
17
13
11
DDR_B_D14
DDR_B_DQS1
DDR_B_DQS#1
<8> DDR_B_BG0 DDR_B_BG1 162 S1# DQS0#(C) +1.2V_VDDQ +1.2V_VDDQ
<8> DDR_B_BG1 S2#/C0

1
1 DDR_B_ACT# 165 28 DDR_B_D3 JDIMM2B 1
<8> DDR_B_ACT# DDR_B_ALERT# S3#/C1 DQ8 29 DDR_B_D7 STD
RD52
<8> DDR_B_ALERT# DDR_B_PAR DDR_B_ODT0 155 DQ9 41 DDR_B_D4 111 141
0_0402_5% @
<8> DDR_B_PAR DDR_B_ODT1 161 ODT0 DQ10 42 DDR_B_D5 112 VDD1 VDD11 142
ODT1 DQ11 24 DDR_B_D0 117 VDD2 VDD12 147

2
DDR_B_BG0 115 DQ12 25 DDR_B_D2 118 VDD3 VDD13 148
DDR_B_CLK0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D1 +1.2V_VDDQ 123 VDD4 VDD14 153
<8> DDR_B_CLK0 DDR_B_CLK#0 DDR_B_SA2 DDR_B_BA0 150 BG1 DQ14 37 DDR_B_D6 124 VDD5 VDD15 154
<8> DDR_B_CLK#0 DDR_B_CLK1 DDR_B_SA1 DDR_B_BA1 145 BA0 DQ15 34 DDR_B_DQS0 +0.6V_B_VREFCA 129 VDD6 VDD16 159
<8> DDR_B_CLK1 BA1 DQS1(T) VDD7 VDD17

1
DDR_B_CLK#1 DDR_B_SA0 32 DDR_B_DQS#0 130 160
<8> DDR_B_CLK#1 DDR_B_MA0 144 DQS1#(C) RD46 135 VDD8 VDD18 163
A0 VDD9 VDD19

1
DDR_B_MA1 133 50 DDR_B_D17 1K_0402_1% 136
DDR_B_CKE0 RD54 RD56 DDR_B_MA2 132 A1 DQ16 49 DDR_B_D21 +0.6V_DDRB_VREFCA VDD10
<8> DDR_B_CKE0 DDR_B_CKE1 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D22 255 258
0_0402_5% @ 0_0402_5% @ RD49 +3VS +0.6VS_VTT
<8> DDR_B_CKE1

2
DDR_B_CS#0 DDR_B_MA4 128 A3 DQ18 63 DDR_B_D19 VDDSPD VTT
<8> DDR_B_CS#0 DDR_B_CS#1 DDR_B_MA5 A4 DQ19 DDR_B_D20
2_0402_1% 10mils
126 46 2 1 164 257
<8> DDR_B_CS#1 +2.5V

2
DDR_B_MA6 127 A5 DQ20 45 DDR_B_D16 VREFCA VPP1 259

Co
DDR_B_MA7 A6 DQ21 DDR_B_D23 1 VPP2
122 58
SOC_SMBDATA_1 DDR_B_MA8 125 A7 DQ22 59 DDR_B_D18 CD66 1 99
<9,19,33> SOC_SMBDATA_1 A8 DQ23 1 VSS VSS

1
SOC_SMBCLK_1 DDR_B_MA9 121 55 DDR_B_DQS2 0.022U_0402_16V7K 2 102
<9,19,33> SOC_SMBCLK_1 DDR_B_MA10 146 A9 DQS2(T) 53 DDR_B_DQS#2 2 5 VSS VSS 103
RD47 CD65
DDR_B_MA11 120 A10_AP DQS2#(C) 1K_0402_1% 0.1U_0201_10V6K 6 VSS VSS 106
A11 VSS VSS

1
DDR_B_ODT0 DDR_B_MA12 119 70 DDR_B_D25 2 9 107
<8> DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA13 158 A12 DQ24 71 DDR_B_D29 10 VSS VSS 167
RD50
<8> DDR_B_ODT1

2
DDR_B_MA14 151 A13 DQ25 83 DDR_B_D30 14 VSS VSS 168

mp
A14_WE# DQ26 24.9_0402_1% VSS VSS
DDR_B_MA15 156 84 DDR_B_D27 15 171
DDR_B_MA16 152 A15_CAS# DQ27 66 DDR_B_D28 18 VSS VSS 172

2
A16_RAS# DQ28 67 DDR_B_D24 19 VSS VSS 175
DDR_B_ACT# 114 DQ29 79 DDR_B_D31 22 VSS VSS 176
ACT# DQ30 80 DDR_B_D26 23 VSS VSS 180
DDR_B_PAR 143 DQ31 76 DDR_B_DQS3 26 VSS VSS 181
DDR_B_ALERT# 116 PARITY DQS3(T) 74 DDR_B_DQS#3 27 VSS VSS 184
Layout Note:
2
Place near JDIMM2 +1.2V_VDDQ RD63 2 1 240_0402_1% DDR_B_EVENT# 134 ALERT# DQS3#(C) WůĂĐĞŶĞĂƌƚŽ^KͲ/DDĐŽŶŶĞĐƚŽƌ͘ 30 VSS VSS 185 2

al
DDR_DRAMRST# 108 EVENT# 174 DDR_B_D39 31 VSS VSS 188
<8,19> DDR_DRAMRST# RESET# DQ32 173 DDR_B_D38 35 VSS VSS 189
RD1 1 2 470_0402_5% DQ33 187 DDR_B_D37 36 VSS VSS 192
+1.2V_VDDQ SOC_SMBDATA_1 254 DQ34 DDR_B_D34 VSS VSS
186 39 193
CD30 2 1 .1U_0402_16V7K SOC_SMBCLK_1 253 SDA DQ35 170 DDR_B_D32 40 VSS VSS 196
@ESD@ SCL DQ36 169 DDR_B_D33 43 VSS VSS 197
+1.2V_VDDQ DDR_B_SA2 166 DQ37 183 DDR_B_D36 44 VSS VSS 201

Co
DDR_B_SA1 260 SA2 DQ38 182 DDR_B_D35 47 VSS VSS 202
DDR_B_SA0 256 SA1 DQ39 179 DDR_B_DQS4 48 VSS VSS 205
SA0 DQS4(T) DDR_B_DQS#4 VSS VSS
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

177 51 206
DQS4#(C) 52 VSS VSS 209
1 1 1 1 1 1 1 1 DDR_B_D40 VSS VSS
CD32

CD33

CD34

CD35

CD36

CD37

CD69

CD70

92 195 56 210
91 CB0_NC DQ40 194 DDR_B_D41 57 VSS VSS 213
101 CB1_NC DQ41 207 DDR_B_D43 60 VSS VSS 214
2 2 2 2 2 2 2 2 CB2_NC DQ42 DDR_B_D46 VSS VSS

nfi
105 208 61 217
88 CB3_NC DQ43 191 DDR_B_D44 64 VSS VSS 218
87 CB4_NC DQ44 190 DDR_B_D45 65 VSS VSS 222
100 CB5_NC DQ45 203 DDR_B_D42 68 VSS VSS 223
104 CB6_NC DQ46 204 DDR_B_D47 69 VSS VSS 226
RD61 2 1 240_0402_1% DDR_B_DQS8 97 CB7_NC DQ47 200 DDR_B_DQS5 72 VSS VSS 227
+1.2V_VDDQ DDR_B_DQS#8 DQS8(T) DQS5(T) DDR_B_DQS#5 VSS VSS
RD62 2 1 240_0402_1% 95 198 73 230

de
DQS8#(C) DQS5#(C) 77 VSS VSS 231
+1.2V_VDDQ 216 DDR_B_D53 78 VSS VSS 234
12 DQ48 215 DDR_B_D52 81 VSS VSS 235
+1.2V_VDDQ DM0#/DBI0# DQ49 DDR_B_D54 VSS VSS
33 228 82 238
54 DM1#/DBI1# DQ50 229 DDR_B_D50 85 VSS VSS 239
75 DM2#/DBI2# DQ51 211 DDR_B_D49 86 VSS VSS 243
DM3#/DBI3# DQ52 DDR_B_D48 VSS VSS
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

178 212 89 244

nti
199 DM4#/DBI4# DQ53 224 DDR_B_D55 90 VSS VSS 247
DM5#/DBI5# DQ54 VSS VSS
1

DDR_B_D51
CD38

CD39

CD40

CD41

CD42

CD43

CD44

CD45

220 225 93 248

241 DM6#/DBI6# DQ55 221 DDR_B_DQS6 94 VSS VSS 251
3 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6 98 VSS VSS 252 3
2

DM8#/DBI8# DQS6#(C) VSS VSS

262 261

al
GND GND
237 DDR_B_D61
DQ56 236 DDR_B_D57 FOX_AS0A821-H4SB-7H
DQ57 249 DDR_B_D58 CONN@
DQ58 250 DDR_B_D63
DQ59 DDR_B_D60
SP07001GA00
232
DQ60 233 DDR_B_D56
DQ61 245 DDR_B_D59
DQ62 246 DDR_B_D62
DQ63 242 DDR_B_DQS7
DQS7(T) 240 DDR_B_DQS#7
DQS7#(C)
Layout Note:
Place near JDIMM1.258
FOX_AS0A821-H4SB-7H
CONN@
SP07001GA00

Layout Note: Layout Note: +0.6VS_VTT

Place near JDIMM1.257,259 Place near JDIMM2.255

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
#575412 WHL-U PDG R0.7 Table 4-23
add 0.1UF 1 1

CD64

CD62

CD63
+2.5V +3VS

2
2 2
4 4
10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

1 1
1

1
CD240

CD68

CD242
CD67

CD55

CD239
.1U_0402_16V7K
2

2 2
Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ͺ̸
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 20 of 57
A B C D E
 A B C D E

NV_GPIO11 RV167 1 N16X@ 2 0_0402_5% DGPU_VID N16 GPU

NV_GPIO0 DGPU_VID <53>
RV168 1 N17S@ 2 0_0402_5%
UGPU1A +3VS_1.8VSDGPU_AON GPIO I/O USAGE
NV_GPIO0 RV169 1 N16X@ 2 0_0402_5% GC6_FB_EN1V8 GPIO0 O GC6_FB_EN
NV_GPIO1 GC6_FB_EN1V8 <22>
Part 1 of 6 RV170 1 N17S@ 2 0_0402_5% GPIO1
NV_GPIO0 A6_OVERT# O MEM_VDD_CTL
<13> PCIE_CTX_C_GRX_P1 AG6 C6 RV289 2 VGA@ 1 10K_0402_5%
AG7 PEX_RX0 GPIO0 B2 NV_GPIO1 NV_GPIO6 RV172 1 N16X@ 2 0_0402_5% GPU_EVENT#_1 GPIO9_ALERT RV290 2 VGA@ 1 10K_0402_5% GPIO2 O LCD_BL_PWM
<13> PCIE_CTX_C_GRX_N1 PEX_RX0_N GPIO1 NV_GPIO2 NV_GPIO2 ACIN_BUF
<13> PCIE_CTX_C_GRX_P2 AF7 D6 RV171 1 N17S@ 2 0_0402_5% RV291 2 VGA@ 1 10K_0402_5% GPIO3 O LCD_VCC
AE7 PEX_RX1 GPIO2 C7 VRAM_VREF_CTL RV292 2 VGA@ 1 10K_0402_5%
<13> PCIE_CTX_C_GRX_N2 PEX_RX1_N GPIO3 NV_GPIO4 NV_GPIO5 3_1.8VSDGPU_MAIN_EN GPIO4 O LCD_BLEN
AE9 F9 RV174 1 N16X@ 2 0_0402_5%
<13> PCIE_CTX_C_GRX_P3 PEX_RX2 GPIO4 NV_GPIO5 NV_GPIO4 3_1.8VSDGPU_MAIN_EN <22,40> GPIO5 O 3V3_MAIN_EN
AF9 A3 RV173 1 N17S@ 2 0_0402_5%
<13> PCIE_CTX_C_GRX_N3 PEX_RX2_N GPIO5 NV_GPIO6

Vinafix.com
AG9 A4 GPIO6 I GPU_EVENT#
<13> PCIE_CTX_C_GRX_P4 PEX_RX3 GPIO6 NV_GPIO13 DGPU_PSI
AG10 B6 RV176 1 N16X@ 2 0_0402_5% GPIO7 O 3D Vision
<13> PCIE_CTX_C_GRX_N4 PEX_RX3_N GPIO7 A6_OVERT# NV_GPIO6 DGPU_PSI <53> +3VS_1.8VSDGPU_AON
AF10 A6 RV175 1 N17S@ 2 0_0402_5%
AE10 NC PEX_RX4 OVERT F8 GPIO9_ALERT GPIO8 I SYS_PEX_RST_MON#
AE12 NC PEX_RX4_N GPIO9 C5 VRAM_VREF_CTL GPIO9 I/O THERM_ALERT
1 NC PEX_RX5 GPIO10 NV_GPIO11 VRAM_VREF_CTL <26> GPU_EVENT#_1 1
AF12 E7 RV293 2 VGA@ 1 10K_0402_5%
AG12 NC PEX_RX5_N GPIO11 D7 ACIN_BUF 3_1.8VSDGPU_MAIN_EN RV294 2 VGA@ 1 10K_0402_5%
GPIO10 O MEM_VREF_CTL

AG13 NC PEX_RX6 GPIO12 B4 NV_GPIO13 NV_GPIO8 RV178 1 N16X@ 2 0_0402_5% SYS_PEX_RST_MON#_R GPU_PEX_RST_HOLD# RV295 2 VGA@ 1 10K_0402_5% GPIO11 O PWM_VID

GPIO
AF13 NC PEX_RX6_N GPIO13 B3
<23> NV_GPIO8 GC6_FB_EN1V8 RV296 2 VGA@ 1 10K_0402_5% GPIO12 I PWR_LEVEL
+3VS_1.8VSDGPU_AON AE13 NC PEX_RX7 GPIO14 C3
NC PEX_RX7_N GPIO15 NV_GPIO1 VRAM_VDD_CTL GPIO13 O PSI
AE15 D5 RV180 1 N16X@ 2 0_0402_5%
AF15 NC PEX_RX8 GPIO16 D4 NV_GPIO8 RV179 1 N17S@ 2 0_0402_5% VRAM_VDD_CTL <51> GPIO14 I HPD_A
AG15 NC PEX_RX8_N GPIO17 C2 GPIO15 I HPD_C
AG16 NC PEX_RX9 GPIO18 F7
AF16 NC PEX_RX9_N GPIO19 E6 +3VS_1.8VSDGPU_AON GPIO16 I FRAME_LOCK#
NV_I2CB_SCL RV183 1 N17S@ 2 1.8K_0402_1% AE16 NC PEX_RX10 GPIO20 C4 GPU_PEX_RST_HOLD# GPIO17 I HPD_D
NV_I2CB_SDA RV184 1 N17S@ 2 1.8K_0402_1% AE18 NC PEX_RX10_N GPIO21 UV11 N16X@ GPIO18 I HPD_E
AF18 NC PEX_RX11 NC AB6 MC74VHC1G08DFT2G_SC70-5
NV_I2CC_SCL RV185 1 N17S@ 2 1.8K_0402_1% AG18 NC PEX_RX11_N PEX_WAKE_NC SA00000OH00 R2000
GPIO19 I HPD_F or HPD_B
NV_I2CC_SDA RV186 1 N17S@ 2 1.8K_0402_1% AG19 NC PEX_RX12 VCC: 2.0 ~ 5.5V I2CS_SDA 1 VGA@ 2 1.8K_0402_1% GPIO20 Reserved
AF19 NC PEX_RX12_N +3VS_1.8VSDGPU_AON QV5 N16X@ R2001
NC PEX_RX13
Push Pull Output GPIO21 O GPU_PEX_RST_HOLD#
AE19 2N7002KDW_SOT363-6 I2CS_SCL 1 VGA@ 2 1.8K_0402_1%

Co
AE21 NC PEX_RX13_N AG3 +3VS_1.8VSDGPU_AON SB00000EO00 R2052
GPIO22
NC PEX_RX14 NC

2
AF21 AF4 DGPU_PSI 2 VGA@ 1 10K_0402_5% GPIO23
AG21 NC PEX_RX14_N NC AF3 VCC: 1.65 ~ 5.5V RV83
AG22 NC PEX_RX15 NC
NC PEX_RX15_N
Push Pull Output 10K_0402_5% CLKREQ_PCIE#0 <11>

5
@ N17 GPU
PH at PCH side GPU_EVENT#_12 1

VCC
GPU_EVENT# <10> GPIO I/O USAGE

3
CV11 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P1 AC9 AE3 1VS_DGPU_PG 1 D2011 VGA@
<13> PCIE_CRX_GTX_P1 PEX_TX0 NC IN B

DACs
CV12 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N1 AB9 AE4 4 ALL_GPWRGD 5 G
D
QV5A RB751V-40_SOD323-2 GPIO0 O PWM_VID
<13> PCIE_CRX_GTX_N1

mp
CV13 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P2 AB10 PEX_TX0_N NC 2 OUT Y PJT138KA 2N SOT363-6 ACIN_BUF 2 1
<40,51> 1.35VS_DGPU_PG GPIO1 GC6_FB_EN

GND
<13> PCIE_CRX_GTX_P2 O
S

CV14 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N2 AC10 PEX_TX1 IN A CV264 RV165 N17S@ D2000 VGA@ DGPU_AC_DETECT <10,36,43>
<13> PCIE_CRX_GTX_N2

4
PEX_TX1_N

2
PCIE_CRX_C_GTX_P3 GPIO2 I GPU_EVENT#

PCI EXPRESS
<13> PCIE_CRX_GTX_P3 CV15 VGA@ 1 2 0.22U_0402_16V7K AD11 UV11 1 RB751V-40_SOD323-2
CV16 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N3 AC11 PEX_TX2 W5 NL17SZ08DFT2G_SC70-5 GPIO3 I/O NVVDDS_PWM
<13> PCIE_CRX_GTX_N3

3
CV17 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P4 AC12 PEX_TX2_N NC AE2 N17S@ VGA@ VGA@ DGPU_CLKREQ#

0.01U_0402_16V7K
<13> PCIE_CRX_GTX_P4 PCIE_CRX_C_GTX_N4 PEX_TX3 TS_VREF TSEN_VREF GPIO4 O 1V8_MAIN_EN
VGA@ 1 2 AB12 AF2

10K_0402_5%
<13> PCIE_CRX_GTX_N4 CV18 0.22U_0402_16V7K
AB13 PEX_TX3_N NC 2 GPIO5 I FRAME_LOCK#

1
AC13 NC PEX_TX4 1 @ 2 GPIO6 O PSI
2
ͲϬϴϯϮϵͲϬϬϭͺsϬϮ AD14 NC PEX_TX4_N RV166 PLTRST_VGA# 2

al
GPIO7 O LCD_BL_PWM
AC14 NC PEX_TX5 0_0402_5%
NC PEX_TX5_N GPIO8 O MEM_VDD_CTL
AC15 QV5B
AB15 NC PEX_TX6 GPIO9 I/O THERM_ALERT
PJT138KA 2N SOT363-6
NC PEX_TX6_N

2
AB16 B7 NV_I2CA_SCL R2003 1 N16X@ 2 1.8K_0402_1% Add CV264 for wavefrom glitch
GPIO23 I2CA_SCL N17S@ GPIO10 O MEM_VREF_CTL
AC16 NC PEX_TX7 A7 NV_I2CA_SDA R2004 1 N16X@ 2 1.8K_0402_1%

G
NC PEX_TX7_N GPIO22 I2CA_SDA A6_OVERT# GPIO11 O LCD_VDD
AD17 1 6 GPU_OVERT# <22,36>
NC PEX_TX8 NV_I2CB_SCL PLTRST_VGA#

Co
AC17 C9 1 N16X@ 2 1.8K_0402_1%

D
R2005 GPIO12 I PWR_LEVEL
AC18 NC PEX_TX8_N I2CB_SCL C8 NV_I2CB_SDA R2006 1 N16X@ 2 1.8K_0402_1%
NC PEX_TX9 I2CB_SDA GPIO13 O LCD_BLEN

I2C
AB18 QV9
AB19 NC PEX_TX9_N A9 NV_I2CC_SCL R2007 1 N16X@ 2 1.8K_0402_1% GPIO14 I HPD_IFPA
BSS138W-7-F_SOT323-3

2
NC PEX_TX10 I2CC_SCL NV_I2CC_SDA

G
AC19 B9 R2008 1 N16X@ 2 1.8K_0402_1% GPIO15 I HPD_IFPB
NC PEX_TX10_N I2CC_SDA @
AD20 GPIO16 Reserved
AC20 NC PEX_TX11 D9 I2CS_SCL GPIO9_ALERT 3 1
NC PEX_TX11_N I2CS_SCL I2CS_SDA GPU_ALERT <36> GPIO17 I HPD_IFPD
AC21 D8

D
NC PEX_TX12 I2CS_SDA GPIO18

nfi
AB21 I HPD_IFPE
AD23 NC PEX_TX12_N
AE23 NC PEX_TX13 Place Under L6 GPIO19 O 3D_VISION
NC PEX_TX13_N GPIO20 Reserved
AF24 C2000
AE24 NC PEX_TX14 XS_PLLVDD L6 +PLLVDD 1 2 .1U_0402_16V7K VGA@ GPIO21 Reserved (OC_WARN)
AG24 NC PEX_TX14_N PLLVDD M6 +GPU_PLLVDD
GPIO22 Reserved
AG25 NC PEX_TX15 SP_PLLVDD +3VS_1.8VSDGPU_AON Q2001 N16X@

de
NC PEX_TX15_N N6 1 N17S@ 2 2N7002KDW_SOT363-6 GPIO23 Reserved
VID_PLLVDD NC
R2009 RV187 VCC: 1.65 ~ 5.5V SB00000EO00

5
10K_0402_5% 0_0402_5% Push Pull Output VGA_GATE
1 VGA@ 2 AE8 C2001 Q2001B

VCC
+3VS_1.8VSDGPU_AON <11> CLK_PCIE_P0

2
AD8 PEX_REFCLK VGA@ PLTRST_VGA# 1 PJT138KA 2N SOT363-6
DGPU_CLKREQ# <11> CLK_PCIE_N0 PEX_REFCLK_N IN B VGA_GATE
AC6 1 2 .1U_0402_16V7K 4 N17S@

G
PEX_CLKREQ_N C2750 1 2 .1U_0402_16V7K 2 OUT Y I2CS_SCL 1 6
1

GND
+3VS_1.8VSDGPU_MAIN SOC_SML1CLK <9,36>

nti
PEX_TSTCLK_OUT+ AF22 IN A

D
NC VGA@
CLK

2 @ 1 PEX_TSTCLK_OUT- AE22 PEX_TSTCLK_OUT NC C11 XTALIN CV233

R2010 200_0402_1% PEX_TSTCLK_OUT_N XTAL_IN B10 XTALOUT
Place Under M6 UV12 @ 0.01U_0402_16V7K VGA_GATE

3
XTAL_OUT NL17SZ08DFT2G_SC70-5 2 @ Q2001A

͸ʹǤͲˆ—…–‹‘

5
3 PLTRST_VGA# AC7 A10 XTAL_SSIN R2012 1 VGA@ 2 10K_0402_5% PJT138KA 2N SOT363-6 3
2 VGA@ 1 PEX_TREMP AF25 PEX_RST_N XTAL_SSIN C10 XTAL_OUTBUFF R2013 1 VGA@ 2 10K_0402_5% N17S@

G
R2011 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF 1 VGA@ 2 VGA_GATE I2CS_SDA 4 3

al
SOC_SML1DATA <9,36>

D
RV161
GM108-ES-S-A1_FCBGA595 0_0402_5%
@

+3VS
RV113 +GPU_PLLVDD
1 N17S@ 2 GC6_FB_EN3V3 R4966
GC6_FB_EN3V3 <12>
10K_0402_5% 0_0402_5%
3

RV111 D2001 1 N17S@ 2

1 N17S@ 2 5
D
2 +1.05VS_1.0VSDGPU
10K_0402_5%
G

1 1.35VSDGPU_PWR_EN 38mA
1.35VSDGPU_PWR_EN <40,51>
S
6

QV8A 3 VGA@
4

GC6_FB_EN1V8 2 G
D
N17S@ +PLLVDD 1 2 N16X@
1

QV8B S PJT138KA 2N SOT363-6 BAV70W_SOT323-3 L2000 PBY160808T-300Y-N_2P R4961 N17S@

PJT138KA 2N SOT363-6 R2014 1 0_0402_5%
1

N17S@ 200K_0402_1% +3VS_1.8VSDGPU_AON C2003 SD028000080

W>>ͺs SM010008A00 3000ma 30ohm@100mhz DCR 0.03
@ Ϭ͘ϭhdžϭ͕ ϮϮhdžϭ N16X@
RV160 1 N16X@ 2 PD at Power Side 22U_0603_6.3V6M X2000
ϯϬŽŚŵ;^ZϬ͘ϬϱͿdžϭ
2

0_0402_5% 2 R4961 27MHZ_10PF_7R27000001

1VS_DGPU_PG R2056 680_0402_1%
<52> 1VS_DGPU_PG EĞĂƌ'Wh XTALOUT_R
10K_0402_5% XTALOUT 1 N16X@ 2 3 1 XTALIN
@ 3 1

15P_0402_50V8J
+3VS_1.8VSDGPU_AON R4967 +GPU_PLLVDD NC NC
SM01000AG00 2A 300ohm@100mhz DCR 0.1

15P_0402_50V8J
17mA
2

1
0_0402_5% 1 2 N16X@ VGA@ C2005

1
VCC: 1.65 ~ 5.5V 1 N16X@ 2 SYS_PEX_RST_MON#_R L2003 HCB1608KF-301T20_2P VGA@ 4 2 VGA@
^WͺW>>sнs/ͺW>>s
5

Push Pull Output +GPU_PLLVDD 1 2 N17S@ C2004

Ϭ͘ϭhdžϮ͕ ϭϬhdžϭ͕ϰϳhdžϭ +3VS_1.8VSDGPU_MAIN

2
R2017 L2001 PBY160808T-300Y-N_2P
22U_0603_6.3V6M

22U_0603_6.3V6M
4.7U_0402_6.3V6M

ϯϬϬŽŚŵ;^ZϬ͘ϮͿdžϭ
VCC

2
PLT_RST_BUF# 1
N17S@ C2752

C2006

C2007

10K_0402_5% 1 1 1 SM010008A00 3000ma 30ohm@100mhz DCR 0.03

<11,30,31,38> PLT_RST_BUF# IN B
4SYS_PEX_RST_MON# 1 VGA@2
DGPU_HOLD_RST# 2 OUT Y
1 ƌLJƐƚĂůƐŵƵƐƚŚĂǀĞĂŵĂdž^ZŽĨϴϬŽŚŵ
GND

<12> DGPU_HOLD_RST# IN A +3VS_1.8VSDGPU_AON

4 CV266 ϮϬϭϲͬϭϭͬϭϬ 4
2 2 2
N16X@

VGA@

UV2 N17S@ ϮϬϬϳĐŚĂŶŐĞƚŽϮϮƵ&

2

NL17SZ08DFT2G_SC70-5 0.01U_0402_16V7K
ϭ͘EsƌĞĨĞƌĞŶĐĞĚĞƐŝŐŶ
3

N17S@ 2 R2019
UV2 N16X@ +3VS_1.8VSDGPU_AON 0_0402_5% RV100
Ϯ͘dŽƉƐŝĚĞŽŶůLJϭ͘ϮŵŵŚŝŐŚ
MC74VHC1G08DFT2G_SC70-5 U2002 N17S@ 10K_0402_5% EĞĂƌ'Wh
5

SA00000OH00 N16X@ @
1

VCC: 2.0 ~ 5.5V SYS_PEX_RST_MON# 2

P

B 4
Push Pull Output
GPU_PEX_RST_HOLD# 1 Y PLTRST_VGA# <22> Security Classification Compal Secret Data Compal Electronics, Inc.
1

A
G

1 Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

MC74VHC1G08DFT2G_SC70-5 CV265 R2018
N16X PEG 1/9
3

VCC: 2.0 ~ 5.5V N16X@ 10K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Push Pull Output 0.01U_0402_16V7K N16X@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
EH5AW M/B LA-G521P
2

Add CV265,CV266 for wavefrom glitch MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 12, 2018 Sheet 21 of 57
A B C D E
 A B C D E

VRAM Interface MDA[15..0]

UGPU1 UGPU1 UGPU1 UGPU1

<26> MDA[15..0] MDA[31..16]

<26> MDA[31..16] MDA[47..32]
<27> MDA[47..32] MDA[63..48]
<27> MDA[63..48]
S IC N16S-GTR-S-A2 BGA 595P GPU ABO ! S IC N17S-G1-A1 BGA 595P GPU ABO ! S IC N17S-G0-A1 BGA 595P GPU ABO ! S IC N17S-G2-A1 BGA 595P GPU ABO !
UGPU1B N16SGTR@ N17SG1@ N17SG0@ N17SG2@
SA00009FP40 SA0000ANV10 SA0000CC920 SA0000CCB20

Part 2 of 6
Vinafix.com CMDA[31..0] <26,27>
MDA0 E18 C27 CMDA0
1 FBA_D00 FBA_CMD0 1
MDA1 F18 C26 CMDA1
MDA2 E16 FBA_D01 FBA_CMD1 E24 CMDA2
MDA3 F17 FBA_D02 FBA_CMD2 F24 CMDA3
MDA4 D20 FBA_D03 FBA_CMD3 D27 CMDA4
MDA5 D21 FBA_D04 FBA_CMD4 D26 CMDA5
MDA6 F20 FBA_D05 FBA_CMD5 F25 CMDA6
MDA7 E21 FBA_D06 FBA_CMD6 F26 CMDA7
MDA8 E15 FBA_D07 FBA_CMD7 F23 CMDA8
MDA9 D15 FBA_D08 FBA_CMD8 G22 CMDA9
MDA10 F15 FBA_D09 FBA_CMD9 G23 CMDA10 +1.35VSDGPU
MDA11 F13 FBA_D10 FBA_CMD10 G24 CMDA11
MDA12 C13 FBA_D11 FBA_CMD11 F27 CMDA12 +3VS
MDA13 B13 FBA_D12 FBA_CMD12 G25 CMDA13 CMDA14 2 VGA@ 1
MDA14 E13 FBA_D13 FBA_CMD13 G27 CMDA14 RV87 10K_0402_5%
MDA15 D13 FBA_D14 FBA_CMD14 G26 CMDA15 CMDA30 2 VGA@ 1
MDA16 B15 FBA_D15 FBA_CMD15 M24 CMDA16 RV88 10K_0402_5%

1
MDA17 C16 FBA_D16 FBA_CMD16 M23 CMDA17

Co
FBA_D17 FBA_CMD17

1
MDA18 A13 K24 CMDA18 RV108
MDA19 A15 FBA_D18 FBA_CMD18 K23 CMDA19 CMDA13 2 VGA@ 1 RV106 10K_0402_5%
MDA20 B18 FBA_D19 FBA_CMD19 M27 CMDA20 RV89 10K_0402_5% 10K_0402_5% @
MDA21 A18 FBA_D20 FBA_CMD20 M26 CMDA21 CMDA29 2 VGA@ 1 @

2
MDA22 A19 FBA_D21 FBA_CMD21 M25 CMDA22 RV90 10K_0402_5%

PJT138KA 2N SOT363-6
2
MDA23 C19 FBA_D22 FBA_CMD22 K26 CMDA23
FBA_D23 FBA_CMD23 Power Side PU to +3VS_1.8VSDGPU_AON

3
MDA24 B24 K22 CMDA24
MDA25 C23 FBA_D24 FBA_CMD24 J23 CMDA25 5 G
D
RV188

mp
MDA26 A25 FBA_D25 FBA_CMD25 J25 CMDA26 S 0_0402_5%

6
MDA27 A24 FBA_D26 FBA_CMD26 J24 CMDA27 QV7A 1 VGA@ 2 VGA_CORE_PG

4
MDA28 A21 FBA_D27 FBA_CMD27 K27 CMDA28 2 G @
D

MDA29 B21 FBA_D28 FBA_CMD28 K25 CMDA29 QV7B S

MDA30 C20 FBA_D29 FBA_CMD29 J27 CMDA30 PJT138KA 2N SOT363-6

1
MDA31 C21 FBA_D30 FBA_CMD30 J26 CMDA31 @ UV10 N16X@
MDA32 R22 FBA_D31 FBA_CMD31 MC74VHC1G08DFT2G_SC70-5
MDA33 R24 FBA_D32 D19 FBA_DBI0 SA00000OH00
FBA_D33 FBA_DQM0 FBA_DBI0 <26>
INTERFACE A

2 MDA34 T22 D14 FBA_DBI1 DV10 N17S@ VCC: 2.0 ~ 5.5V 2

al
FBA_D34 FBA_DQM1 FBA_DBI2 FBA_DBI1 <26>
MDA35 R23 C17 RB751S40T1G_SOD523-2 Push Pull Output
FBA_D35 FBA_DQM2 FBA_DBI3 FBA_DBI2 <26>
MDA36 N25 C22 +3VS_1.8VSDGPU_AON
FBA_D36 FBA_DQM3 FBA_DBI4 FBA_DBI3 <26>
MDA37 N26 P24 1 2
MEMORY

FBA_D37 FBA_DQM4 FBA_DBI5 FBA_DBI4 <27>

MDA38 N23 W24
FBA_DBI5 <27>
VCC: 1.65 ~ 5.5V
MDA39 N24 FBA_D38 FBA_DQM5 AA25 FBA_DBI6
FBA_DBI6 <27> Push Pull Output

5
MDA40 V23 FBA_D39 FBA_DQM6 U25 FBA_DBI7 RV103
FBA_D40 FBA_DQM7 FBA_DBI7 <27>

Co
MDA41 V22 10K_0402_1%

VCC
MDA42 T23 FBA_D41 F19 DQSA#0 T254 @ 2 @ 1 DGPU_MAIN_EN 1
FBA_D42 FBA_DQS_RN0 <21,40> 3_1.8VSDGPU_MAIN_EN IN B PEX_VDD_EN
MDA43 U22 C14 DQSA#1 T249 @ 1 4
FBA_D43 FBA_DQS_RN1 OUT Y PEX_VDD_EN <40,52>
MDA44 Y24 A16 DQSA#2 T252 @ 2

GND
MDA45 AA24 FBA_D44 FBA_DQS_RN2 A22 DQSA#3 T253 @ CV231 @ IN A UV10
MDA46 Y22 FBA_D45 FBA_DQS_RN3 P25 DQSA#4 T255 @ N17S@
.1U_0402_16V7K
MDA47 AA23 FBA_D46 FBA_DQS_RN4 W22 DQSA#5 T256 @ 2 NL17SZ08DFT2G_SC70-5

3
MDA48 AD27 FBA_D47 FBA_DQS_RN5 AB27 DQSA#6 T250 @
FBA_D48 FBA_DQS_RN6

nfi
MDA49 AB25 T27 DQSA#7 T251 @
MDA50 AD26 FBA_D49 FBA_DQS_RN7 DV7 N17S@
FBA_D50 FBA_EDC0 DGPU_PWR_EN <12,40>
MDA51 AC25 E19 RB751S40T1G_SOD523-2
FBA_D51 FBA_DQS_WP0 FBA_EDC1 FBA_EDC0 <26> GPU_OVERT#
MDA52 AA27 C15 1 2 RV189 N17S@ PVT 03/09
FBA_D52 FBA_DQS_WP1 FBA_EDC2 FBA_EDC1 <26> <21,36> GPU_OVERT#
MDA53 AA26 B16 2.2K_0402_5%
FBA_D53 FBA_DQS_WP2 FBA_EDC3 FBA_EDC2 <26>
MDA54 W26 B22 SD028220180
FBA_D54 FBA_DQS_WP3 FBA_EDC4 FBA_EDC3 <26>
MDA55 Y25 R25
FBA_EDC4 <27>

de
MDA56 R26 FBA_D55 FBA_DQS_WP4 W23 FBA_EDC5 +3VS_1.8VSDGPU_AON RV189 1 N16X@ 2 1K_0402_1%
FBA_D56 FBA_DQS_WP5 FBA_EDC6 FBA_EDC5 <27> NVVDD_EN <53>
MDA57 T25 AB26 CV230
FBA_D57 FBA_DQS_WP6 FBA_EDC7 FBA_EDC6 <27>
MDA58 N27 T26 0.1U_0201_10V6K 2 1
FBA_D58 FBA_DQS_WP7 FBA_EDC7 <27>
MDA59 R27 2 1 1
MDA60 V26 FBA_D59 @ @ DV11 CV263
FBA_D60

5
MDA61 V27 RB751S40T1G_SOD523-2 .1U_0402_16V7K
MDA62 W27 FBA_D61 QV6A VGA@

VCC
nti
FBA_D62

3
MDA63 W25 PLTRST_VGA# 1 PJT138KA 2N SOT363-6 2
FBA_D63 <21> PLTRST_VGA# IN B
D24 4 5
D
G @
FBA_CLK0 FBA_CLK0 <26> OUT Y
F16 D25 1 @ 2 2 Near Power PWM IC

GND
+3VS_1.8VSDGPU_AON
S
+FB_PLLAVDD FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# <26> IN A
P22 RV102

4
6
3 FB_PLLAVDD_2 N22 10K_0402_5% DV11 change to @ for wavefrom glitch 3
FBA_CLK1 FBA_CLK1 <27> VGA_CORE_PG
D23 M22 2
D
T97 @ FB_VREF G UV9
FBA_CLK1# <27> <21> GC6_FB_EN1V8 VGA_CORE_PG <53>

3
FB_VREF_PROBE FBA_CLK1_N NL17SZ08DFT2G_SC70-5

al
S

D18 QV6B @ VCC: 1.65 ~ 5.5V

FBA_WCK01 <26>

1
R2028 H22 FB_REFPLL_AVDD FBA_WCK01 C18 PJT138KA 2N SOT363-6
FB_DLLAVDD FBA_WCK01_N FBA_WCK01# <26> Push Pull Output
10K_0402_5% D17 @
FB_CLAMP GNDS_SENSE FBA_WCK23 FBA_WCK23 <26>
1 N16X@ 2 F3 D16
FB_CLAMP FBA_WCK23_N FBA_WCK23# <26>
T24 Thermal shutdown protection
FBA_WCK45 FBA_WCK45 <27>
R2020 60.4_0402_1% U24
FBA_CMD34 FBA_WCK45_N FBA_WCK45# <27>
1 @ 2 F22 V24 change to @ for wavefrom glitch
FBA_CMD35 FBA_CMD34 FBA_WCK67 FBA_WCK67 <27>
+1.35VSDGPU 1 @ 2 J22 V25
FBA_CMD35 FBA_WCK67_N FBA_WCK67# <27>
R2022 60.4_0402_1%
UV9 N16X@ QV6 N16X@
MC74VHC1G08DFT2G_SC70-5 2N7002KDW_SOT363-6
SA00000OH00 SB00000EO00
GM108-ES-S-A1_FCBGA595 VCC: 2.0 ~ 5.5V
@ Push Pull Output

+PEX_IOVDDQ
15+55mA
Place Under F16 P22
1
L2002
2 VGA@
PBY160808T-300Y-N_2P
+FB_PLLAVDD
Esϭϱdž'ͲϬϲϴϬϯͲsϬϯ
22U_0603_6.3V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

Esϭϲdž'ͲϬϳϭϱϴͲsϬϰ
VGA@

VGA@

C2009 N17S@

C2736 N17S@
.1U_0402_16V7K

.1U_0402_16V7K

1 1 1 1 1
C2008 ͲϬϴϯϮϵͲϬϬϭͺsϬϭ
C2011

C2010

VGA@
2 2 2 2 2
4 4

Place Near GPU Place Under H22

SM010008A00 3000ma 30ohm@100mhz DCR 0.03

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X VRAM 2/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Tuesday, January 22, 2019 Sheet 22 of 57
A B C D E
 A B C D E

R4974 1 N16X@ 2 0_0402_5%

R4965
+3VS_1.8VSDGPU_AON
Dh>d/>s>^dZW^ +3VS_1.8VSDGPU_MAIN
0_0402_5% +3VS_1.8VSDGPU_AON R4973 1 N17S@ 2 0_0402_5%
UGPU1C GPCPLL_AVDD 1 N17S@ 2
+GPU_PLLVDD +3VS_1.8VSDGPU_R
strap0 strap1 strap2 strap3 strap4 strap5
Part 3 of 6 F11 C2751 1 2 0.1U_0201_10V6K
GPCPLL_AVDD NC

1
AC3 AD10 N17S@
AC4 NC IFPA_L3 NC AD7 R2029 R2030 R2031 R2032 R2033 R4972 R2035 R2036 R2037
Y4 NC IFPA_L3_N NC B19 N16X@ X76@ X76@ @ @ @ N17S@ N17S@ N17S@
Y3 NC IFPA_L2 FBA_CMD32 V5 49.9K_0402_1% 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 10K_0402_1% 10K_0402_1% 100K_0402_5% 100K_0402_5% 100K_0402_5%
AA3 NC IFPA_L2_N RSV_XVDD_63 NC
V6

2
NC IFPA_L1 RSV_XVDD_64 NC

Vinafix.com
AA2 G1
AB1 NC IFPA_L1_N XVDD NC G2 STRAP0
NC IFPA_L0 XVDD NC

NC
AA1 G3 STRAP1
AA4 NC IFPA_L0_N XVDD NC
G4 STRAP2 ROM_SI
AA5 NC IFPA_AUX_SCL XVDD NC G5 STRAP3 ROM_SO
1 NC IFPA_AUX_SDA_N XVDD NC
G6 STRAP4 ROM_SCLK 1
XVDD NC G7 STRAP5
XVDD NC
AB5 IFPB_L3
V1
AB4 NC XVDD NC
V2
IFPB_L3_N

1
AB3 NC XVDD NC W1
NC IFPB_L2 XVDD NC
AB2 IFPB_L2_N W2 R2038 R2039 R2040 R2041 R2042 R4971 R2044 R2045 R2046 R2046 N17S@
AD3 NC XVDD NC W3 X76@ X76@ X76@ N17S@ N17S@ N17S@ X76@ @ N16X@ 100K_0402_5%
NC IFPB_L1 XVDD NC
AD2 IFPB_L1_N W4 4.99K_0402_1% 45.3K_0402_1% 15K_0402_1% 100K_0402_5% 100K_0402_5% 100K_0402_5% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% SD028100380
AE1 NC XVDD NC
IFPB_L0

2
AD1 NC R2036 N16X@
IFPB_L0_N
AD4 NC 4.99K_0402_1%
NC IFPB_AUX_SCL
AD5 IFPB_AUX_SDA_N D11 R2050 1 @ 2 10K_0402_5% SD034499180
NC BUFRST_N N17X Straps N16X Straps
NC NC D10
T2
NC XVDD NV_GPIO8
T3 E9
NC XVDD GPIO8 NV_GPIO8 <21>
T1

Co
NC XVDD
R1 E10
NC XVDD NC MX110 Decive ID : N16V-GMR1 0x174E
GENERAL
R2
LVDS/TMDS

XVDD
R3 NC
NC XVDD NC
F10
Multi strap table MX130 Decive ID : N16S-GTR 0x174D
N2
NC XVDD
N3 XVDD GPU VRAM RANK X76 Freq Memory Size Memory Config strap2 strap5 ROM_SI ROM_SO ROM_SCLK
NC strap0 strap1 strap3 strap4
D1 STRAP0 Voltage
STRAP0 D2 STRAP1
V3 STRAP1 E4 STRAP2 X76793BOL03 0x8 (SA00009TV50) Micron MT51J256M32HF-70:B PU 4.99K

mp
V4 NC XVDD STRAP2 E3 STRAP3
U3 NC XVDD STRAP3 D3 STRAP4 X76793BOL04 0x9 (SA00009U160) Hynix H5GC8H24AJR-R0C PU 10K
U4 NC XVDD STRAP4 C1 STRAP5 N16V-GMR1
NC XVDD STRAP5 NC
T4 R2051 +1.35V
T5 NC XVDD
40.2K_0402_1%
N16S-GTR
R4 NC XVDD NC F6 MULTI_STRAP_REF0_GND 1 N16X@ 2 256Mx32x2 NC NC
2.5GHz PU 49.9K NC NC NC PU 4.99K PD 4.99K
R5 NC XVDD MULTI_STRAP_REF0_GND F4 2G
NC XVDD VDDS_SENSE NC
F5
2 NC NC 2
X76739BOL04 0x0 (SA000094R30) Samsung K4G80325FB-HC03 PD 4.99K

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N1
NC XVDD
M1 X76739BOL05 0x5(SA00009ZG20) Hynix H5GC8H24MJR-T2C PD 30.1K
NC XVDD
M2 F12
NC XVDD THERMDP
M3 X76739BOL06 0x1 (SA000096K30) Micron MT51J256M32HF-60:A PD 10K
NC XVDD
K2 E12
NC XVDD THERMDN
K3
NC XVDD

Co
K1
NC XVDD
J1
NC XVDD

M4 F2 VCCSENSE_VGA
M5 NC XVDD VDD_SENSE VCCSENSE_VGA <53> Multi strap table MX150 Decive ID : N17S-G1-A1 0x1D10
NC XVDD GPU VRAM RANK X76 Freq Memory Size Memory Config ROM_SI ROM_SO ROM_SCLK
L3 strap0 strap1 strap2 strap3 strap4 strap5
NC XVDD Voltage
L4
NC XVDD

nfi
K4 X76793BOL01 PU 100K
NC XVDD 0x4 (SA00009TV50) Micron MT51J256M32HF-70:B PD 100K PD 100K
K5 X76793BOL02 PU 100K PU 100K
J4 NC XVDD F1 VSSSENSE_VGA 0x5 (SA00009U160) Hynix H5GC8H24AJR-R0C PD 100K
NC XVDD GND_SENSE VSSSENSE_VGA <53>
N17S- G1 +1.35V PU 100K
PU 100K

de
J5 3.0GHz 256Mx32x2
PD 100K PU 100K
PD 100K
N4 NC XVDD 2G
N5 NC XVDD TEST X76739BOL07 0x0 (SA000092D00) Samsung K4G80325FB-HC28 PD 100K PD 100K PD 100K
NC XVDD
P3 AD9 TESTMODE R2054 1 VGA@ 2 10K_0402_5% X76739BOL08 0x2 (SA00009U110) Hynix H5GC8H24MJR-R0C PD 100K PU 100K PD 100K
P4 NC XVDD NVJTAG_SEL TESTMODE
AE5 JTAG_TCK_VGA PAD @ T258
NC XVDD JTAG_TCK AE6 JTAG_TDI PAD @ T257 X76739BOL09 0x1 (SA00009TV10) Micron MT51J256M32HF-70:A PU 100K PD 100K
PD 100K

nti
JTAG_TDI AF6 JTAG_TDO PAD @ T260
J2 JTAG_TDO AD6 JTAG_TMS PAD @ T259
J3 NC XVDD
NC XVDD
JTAG_TMS
JTAG_TRST_N
AG4 JTAG_RST R2053 1 VGA@ 210K_0402_5% Esϭϲdž^ƚƌĂƉƐƐĞƚ ƚ ŝ Ő
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H3
H4 NC XVDD
SERIAL

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NC XVDD
D12
ROM_CS_N B12 ROM_SI
ROM_SI A12 ROM_SO
ROM_SO C12 ROM_SCLK
ROM_SCLK

GM108-ES-S-A1_FCBGA595 Esϭϳ^'ͲϬϳϳϴϱͲϬϬϭͺsϬϳ ͲϬϴϯϮϵͲϬϬϭͺsϬϮ

@

VGA Power Sequence (N16X)

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4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X LVDS 3/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 23 of 57
A B C D E
 A B C D E

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Vinafix.com
1 1

+3VS_1.8VSDGPU_MAIN

+1.35VSDGPU
UGPU1D
+PEX_IOVDDQ +1.05VS_1.0VSDGPU
Esϭϲdž'ͲϬϳϭϱϴͲsϬϱ
3.24A Part 4 of 6
1.275A RV149
B26 PEX_HVDD AA10 0_0805_5% 2 N16X@ 1
FBVDDQ_01 PEX_IOVDDQ_1

VGA@

VGA@

VGA@
C25 AA12 RV150

N17S@

N17S@

N17S@

N17S@

N17S@
10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M
0.1U_0201_10V6K

0.1U_0201_10V6K
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
FBVDDQ_02 PEX_IOVDDQ_2

VGA@
N17S@ C2732

N17S@ C2733

N17S@ C2727

N17S@ C2726

N16X@ C2039

N16X@ C2040

VGA@ C2032

VGA@ C2033

N16X@ C2021

N16X@ C2022
E23 AA13 0_0805_5% 2 N17S@ 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 2 2 1 1 1 1 1 1 1
1

1
E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19

Co
2

2
2 2 2 2 2 2 1 1 FBVDDQ_06 PEX_IOVDDQ_6 2 2 2 2 2 2 2

C2013

C2737

C2754

C2755

C2014

C2738

C2016

C2739

C2017
G13 AA20
G14
G15
FBVDDQ_07
FBVDDQ_08
PEX_IOVDDQ_7
PEX_IOVDDQ_8
AA21
AB22
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Under GPU G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
FBVDDQ_10 PEX_IOVDDQ_10 hŶĚĞƌ'Wh EĞĂƌ'Wh
G18 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25

10U_0402_6.3V6M
FBVDDQ_12 PEX_IOVDDQ_12
N17S@ C2734

N17S@ C2735

VGA@ C2045

VGA@ C2047
G20 AF26
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 1 1 1 FBVDDQ_13 PEX_IOVDDQ_13 DŝĚǁĂLJ'WhΘWŽǁĞƌƐƵƉƉůLJ
Under GPU G21 AF27

mp
H24 FBVDDQ_14 FBVDDQ PEX_IOVDDQ_14
H26 FBVDDQ_AON
EĞĂƌ'Wh DŝĚǁĂLJ'WhΘWŽǁĞƌƐƵƉƉůLJ
2

C2021 N17S@ C2039 N17S@ 2 2 2 J21 FBVDDQ_AON PEX_DVDD AA22

FBVDDQ_AON PEX_IOVDD_1 +1.05VS_1.0VSDGPU
1U 6.3V M X5R 0201 4.7U_0402_6.3V6M K21 AB23

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
FBVDDQ_AON PEX_IOVDD_2

VGA@ C2740

N17S@ C2741

VGA@ C2742

N17S@ C2743

N17S@ C2744

N17S@ C2745

N17S@ C2746
SE00000UC00 SE00000SO00 L22 AC24

1U_0201_6.3V6M
FBVDDQ_19 PEX_IOVDD_3 1 1 1 1 1

1
Near GPU L24 AD25

POWER
C2022 N17S@ C2040 N17S@ L26 FBVDDQ_20 PEX_IOVDD_4 AE26
1U 6.3V M X5R 0201 4.7U_0402_6.3V6M M21 FBVDDQ_21 PEX_IOVDD_5 AE27

2
2 SE00000UC00 SE00000SO00 N21 FBVDDQ_22 PEX_IOVDD_6 2 2 2 2 2 2

al
change 4.7u_0402 for downsize R21 FBVDDQ_23
T21 FBVDDQ_24
RV156 +1.35VSDGPU V21 FBVDDQ_25 +3VS_1.8VSDGPU_AON
0_0402_5% W21 FBVDDQ_26
FBVDDQ_27 hŶĚĞƌ'Wh
1 @ 2 1V8_AON G10
<51> FB_VDDQ_SENSE 1V8_AON3V3_AON G12

0.1U_0201_10V6K

0.1U_0201_10V6K
56mA

4.7U_0402_6.3V6M
VDD18 3V3_AON ͲϬϴϯϮϵͲϬϬϭͺsϬϭ

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VGA@ C2048

N17S@ C2753

VGA@ C2049

VGA@ C2050
G8

1U_0201_6.3V6M
Near DGPU VDD18 VDD33_3 G9
2 2 1 1

ͲϬϴϯϮϵͲϬϬϭͺsϬϮ VDD33_4

V7 1 1 2 2
W7 NC +1.35VSDGPU
AA6 NC
W6 NC FB_CAL_PD_VDDQ D22 FB_CAL_PD_VDDQ 1 VGA@ 2
NC FB_CAL_PD_VDDQ hŶĚĞƌ'Wh EĞĂƌ'Wh
+3VS_1.8VSDGPU_MAIN

nfi
Y6 40.2_0402_1% R2078
NC
FB_CAL_PU_GND C24 FB_CAL_PU_GND 1 VGA@ 2
FB_CAL_PU_GND 40.2_0402_1% R2079

0.1U_0201_10V6K

0.1U_0201_10V6K

4.7U_0402_6.3V6M
B25 FB_CAL_TERM_GND 2 VGA@

C2051

C2052

VGA@ C2053

VGA@ C2054
M7 FB_CAL_TERM_GND 1

1U_0201_6.3V6M
NC FB_CAL_TERM_GND 2 2 1 1
N7 60.4_0402_1% R2080

de
T6 NC
P6 NC
NC 1 1 2 2

VGA@

VGA@
+3VS_1.8VSDGPU_MAIN

T7
R7 IFPD_PLLVDD_2 hŶĚĞƌ'Wh EĞĂƌ'Wh
+3VS_1.8VSDGPU_AON
Esϭϲdž'ͲϬϳϭϱϴͲsϬϱ

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U6 NC
R6 IFPD_RSET AA8
286mA +PEX_PLL_HVDD RV158 2 N16X@ 1 0_0603_5%
NC PEX_PLL_HVDD_1 AA9 RV153

.1U_0402_16V7K
PEX_PLL_HVDD_2

VGA@ C2034
0_0402_5% 2 RV159 2 N17S@ 1 0_0603_5%
3 NC AB8 +PEX_SVDD 1 N16X@ 2 3
PEX_SVDD_3V3
C2036 1 2 4.7U_0402_6.3V6M N16X@

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J7 C2035 1 2 4.7U_0402_6.3V6M N16X@ 1
NC EĞĂƌ'Wh
K7
K6 NC NC AA14
H6 NC NC PEX_PLLVDD_1 AA15
J6 NC PEX_PLLVDD_2 +PEX_PLLVDD
NC
130mA RV146 2 N16X@ 1 0_0603_5% +1.05VS_1.0VSDGPU

4.7U_0402_6.3V6M
N16X@ C2041

C2042

N16X@ C2043
GM108-ES-S-A1_FCBGA595

1U_0201_6.3V6M
.1U_0402_16V7K

2 1 1
@
Esϭϲdž'ͲϬϳϭϱϴͲsϬϱ
1 2 2

N16X@
hŶĚĞƌ'Wh EĞĂƌ'Wh

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X POWER & GND 4/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 24 of 57
A B C D E
 A B C D E

Esϭϲdž'ͲϬϳϭϱϴͲsϬϱ

UGPU1F
+VGA_CORE +VGA_CORE
Part 6 of 6

Vinafix.com
UGPU1E K10 V18
K12 VDD_001 VDD_041 V16
A2 Part 5 of 6 K11 K14 VDD_002 VDD_040 V14
A26 GND_001 GND_057 K13 K16 VDD_003 VDD_039 V12
AB11 GND_002 GND_058 K15 K18 VDD_004 VDD_038 V10
1 GND_003 GND_059 VDD_005 VDD_037 1
AB14 K17 L11 U17

POWER
AB17 GND_004 GND_060 L10 L13 VDD_006VDDS VDDS VDD_036 U15
AB20 GND_005 GND_061 L12 L15 VDD_007 VDD_035 U13
AB24 GND_006 GND_062 L14 L17 VDD_008 VDD_034 U11
GND_007 GND_063 VDD_009VDDS VDDS VDD_033
AC2 L16 M10 T18
AC22 GND_008 GND_064 L18 M12 VDD_010 VDD_032 T16
AC26 GND_009 GND_065 L2 M14 VDD_011 VDD_031 T14
GND_010 GND_066 VDD_012VDDS VDDS VDD_030
AC5 L23 M16 T12
AC8 GND_011 GND_067 L25 M18 VDD_013 VDD_029 T10
AD12 GND_012 GND_068 L5 N11 VDD_014 VDD_028 R17
AD13 GND_013 GND_069 M11 N13 VDD_015 VDD_027 R15
AD15 GND_014 GND_070 M13 N15 VDD_016 VDD_026 R13
AD16 GND_015 GND_071 M15 N17 VDD_017 VDD_025 R11
AD18 GND_016 GND_072 M17 P10 VDD_018 VDD_024 P18
AD19 GND_017 GND_073 N10 P12 VDD_019 VDDS VDDS VDD_023 P16
AD21 GND_018 GND_074 N12 VDD_020 VDDS VDDS VDD_022 P14
AD22 GND_019 GND_075 N14 VDD_021

Co
AE11 GND_020 GND_076 N16
AE14 GND_021 GND_077 N18
AE17 GND_022 GND_078 P11
AE20 GND_023 GND_079 P13
AF1 GND_024 GND_080 P15
AF11 GND_025 GND_081
ͲϬϳϳϱϬͲϬϬϬͲsϬϮ
GND

P17
AF14 GND_026 GND_082 P2
AF17 GND_027 GND_083 P23
ͲϬϴϯϮϵͲϬϬϭͺsϬϭ

mp
AF20 GND_028 GND_084 P26 GM108-ES-S-A1_FCBGA595
AF23 GND_029 GND_085 P5 @
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16
B1 GND_034 GND_090 R18
B11 GND_035 GND_091 T11
2 B14 GND_036 GND_092 T13 2

al
B17 GND_037 GND_093 T15
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16
GND_043 GND_099

Co
E11 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047 GND_103 U5
E22 GND_048 GND_104 V11
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
GND_051 GND_107

nfi
E8 V17
H2 GND_052 GND_108 Y2
H23 GND_053 GND_109 Y23
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

GND
GND
AA7
AB7

de
nti
GM108-ES-S-A1_FCBGA595
@

3 3

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4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X POWER & GND 5/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 25 of 57
A B C D E
 A B C D E

GDDR5 Mode H Mapping

VRAM GDDR5 chips
MDA[63..0] Address 0..31
DATA Bus
32..63
Channel 0 BOT SIDE
<22,27> MDA[63..0]
CMDA[31..0] CMD0 CS#
<22,27> CMDA[31..0]
UV13 @ MF=0
CMD1 A3_BA3
MF=0 MF=1 MF=1 MF=0
CMD2 A2_BA0
A4 MDA0

Vinafix.com
FBA_EDC0 C2 DQ24 DQ0 A2 MDA1
CMD3 A4_BA2 <22> FBA_EDC0 FBA_EDC1 EDC0 EDC3 DQ25 DQ1
C13 B4 MDA2
X76 for N16X 2G VRAM CMD4 A5_BA1
<22> FBA_EDC1 FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 MDA3 BYTE0
<22> FBA_EDC2 FBA_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 MDA4
<22> FBA_EDC3 EDC3 EDC0 DQ28 DQ4
CMD5 WE# E2 MDA5
1
ZZZ ZZZ1 DQ29 DQ5 F4 MDA6 1
FBA_DBI0 D2 DQ30 DQ6 F2 MDA7
X7604@ X76793BOL03@ CMD6 A7_A8 <22> FBA_DBI0 FBA_DBI1 DBI0# DBI3# DQ31 DQ7
D13 A11 MDA8
<22> FBA_DBI1 FBA_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13
CMD7 A6_A11 MDA9
<22> FBA_DBI2 FBA_DBI3 DBI2# DBI1# DQ17 DQ9
Samsung_256Mx32x2 Micron_MT51J256M32HF-70:B P2 B11 MDA10
<22> FBA_DBI3 DBI3# DBI0# DQ18 DQ10
X76739BOL04 X76793BOL03 CMD8 ABI# B13 MDA11 BYTE1
FBA_CLK0 J12 DQ19 DQ11 E11 MDA12
<22> FBA_CLK0 FBA_CLK0# CK DQ20 DQ12
CMD9 A12_RFU J11 E13 MDA13
<22> FBA_CLK0# J3 CK# DQ21 DQ13 F11
ZZZ ZZZ2 CMDA14 MDA14
CKE# DQ22 DQ14 F13
X7605@ X76793BOL04@ CMD10 A0_A10 DQ23 DQ15
MDA15
U11 MDA16
CMDA2 H11 DQ8 DQ16 U13 MDA17
CMD11 A1_A9 BA0/A2 BA2/A4 DQ9 DQ17
Hynix_256Mx32x2 Hynix_ H5GC8H24AJR-R0C CMDA4 K10 T11 MDA18
CMDA3 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 MDA19
X76739BOL05 X76793BOL04 CMD12 RAS# BA2/A4 BA0/A2 DQ11 DQ19 BYTE2
CMDA1 H10 N11 MDA20
BA3/A3 BA1/A5 DQ12 DQ20 N13 MDA21
EĞǁ CMD13 RST# DQ13 DQ21
ZZZ M11 MDA22
K4 DQ14 DQ22 M13
X7606@ CMD14 CKE# CMDA6
A8/A7 A10/A0 DQ15 DQ23
MDA23
CMDA11 H5 U4 MDA24
A9/A1 A11/A6 DQ0 DQ24

Co
CMD15 CAS# CMDA10 H4 U2 MDA25
Micron_256Mx32x2 CMDA7 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MDA26
CMDA9 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MDA27
X76739BOL06 CMD16 CS# A12/RFU/NC DQ3 DQ27 BYTE3
N4 MDA28
A5 DQ4 DQ28 N2 MDA29
CMD17 A3_BA3 VPP/NC DQ5 DQ29
U5 M4 MDA30
X76 for N17S 2G VRAM CMD18 A2_BA0 VPP/NC DQ6 DQ30 M2 MDA31
DQ7 DQ31
CMD19 A4_BA2 RV131 2 VGA@ 1 1K_0402_1% J1 +1.35VSDGPU
FBA_SEN0 MF

mp
ZZZ ZZZ4 RV133 2 VGA@ 1 J10
J13 SEN B1
X7607@ X76793BOL01@ CMD20 A5_BA1 0_0402_5%
ZQ VDDQ
RV132 2 VGA@ 1 121_0402_1% D1
VDDQ F1
CMD21 WE# VDDQ
Samsung_256Mx32x2 Micron MT51J256M32HF-70:B CMDA8 J4 M1
CMDA12 G3 ABI# VDDQ P1
X76739BOL07 X76793BOL01 CMD22 A7_A8 RAS# CAS# VDDQ
CMDA0 G12 T1
CMDA15 L3 CS# WE# VDDQ G2
CMD23 A6_A11 CAS# RAS# VDDQ
ZZZ ZZZ3 CMDA5 L12 L2
WE# CS# VDDQ B3
2 X7608@ X76793BOL02@ CMD24 ABI# VDDQ
2

al
D3
VDDQ F3
CMD25 A12_RFU FBA_WCK01# VDDQ
Hynix_256Mx32x2 Hynix H5GC8H24AJR-R0C D5 H3
<22> FBA_WCK01# FBA_WCK01 D4 WCK01# WCK23# VDDQ K3
X76739BOL08 X76793BOL02 CMD26 A0_A10 <22> FBA_WCK01 WCK01 WCK23 VDDQ M3
FBA_WCK23# P5 VDDQ P3
EĞǁ CMD27 A1_A9 <22> FBA_WCK23# FBA_WCK23 WCK23# WCK01# VDDQ
ZZZ P4 T3
<22> FBA_WCK23 WCK23 WCK01 VDDQ
X7609@ CMD28 RAS# E5

Co
VDDQ N5
A10 VDDQ E10
CMD29 RST# VREFD VDDQ
Micron_256Mx32x2 U10 N10
+FBA_VREFC0 J14 VREFD VDDQ B12
X76739BOL09 CMD30 CKE# VREFC VDDQ D12
VDDQ F12
CMD31 CAS# VDDQ H12
CMDA13 J2 VDDQ K12
RESET# VDDQ M12

nfi
VDDQ P12
VDDQ T12
FBA_CLK0 FBA_CLK0# VDDQ G13
H1 VDDQ L13
VSS VDDQ
1

K1 B14
RV63 RV95 B5 VSS VDDQ D14
40.2_0402_1% 40.2_0402_1% G5 VSS VDDQ F14
L5 VSS VDDQ M14

de
VGA@ VGA@
T5 VSS VDDQ P14
2

B10 VSS VDDQ T14

D10 VSS VDDQ
1 VSS
0.01U_0402_16V7K

VGA@ G10
VSS
CV190

L10 A1
+1.35VSDGPU P10 VSS VSSQ C1
2 T10 VSS VSSQ E1
VSS VSSQ

nti
H14 N1
VSS VSSQ
1

RV136 K14 R1
549_0402_1% +1.35VSDGPU VSS VSSQ U1
VGA@ VSSQ H2
G1 VSSQ K2
3 +FBA_VREFC0 <27> VDD VSSQ 3
RV135 L1 A3
2

931_0402_1% G4 VDD VSSQ C3

FBA_VREFC_L 1 2 +FBA_VREFC0 L4 VDD VSSQ E3

al
C5 VDD VSSQ N3
VGA@ R5 VDD VSSQ R3
VDD VSSQ
1

1 C10 U3
RV56 R10 VDD VSSQ C4
VDD VSSQ
1

D 1.33K_0402_1% CV195 D11 R4

2 QV3 VGA@ 820PF_0402_50V7K G11 VDD VSSQ F5
<21> VRAM_VREF_CTL 2 VGA@ VDD VSSQ
G BSS138W-7-F_SOT323-3 L11 M5
2

VGA@ P11 VDD VSSQ F10

S
3

G14 VDD VSSQ M10

L14 VDD VSSQ C11
VDD VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
170-BALL VSSQ U12
VSSQ H13
SGRAM GDDR5 VSSQ K13
VSSQ A14
VSSQ C14
DA8335 Cap Q'ty VSSQ E14
+1.35VSDGPU +1.35VSDGPU 22U x2 VSSQ N14
10U x 6 VSSQ R14
VSSQ
1U x 10 VSSQ
U14
22U x 3 (unPOP) H5GC4H24AJR-R0C_BGA170
22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
VGA@ CV76

VGA@ CV192

N17S@ CV197

N17S@ CV198

N17S@ CV199

N17S@ CV200

1 1
1

1
N17S@ CV72

N17S@ CV196

N16X Cap Q'ty

10U x2
2

2 2
1U x 8
0.1U x 6
4 4

+1.35VSDGPU +1.35VSDGPU
CV201

CV202

CV203

CV204

CV205

CV207

CV206

CV208

CV210

CV209

N16X@ CV246

N16X@ CV247

N16X@ CV248

N16X@ CV249

N16X@ CV251

N16X@ CV250
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Security Classification Compal Secret Data Compal Electronics, Inc.

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

N17S@

N17S@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2018/01/10 2018/11/04 Title

Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X Lower Rank0 6/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 26 of 57
A B C D E
 A B C D E

GDDR5 Mode H Mapping

VRAM GDDR5 chips
MDA[63..0] Address 0..31
DATA Bus
32..63
Channel 1 BOT SIDE
<22,26> MDA[63..0]
CMDA[31..0] CMD0 CS#
<22,26> CMDA[31..0]
UV15 @ MF=1
CMD1 A3_BA3
MF=0 MF=1 MF=1 MF=0
CMD2 A2_BA0
A4 MDA56

Vinafix.com
FBA_EDC7 C2 DQ24 DQ0 A2 MDA57
CMD3 A4_BA2 <22> FBA_EDC7 FBA_EDC6 EDC0 EDC3 DQ25 DQ1
C13 B4 MDA58
<22> FBA_EDC6 FBA_EDC5 EDC1 EDC2 DQ26 DQ2
CMD4 A5_BA1 R13 B2 MDA59 BYTE7
<22> FBA_EDC5 FBA_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 MDA60
<22> FBA_EDC4 EDC3 EDC0 DQ28 DQ4
CMD5 WE# E2 MDA61
1 DQ29 DQ5 F4 MDA62 1
FBA_DBI7 D2 DQ30 DQ6 F2 MDA63
CMD6 A7_A8 <22> FBA_DBI7 FBA_DBI6 DBI0# DBI3# DQ31 DQ7
D13 A11 MDA48
<22> FBA_DBI6 FBA_DBI5 P13 DBI1# DBI2# DQ16 DQ8 A13
CMD7 A6_A11 MDA49
<22> FBA_DBI5 FBA_DBI4 DBI2# DBI1# DQ17 DQ9
P2 B11 MDA50
<22> FBA_DBI4 DBI3# DBI0# DQ18 DQ10
CMD8 ABI# B13 MDA51 BYTE6
FBA_CLK1 J12 DQ19 DQ11 E11 MDA52
<22> FBA_CLK1 FBA_CLK1# CK DQ20 DQ12
CMD9 A12_RFU J11 E13 MDA53
<22> FBA_CLK1# J3 CK# DQ21 DQ13 F11
CMDA30 MDA54
CKE# DQ22 DQ14 F13
CMD10 A0_A10 DQ23 DQ15
MDA55
U11 MDA40
CMDA19 H11 DQ8 DQ16 U13 MDA41
CMD11 A1_A9 BA0/A2 BA2/A4 DQ9 DQ17
CMDA17 K10 T11 MDA42
CMDA18 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 MDA43
CMD12 RAS# BA2/A4 BA0/A2 DQ11 DQ19 BYTE5
CMDA20 H10 N11 MDA44
BA3/A3 BA1/A5 DQ12 DQ20 N13 MDA45
CMD13 RST# DQ13 DQ21 M11 MDA46
K4 DQ14 DQ22 M13
CMD14 CKE# CMDA26
A8/A7 A10/A0 DQ15 DQ23
MDA47
CMDA23 H5 U4 MDA32
A9/A1 A11/A6 DQ0 DQ24

Co
CMD15 CAS# CMDA22 H4 U2 MDA33
CMDA27 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MDA34
CMDA25 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MDA35
CMD16 CS# A12/RFU/NC DQ3 DQ27 BYTE4
N4 MDA36
A5 DQ4 DQ28 N2 MDA37
CMD17 A3_BA3 +1.35VSDGPU VPP/NC DQ5 DQ29
U5 M4 MDA38
VPP/NC DQ6 DQ30 M2 MDA39
CMD18 A2_BA0 DQ7 DQ31
CMD19 A4_BA2 RV140 2 VGA@ 1 1K_0402_1% J1 +1.35VSDGPU
FBA_SEN2 MF

mp
RV145 2 VGA@ 1 J10
J13 SEN B1
CMD20 A5_BA1 0_0402_5%
ZQ VDDQ
RV141 2 VGA@ 1 121_0402_1% D1
VDDQ F1
CMD21 WE# VDDQ
CMDA24 J4 M1
CMDA31 G3 ABI# VDDQ P1
CMD22 A7_A8 RAS# CAS# VDDQ
CMDA21 G12 T1
CMDA28 L3 CS# WE# VDDQ G2
CMD23 A6_A11 CAS# RAS# VDDQ
CMDA16 L12 L2
WE# CS# VDDQ B3
2 CMD24 ABI# VDDQ
2

al
D3
VDDQ F3
CMD25 A12_RFU FBA_WCK67# VDDQ
D5 H3
<22> FBA_WCK67# FBA_WCK67 D4 WCK01# WCK23# VDDQ K3
CMD26 A0_A10 <22> FBA_WCK67 WCK01 WCK23 VDDQ M3
FBA_WCK45# P5 VDDQ P3
CMD27 A1_A9 <22> FBA_WCK45# FBA_WCK45 WCK23# WCK01# VDDQ
P4 T3
<22> FBA_WCK45 WCK23 WCK01 VDDQ
CMD28 RAS# E5

Co
VDDQ N5
A10 VDDQ E10
CMD29 RST# VREFD VDDQ
U10 N10
+FBA_VREFC0 J14 VREFD VDDQ B12
CMD30 CKE# <26> +FBA_VREFC0 VREFC VDDQ D12
VDDQ F12
CMD31 CAS# 1 VDDQ H12
CMDA29 J2 VDDQ K12
CV229 RESET# VDDQ M12

nfi
820PF_0402_50V7K 2 VDDQ P12
VGA@ VDDQ T12
VDDQ G13
H1 VDDQ L13
K1 VSS VDDQ B14
FBA_CLK1 FBA_CLK1# B5 VSS VDDQ D14
G5 VSS VDDQ F14
VSS VDDQ
1

L5 M14

de
RV96 RV62 T5 VSS VDDQ P14
40.2_0402_1% 40.2_0402_1% B10 VSS VDDQ T14
VGA@ VGA@ D10 VSS VDDQ
G10 VSS
2

L10 VSS A1
P10 VSS VSSQ C1
1 VSS VSSQ
0.01U_0402_16V7K

VGA@ T10 E1
VSS VSSQ
CV191

nti
H14 N1
K14 VSS VSSQ R1
2 +1.35VSDGPU VSS VSSQ U1
VSSQ H2
G1 VSSQ K2
3
L1 VDD VSSQ A3 3
G4 VDD VSSQ C3
L4 VDD VSSQ E3

al
C5 VDD VSSQ N3
R5 VDD VSSQ R3
C10 VDD VSSQ U3
R10 VDD VSSQ C4
D11 VDD VSSQ R4
G11 VDD VSSQ F5
L11 VDD VSSQ M5
P11 VDD VSSQ F10
G14 VDD VSSQ M10
L14 VDD VSSQ C11
VDD VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
VSSQ U12
DA8335 Cap Q'ty 170-BALL
VSSQ H13
22U x2 SGRAM GDDR5 VSSQ K13
10U x 6 VSSQ A14
+1.35VSDGPU +1.35VSDGPU VSSQ
1U x 10 VSSQ
C14
22U x 3 (unPOP) E14
VSSQ N14
VSSQ R14
VSSQ U14
22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

VSSQ
N16X Cap Q'ty
VGA@ CV217

VGA@ CV218

N17S@ CV219

N17S@ CV220

N17S@ CV221

N17S@ CV222

1 1
1

H5GC4H24AJR-R0C_BGA170
N17S@ CV215

N17S@ CV216

10U x2
1U x 8
2

2 2 0.1U x 6

4 +1.35VSDGPU 4
+1.35VSDGPU
N16X@ CV252

N16X@ CV253

N16X@ CV254

N16X@ CV255

N16X@ CV257

N16X@ CV256
0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
CV223

CV224

CV225

CV226

CV228

CV212

CV227

CV211

CV213

CV214

1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2
VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

N17S@

N17S@

2 2 2 2 2 2 2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X Lower Rank1 7/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 27 of 57
A B C D E
 A B C D E

>WKtZ/Zh/d
+3VS +LCDVDD +19VB +INVPW R_B+ WůĂĐĞĐůŽƐĞĚƚŽ:Wϭ
UX1
5 1
Vinafix.com
tсϴϬŵŝůƐ
tсϲϬŵŝůƐ tсϲϬŵŝůƐ
+LCDVDD
1U_0201_6.3V6M

IN OUT LX1 +3VS

1
CX1 2 1 1 HCB2012KF-221T30_0805
GND CX4 1 2
1 1
4 3 0.1U_0201_10V6K 3S@ 1 1
2 EN OC

1000P_0402_50V7K
CX5
@ SM01000EJ00 3000ma 1 1
SY6288C20AAC_SOT23-5 CX3 2 2 CX2 CX6 CX7
220ohm@100mhz
4.7U_0402_6.3V6M DCR 0.04 68P_0402_50V8J 0.1U_0201_10V6K .1U_0402_16V7K
2 2

@EMI@
@EMI@ @
<7> SOC_ENVDD 2 2
1

RX9
100K_0402_5%
@
2

Note: Unmount LX1 when panel boost

circuit was use. (2S battery cell)

<7>
<7>
<7>
<7>
EDP_TXP0
EDP_TXN0
EDP_TXP1
EDP_TXN1
CX8
CX9
CX10
CX11
1
1
1
1
2
2
2
2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C
EDP_TXP2_C
Co >WE>ŽŶŶ͘
+INVPW R_B+
W=60mils 1
1
JEDP1

mp
CX17 1 2 .1U_0402_16V7K 2 41
<7> EDP_TXP2 EDP_TXN2_C SOC_BKL_PW M 2 G1
CX16 1 2 .1U_0402_16V7K RX1 1 @ 2 100K_0402_5% 3 42
<7> EDP_TXN2 EDP_TXP3_C <7> SOC_BKL_PW M 3 G2
CX19 1 2 .1U_0402_16V7K 4 43
<7> EDP_TXP3 EDP_TXN3_C 4 G3
CX18 1 2 .1U_0402_16V7K @EMI@ 5 44
<7> EDP_TXN3 SOC_BKL_PW M 5 G4
CX12 1 2 220P_0402_50V7K 6 45
CX14 1 2 .1U_0402_16V7K EDP_AUXP_C @EMI@ BKOFF# 7 6 G5 46
<7> EDP_AUXP EDP_AUXN_C EDP_HPD 7 G6
<7> EDP_AUXN CX15 1 2 .1U_0402_16V7K BKOFF# CX13 1 2 220P_0402_50V7K 8
<36> BKOFF# 8
2
+LCDVDD 9 2

al
RX2 1 @ 2 10K_0402_5% 10 9
+3VS 11 10
2 @ 1
W=60mils 12 11
EDP_AUXN_C +3VS 12
100K_0402_5% 1 @ 2 RX3 RX12 0_0402_5% 13
100K_0402_5% 1 @ 2 RX4 EDP_AUXP_C EDP_AUXN_C 14 13
ƌĞƐĞƌǀĞĨŽƌ/ZĐĂŵĞƌĂ EDP_AUXP_C 14
15

Co
16 15
2 @ 1 EDP_HPD EDP_TXP0_C 17 16
<7> CPU_EDP_HPD EDP_TXN0_C 17
RX5 0_0402_5% 18
RX6 19 18
100K_0402_5% EDP_TXP1_C 20 19
2 1 EDP_TXN1_C 21 20
22 21

nfi
EDP_TXP2_C 23 22
dŽƵĐŚ ^ĐƌĞĞŶ EDP_TXN2_C 24 23
24
25
+5VS +3VS +TS_PW R EDP_TXP3_C 26 25
EDP_TXN3_C 27 26
RX7 1 @ 2 0_0603_5% 28 27

de
RX8 1 2 0_0603_5% USB20_P9 29 28
<13> USB20_P9 USB20_N9 29
30
<13> USB20_N9 30
31
32 31
dŽƵĐŚ ^ĐƌĞĞŶ +TS_PW R 32
33
TS_EN 34 33

nti
<12,36> TS_EN 34
+3VS 35
USB20_N7_CAMERA 36 35
USB20_P7_CAMERA 37 36
3 ĂŵĞƌĂ &ŽƌĂŵĞƌĂ DMIC_CLK_R
38 37
38
3
39
<32> DMIC_CLK_R DMIC_DATA_R 39
@EMI@ 40

al
USB20_N7 USB20_N7_CAMERA <32> DMIC_DATA_R 40
RX10 1 2 0_0402_5%
<13> USB20_N7
E-T_0871K-F40N-00L
@EMI@ CONN@
USB20_P7 RX11 1 2 0_0402_5% USB20_P7_CAMERA
<13> USB20_P7 SP010011Z00
DMIC_DATA_R
DMIC_CLK_R
WE͗^WϬϭϬϬϭϰϭϬ

3
DX1
@ESD@
YSLC05CH_SOT23-3

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 28 of 57
A B C D E
 A B C D E

+5VS W=40mils +HDMI_5V_OUT HDMI_C_CLKN RY40 1 EMI@ 2 5.6 +-5% 0402 HDMI_R_CLKN

RY28 1 2 2.2K_0402_5% SOC_DP1_CTRL_CLK

UY1 +3VS SOC_DP1_CTRL_CLK <7,29>
RY29 1 2 2.2K_0402_5% SOC_DP1_CTRL_DATA
SOC_DP1_CTRL_DATA <7,29> HDMI_C_CLKP HDMI_R_CLKP
3 RY41 1 EMI@ 2 5.6 +-5% 0402
OUT
1
1 RY27 1 2 2.2K_0402_5% HDMI_CTRL_DAT
IN

GND
2
2
CY9
0.1U_0201_10V6K Vinafix.com +HDMI_5V_OUT
RY30 1 2 2.2K_0402_5% HDMI_CTRL_CLK

1 1
AP2330W -7_SC59-3 HDMI_C_TX_N0 RY42 1 EMI@ 2 5.6 +-5% 0402 HDMI_R_TX_N0

port 0, 2 swap for INTEL HDMI HDMI_C_TX_P0 RY43 1 EMI@ 2 5.6 +-5% 0402 HDMI_R_TX_P0
<7> SOC_DP1_P2 CY14 2 1 0.1U_0201_10V6K HDMI_C_TX_P0 RY31 1 2 470_0402_5%
<7> SOC_DP1_N2 CY15 2 1 0.1U_0201_10V6K HDMI_C_TX_N0 RY32 1 2 470_0402_5%

<7> SOC_DP1_P1 CY12 2 1 0.1U_0201_10V6K HDMI_C_TX_P1 RY33 1 2 470_0402_5%

<7> SOC_DP1_N1 CY13 2 1 0.1U_0201_10V6K HDMI_C_TX_N1 RY34 1 2 470_0402_5%

<7> SOC_DP1_P0 CY10 2 1 0.1U_0201_10V6K HDMI_C_TX_P2 RY35 1 2 470_0402_5%

<7> SOC_DP1_N0 CY11 2 1 0.1U_0201_10V6K HDMI_C_TX_N2 RY36 1 2 470_0402_5%
HDMI_C_TX_N1 HDMI_R_TX_N1

Co
RY44 1 EMI@ 2 5.6 +-5% 0402
<7> SOC_DP1_P3 CY16 2 1 0.1U_0201_10V6K HDMI_C_CLKP RY37 1 2 470_0402_5%
<7> SOC_DP1_N3 CY17 2 1 0.1U_0201_10V6K HDMI_C_CLKN RY38 1 2 470_0402_5%

HDMI_C_TX_P1 RY45 1 EMI@ 2 5.6 +-5% 0402 HDMI_R_TX_P1

mp +3VS

6
D
2
G 2N7002KDW _SOT363-6
2 QY5A HDMI_C_TX_N2 RY46 1 EMI@ 2 5.6 +-5% 0402 HDMI_R_TX_N2 2

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S

1
+3VS
HDMI_C_TX_P2 RY47 1 EMI@ 2 5.6 +-5% 0402 HDMI_R_TX_P2

Co
2
G

SOC_DP1_CTRL_DATA 1 6 HDMI_CTRL_DAT
<7,29> SOC_DP1_CTRL_DATA
S

PJT138KA 2N SOT363-6

nfi
QY7B
5

+3VS
,D/ ĐŽŶŶĞĐƚŽƌ
G

SOC_DP1_CTRL_CLK 4 3 HDMI_CTRL_CLK
<7,29> SOC_DP1_CTRL_CLK
S

JHDMI1

de
PJT138KA 2N SOT363-6 HDMI_HPD 19
18 HP_DET
QY7A +HDMI_5V_OUT +5V
17
DDC/CEC_GND

2
HDMI_CTRL_DAT 16
RY39 HDMI_CTRL_CLK 15 SDA
1M_0402_5% 14 SCL

nti
13 Utility
CEC

5
HDMI_R_CLKN 12

G
1
QY5B 11 CK-
3 2N7002KDW _SOT363-6 HDMI_R_CLKP 10 CK_shield 3
HDMI_R_TX_N0 9 CK+
SOC_DP1_HPD 4 3 HDMI_HPD 8 D0-

al S
<7> SOC_DP1_HPD HDMI_R_TX_P0 D0_shield

D
7
HDMI_R_TX_N1 6 D0+
D1-

2
5
RY11 HDMI_R_TX_P1 4 D1_shield 23
HDMI_R_TX_N2 3 D1+ GND1 22
100K_0402_5% D2- GND2
2 21
HDMI_R_TX_P2 1 D2_shield GND3 20

1
D2+ GND4
ACON_HMRBL-AK120D
DC232007600
CONN@
SYMBOL:DC232004700

DY3 ESD@ DY2 ESD@ DY1 ESD@

ĨŽƌ^ƚĞƐƚ
HDMI_R_TX_N11   9 HDMI_R_TX_N1 HDMI_R_TX_N0 1   9 HDMI_R_TX_N0 HDMI_HPD 6 3 HDMI_CTRL_DAT
I/O4 I/O2
HDMI_R_TX_P12   8 HDMI_R_TX_P1 HDMI_R_TX_P0 2   8 HDMI_R_TX_P0

HDMI_R_TX_N24   7 HDMI_R_TX_N2 HDMI_R_CLKN 4   7 HDMI_R_CLKN 5 2

VDD GND
HDMI_R_TX_P25   6 HDMI_R_TX_P2 HDMI_R_CLKP 5   6 HDMI_R_CLKP

3  3  HDMI_CTRL_CLK 4 1
4 I/O3 I/O1 +HDMI_5V_OUT 4

8 8 AZC199-04S.R7G_SOT23-6

TVW DF1004AD0 TVW DF1004AD0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: W ednesday, July 18, 2018 Sheet 29 of 57
A B C D E
 A B C D E

LDO mode
>EͲZd>ϴϰϭϭ W=60mil RL1 2 LDO@ 1 0_0603_5% W=60mil
300mA
+LAN_VDD +3V_LAN
W=60mil
1.4A
LL1 SWR@ IDC=1200mA
+REGOUT 1 2
+3VALW +3V_LAN 2.2UH_HPC252012NF-2R2M_20%

4.7U_0402_6.3V6M
CL1

1U_0201_6.3V6M
RL2 1 Using for Switch mode 1 1 1 1 1 1 1 1 1 1 1 1 1
Vinafix.com

0.1U_0201_10V6K
CL2 LDO@

0.1U_0201_10V6K
CL28 SWR@

0.1U_0201_10V6K
CL3

0.1U_0201_10V6K
CL4

0.1U_0201_10V6K
CL5

0.1U_0201_10V6K
CL6

0.1U_0201_10V6K
CL7

0.1U_0201_10V6K
CL9

0.1U_0201_10V6K
CL11

0.1U_0201_10V6K
CL12

0.1U_0201_10V6K
CL13
CL8
0_0805_5%
1 @ 2 The trace length from
Lx to PIN48 (REGOUT)
2 2 2 2 2 2 2 2 2 2 CL10 2 2 2 2
1
60mil 60mil and from C to Lx must
1
UL1 < 200mils. 4.7U_0402_6.3V6M
5 1
IN OUT
2
GND
WůĂĐĞ ŶĞĂƌ WŝŶ ϯ͕ϴ͕ϯϯ͕ϰϲ WůĂĐĞŶĞĂƌWŝŶϮϬ Using for Switch mode WůĂĐĞ ŶĞĂƌ WŝŶ ϭϭ͕ϯϮ͕ϰϴ
4 3 11/27: P/N change to SH00000RT00
EN OC
1 The trace length
CL14 SY6288C20AAC_SOT23-5 ( S COIL 2.2UH +-20% from C to
HPC252012NF-2R2M 1.3A) PIN34,35(VDDREG)
1U_0201_6.3V6M LAN_PWR_EN
2 LAN_PWR_EN <36> must < 200mils.

UL2
From EC
reserve EC_PME# pull high 100K to +3VALW_EC Power Manahement/Isolation
High active. ISOLATEB 31

Co
2 1 LAN_PME# 39 ISOLATEBPIN
EN threshold voltage min:1.2V <36> EC_PME# LANWAKEB
RL3 0_0402_5% Card Reader
typ:1.6V max:2.0V SD_D0 SD_D0_R
Current limit threshold 1.5~2.8A DVT modify 12/04
+3V_LAN RL8 1 2 10K_0402_5% 15 RL9 1 @ 2 0_0402_5% SD_D0_R <38>
for WOL pull high to +3V_LAN PCI-Express SD_D0/MS_D1 14 SD_D1 RL4 1 @ 2 0_0402_5% SD_D1_R
CLK_R_PCIE_P1 SD_D1 SD_CLK SD_CLK_R SD_D1_R <38>
+3V_LAN Rising time must >0.5ms and <100ms <11,38> CLK_PCIE_P1 RL29 1 2 0_0201_5% 23 16 RL10 1 2 10_0402_5% SD_CLK_R <38>
RL30 1 2 0_0201_5% CLK_R_PCIE_N1 24 REFCLK_P SD_CLK/MS_D0 17 SD_CMD RL5 1 @ 2 0_0402_5% SD_CMD_R
<11,38> CLK_PCIE_N1 REFCLK_N SD_CMD/MS_D2 SD_D3 SD_D3_R SD_CMD_R <38>
18 RL6 1 @ 2 0_0402_5%
PLT_RST_BUF# SD_D3/MS_D3 SD_D2 SD_D2_R SD_D3_R <38> 2
30 19 RL7 1 @ 2 0_0402_5%

mp
<11,21,31,38> PLT_RST_BUF# CLKREQ_PCIE#1 PERSTBPIN SD_D2/MS_CLK SD_WP SD_D2_R <38>
29 28 CL16
WhĂƚW,ƐŝĚĞ <11,38> CLKREQ_PCIE#1 CLKREQBPIN SD_WP/MS_BS
5P_0402_50V8C
CL17 1 2 .1U_0402_16V7K PCIE_CRX_C_DTX_P5 25 1
<13,38> PCIE_CRX_DTX_P5 PCIE_CRX_C_DTX_N5 HSOP @EMI@
CL15 1 2 .1U_0402_16V7K 26
<13,38> PCIE_CRX_DTX_N5 21 HSON 42 SD_CD#
<13> PCIE_CTX_C_DRX_P5 HSIP SD_CD# SD_CD# <38> ĐůŽƐĞƚŽ ƉŝŶϭϳ
22 43
<13> PCIE_CTX_C_DRX_N5 HSIN MS_CD#
2 Transceiver Interface 2

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LAN_MIDI0+ 1
LAN_MIDI0- 2 MDIP0
LAN_MIDI1+ 4 MDIN0
+3V_LAN LAN_MIDI1- 5 MDIP1 48 +3V_LAN
SWR mode LAN_MIDI2+ 6 MDIN1 AVDD33 11 WƌŽƚĞĐƚĐŽƚĂĐƚ ĂƌĚĐŽŶƚĂĐƚ
+3V_LAN LAN_MIDI2- 7 MDIP2 AVDD33 12
MDIN2 DVDD33
1400mA
1 SWR@2 0_0402_5% LAN_MIDI3+ 9 32

Co
RL11
LAN_MIDI3- 10 MDIP3 DVDD33 tƌŝƚĞƉƌŽƚĞĐƚ tƌŝƚĞŶĂďůĞ
MDIN3
1

RL13 1 LDO@2 0_0402_5% ENSWREG ;>ŽĐŬͿ ;hŶůŽĐŬͿ

RL12 RL14
LDO mode 330_0402_1% XTLI 44 33
10K_0402_5%
@
XTLO_R 1 2 XTLO 45 CKXTAL1 Clock DVDD10 3
+LAN_VDD ĂƌĚhŶŝŶƐĞƌƚ KƉĞŶ KƉĞŶ KƉĞŶ
CKXTAL2 AVDD10 8 300mA
ĂƌĚŝŶƐĞƌƚ KƉĞŶ ůŽƐĞ ůŽƐĞ
2

AVDD10

nfi
GPO Regulator and Reference
+REGOUT 36 20
+3VS 35 REG_OUT EVDD10
+3V_LAN VDDREG
ENSWREG 34 800mA
46 ENSWREG_H 13
+LAN_VDD AVDD10 Card_3V3 +CARD_3V3
1

RL15 2 RL16 1 LAN_RST 47

de
YL1 1K_0402_5% 2.49K_0402_1% RSET 27 +VDD33_18
25MHZ_10PF_XRCGB25M000F2P34R0 DV33/18
@ T261

0.1U_0201_10V6K
CL20
41
2

XTLO_R LED0

0.1U_0201_10V6K
CL22
XTLI 1 3 ISOLATEB RL17 1 @ 2 GPO 38 1 1 1
1 3 <36> LAN_GPO 37 LED1/GPO LEDs
0_0402_5%
LED3
2

NC NC for disable PHY 40

@ T262 LED_CR
1

reserve 0 ohm 49

nti
RL18 @ T263 @
CL18 2 4 CL19 E_Pad 2 2 CL21 2
15K_0402_5%
15P_0402_50V8J 15P_0402_50V8J 4.7U_0402_6.3V6M
2

3 3

WůĂĐĞŶĞĂƌWŝŶϮϳ

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RTL8411B-CGT_QFN48_6X6

ĂƌĚZĞĂĚĞƌŽŶŶĞĐƚŽƌ
SD Write protect inverter circuit +CARD_3V3
TL1 JRJ45
JSD1
LAN_TERMAL1 24 MCT1 12
LAN_MIDI0+ 2 TCT1 MCT1 23 RJ45_MIDI0+ RJ45_MIDI3- 8 GND 6
LAN_MIDI0- 3 TD1+ MX1+ 22 RJ45_MIDI0- PR4- 11 SD_CMD_R 3 VDD
TD1- MX1- RJ45_MIDI3+ GND SD_CLK_R CMD

0.1U_0201_10V6K
CL24
7 7
4 21 MCT2 PR4+ 5 CLK
LAN_MIDI1+ TCT2 MCT2 RJ45_MIDI1+ RJ45_MIDI1- 1 1 VSS1
5 20 6 +3VS +3V_LAN 8
LAN_MIDI1- 6 TD2+ MX2+ 19 RJ45_MIDI1- PR2- CL23 VSS2
TD2- MX2- RJ45_MIDI2- 5 4.7U_0402_6.3V6M SD_D0_R 9
PR3- 2 2 SD_D1_R DAT0

100K_0402_5%
RL20

100K_0402_5%
RL21
7 18 MCT3 IC side 10
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+ RJ45_MIDI2+ 4 SD_D2_R 1 DAT1
TD3+ MX3+ PR3+ DAT2

1
LAN_MIDI2- 9 16 RJ45_MIDI2- SD_D3_R 2
TD3- MX3- RJ45_MIDI1+ 3 SD_WP CD/DAT3
10 15 MCT4 PR2+ CL25 @ 12
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+ RJ45_MIDI0- 2
40mil 10P_0402_50V8J
40mil GND 13
TD4+ MX4+ PR1- ůŽƐĞƚŽĂƌĚZĞĂĚĞƌKEE GND

1
LAN_MIDI3- 12 13 RJ45_MIDI3- 10 2 1 RJ45_GND D SD_WP# 11
LANGND
<38> SD_WP#
2

TD4- MX4- RJ45_MIDI0+ 1 GND SD_WP# 2 2 SD_CD# 4 W/P

PR1+ CD
2 RL28
2 RL27
2 RL26
RL25

1 9 G QL1
GND
Connector side S TAITW_PSDATQ09GLBS1NN4H1

3
2

CL26 GST5009-E L2N7002LT1G_SOT23-3 CONN@ CR_GND

2

.1U_0402_16V7K SP050006B10 SINGA_2RJ1660-000111F @ SP011611110

2 CONN@ JPL1
Place close to TCT pin LTCX008KA00 JUMP_43X118
4 RL19 4
DL1 SD_CLK_R 1 EMI@ 2 0_0402_5%1 2
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
1
1
1
1

LANGND ESD@ CL27 EMI@

>E ŽŶŶĞĐƚŽƌ PESD5V0U2BT_SOT23-3 SD_WP# 1 @ 2 SD_WP 10P_0402_50V8J
>ϭĐŚĂŶŐĞƚŽ^ϬϬϬϬϬdϬϬĨŽƌ^ƌĞƋƵĞƐƚ RL22 0_0402_5%
Close to JREAD1 for EMI
RJ45_GND
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8411B-CG/Card Reader
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Monday, July 16, 2018 Sheet 30 of 57
A B C D E
 A B C D E

+1.05VALW_PRIM +3VS_WLAN

tŝƌĞůĞƐƐ>E
+3VS_WLAN
4/19 for CNV across mode 4/19 DEL RM1
RM6 +3VALW
2 1 10K_0402_5% WLAN_PME# UM1 W=60mils
1 1 5 1
CM32 CM31 IN OUT
NGFF WL+BT (KEY E) 0.1U_0201_10V6K 0.1U_0201_10V6K
CM19
1 GND
2
2 2 WLAN_ON 4 3
UART_2_CRXD_R_DTXD RM45 1 UART@ 2 0_0402_5% <36> WLAN_ON EN OC 1 1 1
1U_0201_6.3V6M CM1 CM2 CM3

Vinafix.com
UART_2_CTXD_R_DRXD RM46 1 UART@ 2 0_0402_5% UART_2_CRXD_DTXD <12> 2 SY6288C20AAC_SOT23-5 @
UART_2_CTXD_DRXD <12>
BYOC@ 4.7U_0402_6.3V6M 0.1U_0201_10V6K
2 2 2
Co-layout with CNVi PH +3VS at SOC side,
0.1U_0201_10V6K
1 for win7 USB3 debug 1
KEY E +3VS_WLAN
reserve 1000p for cnvi
JNGFF1 1 2 1000P_0402_50V7K
ηϱϳϭϵϬϲĐŚĂŶŐĞƚŽh^ƉŽƌƚϭϬĨŽƌEsŝ 1 2 CM18 @
USB20_P10 3 GND_1 3.3VAUX_2 4
<13> USB20_P10 USB20_N10 5 USB_D+ 3.3VAUX_4 6 1 RM41 2 CNVI@ /Ed>Z&>ŝŶĚĂƐƵŐŐĞƐƚƌĞƐĞƌǀĞĨŽƌEsŝ
&Žƌd <13> USB20_N10 7 USB_D- LED1# 8
@ T52
75K_0402_1%
RM26 1 2 0_0201_5% CNV_PRX_R_DTX_N1 9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R 2 1 +1.8VALW_PRIM
<10> CNV_PRX_DTX_N1 SDIO_CLK PCM_SYNC CNV_RF_RESET# <10>
RM25 1 2 0_0201_5% CNV_PRX_R_DTX_P1 11 12 RM42 0_0402_5%
<10> CNV_PRX_DTX_P1 SDIO_CMD PCM_OUT CLKREQ_CNV#_R CNV_BRI_PTX_R_DRX 1 RM57 2
13 14 2 1
SDIO_DAT0 PCM_IN CLKREQ_CNV# <10>
RM27 1 2 0_0201_5% CNV_PRX_R_DTX_N0 15 16 RM37 0_0402_5% @ 10K_0402_5%
<10> CNV_PRX_DTX_N0 SDIO_DAT1 LED2# @ T267
RM28 1 2 0_0201_5% CNV_PRX_R_DTX_P0 17 18
<10> CNV_PRX_DTX_P0 SDIO_DAT2 GND_18 +3VS_WLAN
19 20
RM29 1 2 0_0201_5% CLK_CNV_PRX_R_DTX_N 21 SDIO_DAT3 UART_WAKE 22 UART_2_CRXD_R_DTXD RM47 1 CNVI@ 2 0_0402_5%
<10> CLK_CNV_PRX_DTX_N 2 0_0201_5% CLK_CNV_PRX_R_DTX_P SDIO_WAKE UART_TX CNV_BRI_PRX_DTX <12> WL_OFF#
RM30 1 23 1 RM58 2
<10> CLK_CNV_PRX_DTX_P SDIO_RST
W,нϯs^Ăƚ^KƐŝĚĞ͕ĨŽƌǁŝŶϳh^ϯĚĞďƵŐ 10K_0402_5%

Co
24 UART_2_CTXD_R_DRXD RM48 1 CNVI@ 2 0_0402_5%
25 UART_RX 26 CNV_RGI_PRX_R_DTX 2 1 CNV_RGI_PTX_DRX <12>
PCIE_CTX_C_DRX_P6 27 GND_33 UART_RTS 28 CNV_BRI_PTX_R_DRX RM38 2 1 0_0402_5% CNV_RGI_PRX_DTX <12> 2 RM56 1 CLKREQ_CNV#_R
<13> PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6 PET_RX_P0 UART_CTS E51TXD_P80DATA_R CNV_BRI_PTX_DRX <12>
29 30 RM39 2 1 0_0402_5% 71.5K_0402_1%
<13> PCIE_CTX_C_DRX_N6 31 PET_RX_N0 CLink_RST 32 E51RXD_P80CLK_R 2 1 0_0402_5% E51TXD_P80DATA <36>
RM2
PCIE_CRX_DTX_P6 33 GND_39 CLink_DATA 34 E51RXD_P80CLK <36>
<13> PCIE_CRX_DTX_P6 RM7 0_0402_5%
PCIE_CRX_DTX_N6 35 PER_TX_P0 CLink_CLK 36
<13> PCIE_CRX_DTX_N6 PER_TX_N0 COEX3
37 38

mp
CLK_PCIE_P2 39 GND_45 COEX2 40
<11> CLK_PCIE_P2 CLK_PCIE_N2 41 REFCLK_P0 COEX1 42 SUSCLK_R RM14 1 @ 2 0_0402_5%
<11> CLK_PCIE_N2 43 REFCLK_N0 SUSCLK(32KHz) 44 WL_RST#_R 2 1 PLT_RST_BUF# SUSCLK <11>
CLKREQ_PCIE#2 45 GND_51 PERST0# 46 BT_ON PLT_RST_BUF# <11,21,30,38> E51TXD_P80DATA_R
<11> CLKREQ_PCIE#2 RM4 0_0402_5%
WLAN_PME# 47 CLKREQ0# W_DISABLE2# 48 WL_OFF# BT_ON <36>
<36> WLAN_PME# 49 PEWAKE0# W_DISABLE1# 50 WL_OFF# <36>
GND_57 I2C_DAT WϴϬ>< ĂŶĚ dͺKE ĞŶĂďůĞ ƐĞƉĞƌĂƚĞ͘

1
RM33 1 2 0_0201_5% CNV_PTX_R_DRX_N1 51 52 RM40
2 <10> CNV_PTX_DRX_N1 2 0_0201_5% CNV_PTX_R_DRX_P1 RSVD/PCIE_RX_P1 I2C_CLK 2
RM35 1 53 54 0_0201_5% RM19
<10> CNV_PTX_DRX_P1

al
55 RSVD/PCIE_RX_N1 I2C_IRQ 56 REFCLK_CNV_R 1 2
GND_63 RSVD_64 REFCLK_CNV <11> 100K_0402_5%
RM36 1 2 0_0201_5% CNV_PTX_R_DRX_N0 57 58
<10> CNV_PTX_DRX_N0 2 0_0201_5% CNV_PTX_R_DRX_P0 RSVD/PCIE_TX_P1 RSVD_66 For CNVi Feature
RM31 1 59 60
<10> CNV_PTX_DRX_P0

2
61 RSVD/PCIE_TX_N1 RSVD_68 62
GND_69 RSVD_70 1 @EMC@
RM32 1 2 0_0201_5% CLK_CNV_PTX_R_DRX_N 63 64 CM17
<10> CLK_CNV_PTX_DRX_N 2 0_0201_5% CLK_CNV_PTX_R_DRX_P RSVD_71 3.3VAUX_72
RM34 1 65 66 0.1U_0201_10V6K
<10> CLK_CNV_PTX_DRX_P 67 RSVD_73 3.3VAUX_74

Co
GND_75 68 2 For ESD req reserve LC filter
GND1 close PCH reserve for BT_ON OD pull high (1.0)
69
GND2
BELLW_80152-3221 BT_ON 1 2
+3VS_WLAN
CONN@ 8.2K_0402_5% RM49
SP070013E00

ŵ^dͬ^^
nfi JSSD1
KEY M
+3VS +3VS_SSD_NGFF

de
1 2
GND 3P3VAUX +3VS_SSD_NGFF
3 4
PCIE_CRX_DTX_N9 5 GND 3P3VAUX 6 RM9 1 2
<13> PCIE_CRX_DTX_N9 PCIE_CRX_DTX_P9 7 PERn3 NC 8
<13> PCIE_CRX_DTX_P9 PERp3 NC SSD_LED#

10U_0402_6.3V6M

10U_0402_6.3V6M
9 10 0_0805_5% 2 1
GND DAS/DSS# @ T245

1
2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N9

CM30

CM14
CM5 1 11 12
<13> PCIE_CTX_DRX_N9 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P9 13 PETn3 3P3VAUX 14 RM10 1 2 + CM29

nti
CM6
<13> PCIE_CTX_DRX_P9 15 PETp3 3P3VAUX 16 150U_B2_6.3VM_R35M

2
PCIE_CRX_DTX_N10 17 GND 3P3VAUX 18 0_0805_5% 1 CM13 SGA00009M00
<13> PCIE_CRX_DTX_N10 PCIE_CRX_DTX_P10 19 PERn2 3P3VAUX 20 2
3 <13> PCIE_CRX_DTX_P10 21 PERp2 NC 22 0.1U_0201_10V6K 3
CM7 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N10 23 GND NC 24
<13> PCIE_CTX_DRX_N10 CM8 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P10 25 PETn2 NC 26

al
<13> PCIE_CTX_DRX_P10 27 PETp2 NC 28 ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ
PCIE_CRX_DTX_N11 29 GND NC 30
<13> PCIE_CRX_DTX_N11 PCIE_CRX_DTX_P11 31 PERn1 NC 32
<13> PCIE_CRX_DTX_P11 33 PERp1 NC 34
CM9 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N11 35 GND NC 36
<13> PCIE_CTX_DRX_N11 CM10 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P11 37 PETn1 NC 38 RM21 1 @ 2 0_0402_5%
<13> PCIE_CTX_DRX_P11 39 PETp1 DEVSLP 40 SSD_DEVSLP2 <13>
RM16 1 2 0_0201_5% PCIE_CRX_R_DTX_P12 41 GND NC 42 2 1
<13> PCIE_CRX_DTX_P12 RM17 1 2 0_0201_5% PCIE_CRX_R_DTX_N12 43 PERn0/SATA-B+ NC 44 RM20 0_0402_5%
<13> PCIE_CRX_DTX_N12 45 PERp0/SATA-B- NC 46 CM15 1 2 1000P_0402_50V7K
CM11 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N12 47 GND NC 48 ESD@
<13> PCIE_CTX_DRX_N12 CM12 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P12 49 PETn0/SATA-A- NC 50 NGFF_SSD_RST#_R 2 1 PLT_RST_BUF#
<13> PCIE_CTX_DRX_P12 51 PETp0/SATA-A+ PERST# 52 NGFF_CLKREQ#_R RM18 2 1 0_0402_5%
GND CLKREQ# CLKREQ_PCIE#3 <11>
53 54 RM5 0_0402_5%
<11> CLK_PCIE_N3 REFCLKN PEWake#
Port P and N follow SATA 55 56
<11> CLK_PCIE_P3 REFCLKP NC
57 58
GND NC

+3VS_SSD_NGFF 59 60 SUSCLK_SSD
NC SUSCLK(32kHz) @ T246
RM22 61 62
10K_0402_5% 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
1 @ 2 65 GND 3P3VAUX 66
GND 3P3VAUX +3VS_SSD_NGFF
67
GND 68
2 1 SSD_DET# GND1 69
<13> SATAXPCIE2 GND2
RM23 0_0402_5%
BELLW_80159-3221
4 4
CONN@
1

D
QM1 2
SP070018L00
BSS138W-7-F_SOT323-3 G
@ S
3

SSD_DET# (SATA_GP0)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title
SATA Device 0
PCIE Device 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M.2 Key E (WLAN)/Key M(SSD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Monday, July 23, 2018 Sheet 31 of 57
A B C D E
 A B C D E

,ƵĚŝŽŽĚĞĐ ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ

+PVDD_HDA

^DϬϭϬϬϬ:ϬϬ ϯϬϬϬŵ ϮϮϬŽŚŵΛϭϬϬŵŚnj Z Ϭ͘Ϭϰ +5VS (output = 300 mA) +VDDA
ϰϬŵŝů ϰϬŵŝů JPA1 ϰϬŵŝů /Ŷƚ͘^ƉĞĂŬĞƌŽŶŶ͘
+VDDA
LA1 2 1 1
1 2
2 ϰϬŵŝů SPK_R+
JSPK1
HCB2012KF-221T30_0805 1 1 1 SPKR+ LA2 EMI@ 1 2 PBY160808T-121Y-N_2P 1
1

1
SPK_R-

0.1U_0201_10V6K
CA2

0.1U_0201_10V6K
CA3

.1U_0402_16V7K
CA4
JUMP_43X79 4.75V SPKR- LA3 EMI@ 1 2 PBY160808T-121Y-N_2P 2

10U_0402_6.3V6M

10U_0402_6.3V6M
1 2 SPK_L+ 3 2

CA1
SPKL+

CA34
@ LA4 EMI@ PBY160808T-121Y-N_2P
SPKL- LA5 EMI@ 1 2 PBY160808T-121Y-N_2P SPK_L- 4 3

2
2 2 @ +AVDD1_HDA 2 5 4
G1

Vinafix.com @ESD@ D/ƌĞƋƵĞƐƚĨŽƌƐŽůǀĞD/ŶŽŝƐĞ͕^DϬϭϬϬϬKtϬϬ͘ 6

GND GND
'EΘ'E ŵŽĂƚ G2

3
GND ACES_50278-00401-001
GND CONN@
WůĂĐĞŶĞĂƌ WŝŶϰϭ WůĂĐĞŶĞĂƌ WŝŶϰϲ @ESD@ @ESD@
1
DA1 DA2 SP02000RR00 1

ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ CA35 1 2 10U_0402_6.3V6M ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
GND ϮϬŵŝů

1
CA5 1 2 10U_0402_6.3V6M RA1 1 2 0_0603_5%
+VDDA
1

1
0.1U_0201_10V6K
CA8
WŝŶϵŶĞĞĚƚŽŵĂƚĐŚŝŶŐǁŝƚŚ^K, CA6 1 2 0.1U_0201_10V6K CA9 CA36 GND GND
ŝŶƚĞƌĨĂĐĞ͘

10U_0402_6.3V6M

10U_0402_6.3V6M
2 1 +3VS_DVDDIO
+3VS WůĂĐĞŶĞĂƌWŝŶϵ

2
RA2 0_0402_5% 2 @
+3VS_DVDD 'EΘ'E ŵŽĂƚ ƌĞƐĞƌǀĞĨŽƌ ϰD/
33_0402_5% RA37
PCH_DMIC_DATA1 2 @ 1
ϮϬŵŝů GNDA <10> PCH_DMIC_DATA1 PCH_DMIC_CLK1 +3VS
2 1 WůĂĐĞŶĞĂƌ WŝŶϮϲ 2 @ 1
+3VS <10> PCH_DMIC_CLK1 JMIC1
RA5 0_0402_5% 33_0402_5% RA38
1 0_0402_5% RA39 1
1

1
+1.8VS_VDDA DMIC_DATA34 DMIC_R_DATA1

0.1U_0201_10V6K
CA11
CA37 CA10 2 1 +1.8VS 2 @ 1 2
RA6 0_0402_5% DMIC_CLK 2 @ 1 DMIC_R_CLK1 3 2
1 3

1
0.1U_0201_10V6K
CA12
CA13 0_0402_5% RA40 4

10U_0402_6.3V6M

10U_0402_6.3V6M
2

2
2 4

Co
5
6 G1

10U_0402_6.3V6M
2
2 @ G2
1 2 DMIC_CLK WůĂĐĞŶĞĂƌWŝŶϭ GND GNDA ACES_50278-00401-001
CA32 @EMI@ CONN@
10P_0402_50V8J

41

46

26

40
SP02000RR00

9
UA1 WůĂĐĞŶĞĂƌ WŝŶϰϬ GND
Reserved for EMI

DVDD

DVDD-IO

PVDD1

PVDD2

AVDD1

AVDD2
ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ
GND

2
UA1

ϰϬŵŝů RING2
LINE1-L
LINE1-R
22
21

24
23

17
LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)

LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)
mp
MIC2-L(PORT-F-L) /RING2
SPK-OUT-L-
SPK-OUT-L+

SPK-OUT-R+
SPK-OUT-R-
43
42

45
44
SPKL-
SPKL+

SPKR+
SPKR-
2

al
SLEEVE 18
ALC256-CG MQFN 48P CODEC MIC2-R(PORT-F-R) /SLEEVE 32 HP_LEFT
Combo MIC
256@ +MICBIAS +MICBIAS 31
LINE1-VREFO-L
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
33 HP_RIGHT ŝŐŝƚĂů D/
SA000080Q00 30
LINE1-VREFO-R 10 HDA_SYNC_R
DMIC_DATA SYNC HDA_BIT_CLK_R HDA_SYNC_R <10>
2 6
DMIC_CLK GPIO0/DMIC-DATA BCLK HDA_BIT_CLK_R <10>
3
GPIO1/DMIC-CLK PCH_DMIC_DATA

Co
1 @EMI@ 2 1 2 CA15 @EMI@ GND 2 @ 1
<10> PCH_DMIC_DATA
RA10 0_0402_5% 22P_0402_50V8J 33_0402_5% RA36
EC_MUTE# 47 5 HDA_SDOUT_R PCH_DMIC_CLK 2 @ 1
<36> EC_MUTE# HDA_RST#_R 2 255@ 1 11 PDB SDATA-OUT 8 HDA_SDIN0_AUDIO 1 RA33 2
HDA_SDOUT_R <10> <10> PCH_DMIC_CLK
33_0402_5% RA11
TO eDP Conn
 WŝŶϭϭ͕ϭϮ <10> HDA_RST#_R
0_0402_5% RA41 RESETB SDATA-IN 33_0402_5%
HDA_SDIN0 <10>
>Ϯϱϱ͗Z^d͕WW 48 DMIC_DATA34 DMIC_DATA 2 EMI@ 1 RA35 DMIC_DATA_R
>Ϯϱϲ͗&ůŽĂƚ ŝ ŶŐ;/ ϮͿ MONO_IN 12 SPDIF-OUT/GPIO2 0_0402_5% DMIC_DATA_R <28>
ϭϬŵŝů ůŽƐĞĐŽĚĞĐ
PCBEEP 16 PC_BEEP DMIC_CLK 2 1 DMIC_CLK_R
HP_PLUG# RA13 2 1 200K_0402_1% SENSE_A 13 MONO-OUT RA34 DMIC_CLK_R <28>
<35> HP_PLUG# +MIC2_VREFO

nfi
RA14 2 1 100K_0402_1% 14 SENSE A BLM15PX221SN1D
+3VS SENSE B 29 10U_0402_6.3V6M 1 2 CA18 GND EMI@
MIC2-VREFO
1

37
CA19 35 CBP 7 10U_0402_6.3V6M 1 2 CA20
CBN LDO3-CAP GNDA
+1.8VS_VDDA 2 256@ 1 2.2U_0201_6.3V6M 39
2

0_0402_5% RA43 LDO2-CAP 27 10U_0402_6.3V6M 1 2 CA21

LDO1-CAP GNDA
2 255@ 1 CPVDD 36
+3VS_DVDD CPVDD

de
WŝŶϮϬ 0_0402_5% RA42 1 RA15 2
28 CODEC_VREF 100K_0402_5% ϭϬŵŝů
>Ϯϱϱ ͗ ϯ͘ϯs 2 1 20 VREF
1
+3VALW CPVREF ,ĞĂĚƉŚŽŶĞ KƵƚ

1
>Ϯϱϲ ͗ ϯ͘ϯs Žƌ ϱs

0.1U_0201_10V6K
CA23

2.2U_0201_6.3V6M
CA24
RA16 0_0402_5% 15
10U_0402_6.3V6M 1 2 CA22 19 JDREF 34 CPVEE
WŽǁĞƌĨŽƌĐŽŵďŽũĂĐŬĚĞƉŽƉ GNDA MIC-CAP CPVEE
ĐŝƌĐƵŝƚĂƚƐLJƐƚĞŵƐŚƵƚĚŽǁŶŵŽĚĞ

2
@ 2

1
4 +MIC2_VREFO

nti
49 DVSS 25 CA26
WŝŶϰ Thermal PAD AVSS1 38 2.2U_0201_6.3V6M
>Ϯϴϯ ͗ s^^

2
AVSS2
3 >ϮϱϱͬϮϱϲͬϮϯϯ͗d;&Žƌ:ĂƉĞŶĐƵƐƚŽŵĞƌ ŽŶůLJͿ WůĂĐĞŶĞĂƌƉŝŶϮϴ 3
ALC255-CG_MQFN48_6X6

1
WŝŶϯϲ SA000082700 GND
GND 255@ RA19 RA20

al
>Ϯϱϱ ͗ ϯ͘ϯs GNDA 2.2K_0402_5% 2.2K_0402_5%
>Ϯϱϲ ͗ ϭ͘ϴs GNDA

2
RA21 CA27 SLEEVE
SLEEVE <35>
K^ŵŽĚĞ 22K_0402_5% .1U_0402_16V7K WŝŶϭϱ RING2 RING2 <35>
2 1 BEEP#_R 1 2 MONO_IN
<36> BEEP# >Ϯϴϯ͗ZĞĨ͘ZĞƐŝƐƚŽƌĨŽƌ:ĂĐŬĞƚĞĐƚ
255@
WŝŶϭϲ >ϮϱϱͬϮϱϲͬϮϯϯ͗:ĂĐŬĞƚĞĐƚĨŽƌ^W/&ͲKhdĂŶĚ^W<ͲKhdƉŽƌƚ
RA22 CA33 >Ϯϱϱ͗ DKEKͲKhd
2

>Ϯϱϲ ͗ W
4.7K_0402_5%

K^ŵŽĚĞ 22K_0402_5% 1 .1U_0402_16V7K

PC_BEEP
100P_0402_50V8J
CA28 @EMI@

2 1 1 2
<10> PCH_SPKR
RA23

256@
2 HP_LEFT RA24 1 2 0_0603_5% HPOUT_L_1
HPOUT_L_1 <35>
1

HP_RIGHT RA27 1 2 0_0603_5% HPOUT_R_1 HPOUT_R_1 <35>

LINE1-L 1 2
GND CA29 4.7U_0402_6.3V6M
LINE1-R 1 2
CA30 4.7U_0402_6.3V6M
+MICBIAS DA5
2 2 RA29 1
'EΘ'EŵŽĂƚ 4.7K_0402_5%
1

RA47 2 1 0_0402_5% 3 2 RA32 1

4.7K_0402_5%
BAT54A-7-F_SOT23-3
4 SCSBAT54100 4
RA44 2 1 0_0402_5%
^zDK>͗^^dϱϰϬϬ
sĞŶĚŽƌ ƐƵŐŐĞƐƚ͗
ƚůĞĂƐƚŽŶĞ'ƌŽƵŶĚƐŚŽƌƚĐůŽƐĞƚŽĐŽĚĞĐ͘
RA45 2 1 0_0402_5%

RA46 2 1 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title
HD Audio Codec ALC255/ALC256 Colay
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GND GNDA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 32 of 57
A B C D E
 A B C D E

'Ͳ^ĞŶƐŽƌƌĞƐĞƌǀĞĚĨŽƌƐĞƌŝĂů
+3VS

1
RZ1
10K_0402_5%
Vinafix.com +3VS

GSEN@ UZ1 GSEN@

1 1 CZ1 1 2 10U_0402_6.3V6M 1

2
8 Vdd_IO
4 CS 14 CZ2 1 2 GSEN@
<9,19,20> SOC_SMBCLK_1 SCLSPC Vdd
6 0.1U_0201_10V6K
<9,19,20> SOC_SMBDATA_1 SDA/SDI/SDO
+3VS RZ2 1 @ 2 10K_0402_5% 7
RO25 1 GSEN@ 2 10K_0402_5% SDO/SA0 11 G_INT#
INT1 G_INT2 G_INT# <12>
16 9
15 ADC1 INT2
13 ADC2 10 INT1/2 all High Active
ADC3 RES
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3

Co
GSEN@

LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)

2
mp 2

al FFC JHDD1
14
Type

Co
+5VS_HDD 13 GND
GND
+5VS_HDD 12
11 12
0_0402_5% 10 11
G_INT2 G_INT2 RO4 1 @ 2 G_INT2_R 9 10
8 9

nfi
7 8
7
2

SATA_CRX_DTX_P0 CO4 1 2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_P0 6

<13> SATA_CRX_DTX_P0 SATA_CRX_DTX_N0 RDSATA_CRX_C_DTX_N0 6
RO26 CO3 1 2 0.01U_0402_16V7K 5
<13> SATA_CRX_DTX_N0 5
0_0402_5% 4
SATA_CTX_DRX_N0 CO2 1 2 0.01U_0402_16V7K RDSATA_CTX_C_DRX_N0 3 4
<13> SATA_CTX_DRX_N0 SATA_CTX_DRX_P0 RDSATA_CTX_C_DRX_P0 3
CO1 1 2 0.01U_0402_16V7K 2

de
<13> SATA_CTX_DRX_P0
1

1 2
1
close to CONN.
ACES_51625-01201-001
CONN@
SP010028W00

nti
+5VS +5VS_HDD

3 3
1 2
100mils
RO3 0_0805_5%

al
10U_0402_6.3V6M

10U_0402_6.3V6M
1

1
CO16

CO12
CO13
0.1U_0201_10V6K
@

2
2

ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ HDD Re-Driver
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 33 of 57
A B C D E
 5 4 3 2 1

dLJƉĞh^ϯ͘Ϭ'ĞŶϭ DS1~4 change to SC300001Y00 For ESD request

DS1 ESD@
USB20_P2_L 1  USB20_P2_L
 9

<13> USB3_CTX_DRX_N3
1 2 USB3_CTX_C_DRX_N3 RS1 1 @ 2 0_0402_5% USB3_CTX_L_DRX_N3 USB20_N2_L 2   8
USB20_N2_L
CS1 0.22U_0402_25V6K
USB3_CRX_L_DTX_N3 4  7
USB3_CRX_L_DTX_N3

<13> USB3_CTX_DRX_P3 1 2 USB3_CTX_C_DRX_P3 RS2 1 @ 2 0_0402_5% USB3_CTX_L_DRX_P3
USB3_CRX_L_DTX_P3 5 USB3_CRX_L_DTX_P3

Vinafix.com  6
CS2 0.22U_0402_25V6K 

3 
D D
8

AZ1045-04F_DFN2510P10E-10-9

DS2 ESD@
1 2 USB3_CRX_C_DTX_N3 RS3 1 @ 2 0_0402_5% USB3_CRX_L_DTX_N3 USB3_CTX_L_DRX_N2 1
  9
USB3_CTX_L_DRX_N2
<13> USB3_CRX_DTX_N3
CS106 0.33U_0402_10V6K
USB3_CTX_L_DRX_P2 2  8
USB3_CTX_L_DRX_P2

1 2 USB3_CRX_C_DTX_P3 RS4 1 @ 2 0_0402_5% USB3_CRX_L_DTX_P3
<13> USB3_CRX_DTX_P3 TBTA_SBU2 4  TBTA_SBU2
CS107 0.33U_0402_10V6K  7

1
RS199

RS198
220K +-5% 0201

220K +-5% 0201

TBTA_SBU1 5   6
TBTA_SBU1

3 

2
8

AZ1045-04F_DFN2510P10E-10-9

Co
<13> USB3_CTX_DRX_N2
1 2 USB3_CTX_C_DRX_N2 RS5 1 @ 2 0_0402_5% USB3_CTX_L_DRX_N2 DS3 ESD@
CC2_VCONN 1  CC2_VCONN
CS3 0.22U_0402_25V6K  9

<13> USB3_CTX_DRX_P2
1 2 USB3_CTX_C_DRX_P2 RS6 1 @ 2 0_0402_5% USB3_CTX_L_DRX_P2 2   8
CS4 0.22U_0402_25V6K
4   7
CC1_VCONN 5   6
CC1_VCONN

mp
3 

C AZ1045-04F_DFN2510P10E-10-9 C
1 2 USB3_CRX_C_DTX_N2 RS7 1 @ 2 0_0402_5% USB3_CRX_L_DTX_N2
<13> USB3_CRX_DTX_N2
CS104 0.33U_0402_10V6K
DS4 ESD@
1 2 USB3_CRX_C_DTX_P2 RS8 1 @ 2 0_0402_5% USB3_CRX_L_DTX_P2 USB3_CRX_L_DTX_P2 1
  9
USB3_CRX_L_DTX_P2
<13> USB3_CRX_DTX_P2

al
CS105 0.33U_0402_10V6K
USB3_CRX_L_DTX_N2 2  8
USB3_CRX_L_DTX_N2
1 

1
RS197

RS196
220K +-5% 0201

220K +-5% 0201

USB3_CTX_L_DRX_N3 4  7
USB3_CTX_L_DRX_N3

USB3_CTX_L_DRX_P3 5  6
USB3_CTX_L_DRX_P3

2

3 

Co
#575549 USB3P1_TYPE_C_ECN WW50 8
add RC on TYPEC USB3 trace
AZ1045-04F_DFN2510P10E-10-9

nfi
+3VALW +3VALW_CC +5VALW_CC_VOUT
+5VALW +5VALW_CC @EMI@
ϭϮϬŵŝůƐ ϯ ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ 2 1 RS204 2 1 0_0603_5%
JPS2
1 2
1 2
0.1U_0201_10V6K

0.01U_0402_16V7K

RS10 0_0402_5%
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
JUMP_43X79 1 2 1 CR_GND
10U_0402_6.3V6M

10U_0402_6.3V6M

1
CS113

CS7

CS9

CS10

CS8

CS114
@ RS205 2 @EMI@ 1 0_0603_5%

de
1

1
CS112

CS5

+ CS6
150U_B2_6.3VM_R35M
2

2
SGA00009M00 1 2 TYPEC_GND
2

B B

nti
+3VALW_CC
ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ @ JPS1
1 2 +USB3_VCCC +USB3_VCCC
RS200 1 2 100K_0402_5% CC_AUDIO# 1 2
RS201 1 2 100K_0402_5% CC_POL# JUMP_43X118
ϭϮϬŵŝůƐ ϯ
RS202 1 2 100K_0402_5% CC_UFP# +USB3_VCCC
RS203 1 2 100K_0402_5% CC_LD_DET# +5VALW_CC +5VALW_CC_VOUT
US1 @ QS1
ϯϬs ϭϬŵKŚŵ
AON6405L 1P DFN CC1_VCONN/CC2_VCONN 20mils JUSB2
ϭϮϬŵŝůƐ ϯ ϭϮϬŵŝůƐ ϯ

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+3VALW_CC 1 A1 B12
2 14 2 GND GND
3 IN1 OUT 15 5 3 USB3_CTX_L_DRX_P3 A2 B11 USB3_CRX_L_DTX_P3
+3VALW_CC 4 IN1 OUT USB3_CTX_L_DRX_N3 A3 SSTXP1 SSRXP1 B10 USB3_CRX_L_DTX_N3
IN2 SSTXN1 SSRXN1

1
0.1U_0402_25V_K_X5R 2 1 CS11
5 RS15 RS12 A4 B9 CS12 1 2 0.1U_0402_25V_K_X5R
4

RS13 1 2 100K_0402_5% CC_FAULT# AUX 1 CC_FAULT# +3VALW_CC 100K_0402_5% @ 1M_0402_5% VBUS VBUS
RS18 1 2 100K_0402_5% CC_DEBUG# FAULTb 20 CC_LD_DET# @ DS5 CC1_VCONN A5 B8 TBTA_SBU2
LD_DETb CC1 SBU2

3
2 1 CC_EN 6 CS13
<36> EC_TYPEC_EN 2

2
EN
1

RS37 0_0402_5% 10U_0805_25V6K USB20_P2_L A6 B7 USB20_N2_L

RS20 1 2 100K_0402_5% CC_CHG USB20_N2_L A7 DP1 DN2 B6 USB20_P2_L

AZ4024-02S.R7G C/A SOT23

RS42

2
RS40 1 @ 2 100K_0402_5% CC_CHG_HI CC_CHG 7 11 CC1_VCONN @ 10K_0402_5% DN1 DP2
CC_CHG_HI 8 CHG CC1 13 CC2_VCONN TBTA_SBU1 A8 B5 CC2_VCONN
CHG_HI CC2 SBU1 CC2
3

RS41 1 @ 2 100K_0402_5% CC_EN D

2

1
5 QS2B 0.1U_0402_25V_K_X5R 2 1 CS14 A9 B4 CS15 1 2 0.1U_0402_25V_K_X5R
16 CC_DEBUG# G 2N7002KDW_SOT363-6 ESD@ VBUS VBUS
CC_REF 10 DEBUGb 17 CC_AUDIO# @ ^ϱĐŚĂŶŐĞƚŽ^ϬϬϬϬϮYϬϬĨŽƌ^ƌĞƋƵĞƐƚ USB3_CRX_L_DTX_N2 A10 B3 USB3_CTX_L_DRX_N2
REF AUDIOb SSRXN2 SSTXN2
6

18 CC_POL# D S USB3_CRX_L_DTX_P2 A11 B2 USB3_CTX_L_DRX_P2

4

POLb 19 CC_UFP# 2 QS2A SSRXP2 SSTXP2

2 1 CC_CHG_HI RS39 1 2 100K_0402_1% 9 UFPb G 2N7002KDW_SOT363-6 A12 B1
<36> TYPEC_3A_1P5A# GND1 GND GND
12 21 @
RS38 0_0402_5% GND2 powerpad S 1 6
1

LS5 EMI@ 2 GND GND 7

USB20_P2 2 1 USB20_P2_L 3 GND GND 8
<13> USB20_P2 2 1 GND GND
A 4 9 A
TPS25810RVCR_QFN20_4X3 5 GND GND 10
USB20_N2 3 4 USB20_N2_L GND GND
<13> USB20_N2 3 4 LOTES_AUSB0372-P001A CONN@
DLM0NSN900HY2D_4P DC23300QQ00
SM070005U00 TYPEC_GND CR_GND CR_GND
Symbol:LTCX007XY00
ĨŽƌ^ƚĞƐƚ ĨŽƌ^ƚĞƐƚ
Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CC+USB TYPE C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
Note : 2017 BIOS SPEC define DC mode 30% stop charge MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 34 of 57
5 4 3 2 1
 A B C D E

h^ϯ͘Ϭ;WŽƌƚϭͿ
DS21 change to SC300001Y00 For ESD request +USB3_VCCA

DS21 ESD@ W=100mils

USB3_CTX_L_DRX_P1 1 USB3_CTX_L_DRX_P1
@RF@   9
<13> USB3_CTX_DRX_N1 CS21 1 2 USB3_CTX_C_DRX_N1
.1U_0402_16V7K
RS21
Vinafix.com
1

@RF@
2 0_0402_5% USB3_CTX_L_DRX_N1
USB3_CTX_L_DRX_N1 2   8 USB3_CTX_L_DRX_N1 1
+
1
CS22 1 2 USB3_CTX_C_DRX_P1 RS22 1 2 0_0402_5% USB3_CTX_L_DRX_P1 USB3_CRX_L_DTX_P1 4   7 USB3_CRX_L_DTX_P1 CS25 CS26
1 <13> USB3_CTX_DRX_P1 1
.1U_0402_16V7K 150U_B2_6.3VM_R35M 470P_0402_50V7K
USB3_CRX_L_DTX_N1 5  6 USB3_CRX_L_DTX_N1 SGA00009M00 2 2 @

3  h^ϯ͘ϬŽŶŶ͘
@RF@
USB3_CRX_DTX_N1 RS24 1 2 0_0402_5% USB3_CRX_L_DTX_N1 8 JUSB1
<13> USB3_CRX_DTX_N1 USB3_CTX_L_DRX_P1 9
@RF@ AZ1045-04F_DFN2510P10E-10-9 1 SSTX+
USB3_CRX_DTX_P1 RS25 1 2 0_0402_5% USB3_CRX_L_DTX_P1 USB3_CTX_L_DRX_N1 8 VBUS
<13> USB3_CRX_DTX_P1 U2DP1_L 3 SSTX-
7 D+
U2DN1_L 2 GND 10
USB3_CRX_L_DTX_P1 6 D- GND 11
DS22 ESD@ 4 SSRX+ GND 12
6 3 U2DN1_L USB3_CRX_L_DTX_N1 5 GND GND 13
LS23 EMI@ I/O4 I/O2 SSRX- GND
U2DP1 2 1 U2DP1_L +USB3_VCCA ACON_TARBA-9U1393

Co
2 1 CONN@
5 2 LTCX008KB00
U2DN1 3 4 U2DN1_L VDD GND
3 4
Symbol:DC23300N800
DLM0NSN900HY2D_4P TYPEC_GND USB_GND
SM070005U00 4 1 U2DP1_L
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
ĨŽƌ^ƚĞƐƚ

mp
@EMI@
RS206 2 1 0_0603_5%

+5VALW

For Test Debug Only USB_GND

+5VALW
2 +5VALW RS14 1 CHG@ 2 10K_0402_5% CHG_CTL2 vendor recommend 2

al
RS147
1 @ 2 CHG_CTL3 1 2
RS150 10K_0402_5% RS152 1 @ 2 10K_0402_5% CHG_ILMSEL reserve VIN & VOUT 1206 for
QFN current measure

22U_0603_6.3V6M

0.1U_0201_10V6K
0_1206_5% 1 1
CHG_EN CHG_CTL1

CS95

CS93
2 1

Co
@ Rerserve PU, vendor suggest to EC control @ +USB3_VCCA
RS151 10K_0402_5% CHG@
if future need support SDP2 2 2
US22 CHG@
+5VALW_CHG 1 12 +USB3VCCA_CHG RS148 1 2 0_1206_5%
VIN VOUT
USB20_N1 2
<13> USB20_N1 USB20_P1 3 DM_OUT
<13> USB20_P1 DP_OUT

nfi
10 U2DP1
USB Host Charger Truth Table <13> USB_OC0#
USB_OC0# RS11 2 @ 1 0_0402_5%
CHG_ILMSEL
13

4
FAULT#
DP_IN
DM_IN
11 U2DN1

CHG_EN CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Note 1 <36> CHG_ILMSEL ILIM_SEL
Setting
CS94 CHG_EN 5 15
Reserve ILIM_L R as vendor recommend
<36> CHG_EN EN ILIM_L 16
0 0 1 0 1 SDP1-OFF ILIM_H Port power off 0.1U_0201_10V6K

de
@ 2 ILIM_HI

1
SDP1 CHG_CTL1 6
1 0 1 0 1 ILIM_H Data Lines Connected <36> CHG_CTL1 CHG_CTL2 CTL1

22.1K_0402_1%

39K_0402_1%
7 9
CHG_CTL3 CTL2 NC

RS98

RS99
1 0 1 1 1 DCP ILIM_H Data Lines Disconnected 8 14
<36> CHG_CTL3 CTL3 GND 17
Aut o Thermal Pad ILM R vaule
CHG@ @

2
Ios(mA)=50250/R(Kohm)

nti
1 1 1 1 1 CDP ILIM_H Data Lines Connected SLGC55544CVTR_TQFN16_3X3
SA000097E10 ILIM_Hi=2273mA
3
ILIM_L=1288mA 3

/Kͬ;h^džϮ͕ĂƌĚƌĞĂĚĞƌ͕>Ϳ
<36>
<36>
<36>
<36>

<32>
<32>
PWR_LED#
PWR_SUSP_LED#
BATT_BLUE_LED#
BATT_AMB_LED#

HP_PLUG#
HPOUT_L_1
PWR_LED#
PWR_SUSP_LED#
BATT_BLUE_LED#
BATT_AMB_LED#
GNDA HP_PLUG#
HPOUT_L_1
HPOUT_R_1
al
1
2
3
4
5
6
7
JIO1

1
2
3
4
5
6
7
<13>

<13>
USB20_P3

USB20_N3
USB20_P3

USB20_N3
3

2
SM070005U00
DLM0NSN900HY2D_4P
3

2
L3 EMI@
4
4

1
1
USB20_L_P3

USB20_L_N3

8
<32> HPOUT_R_1 8
SLEEVE 9
<32> SLEEVE 9
RING2 10
<32> RING2 10
11
12 11
USB20_L_N4 13 12 4/24 Modify
USB20_L_P4 14 13
15 14
16 15
USB20_L_N3 17 16 SM070005U00
USB20_L_P3 18 17 DLM0NSN900HY2D_4P
19 18 USB20_P4 3 4 USB20_L_P4
20 19 <13> USB20_P4 3 4
USB_EN 21 20
<36> USB_EN 21 USB20_N4 USB20_L_N4
22 2 1
23 22 <13> USB20_N4 2 1
24 23 L4 EMI@
4 25 24 4
26 25
27 26
28 27
29 28
30 29
31 30 34
32 31 GND2 33
+5VALW 32 GND1 Security Classification Compal Secret Data Compal Electronics, Inc.
ACES_51547-03201-W01 Issued Date 2018/01/10 2018/11/04 Title
CONN@
Deciphered Date
USB3 Conn/IOB
SP01001PC00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 35 of 57
A B C D E
 A B C D E

+3VLP_EC WE͗^DϬϭϬϬϬ<ϱϬϬ +3VLP_ECA

+3VLP LB1
FBMA-L11-160808-800LMT_0603 near SOC SOC_RTCRST# <11>
CB9 1 2 1000P_0402_50V7K EC_RST# 1 2 1 2 +3VLP_ECA
D

1
RB22 0_0805_5%
EC_CLR_CMOS 2 QB6
+1.8VALW_PRIM

0.1U_0201_10V6K
CB1

0.1U_0201_10V6K
CB2

0.1U_0201_10V6K
CB3
1 1 1 G L2N7002LT1G_SOT23-3

1
S

3
1

0_0402_5%
RB26

RB2
LPC@ 10K_0402_5%
+3VLP_EC
Vinafix.com 2 2
ESPI@
RB3
0_0402_5%
2

2
ECAGND
ECAGND <42>

2
1 @ 2 EC_PME#

2
1 RB5 47K_0402_5% +3VCC_LPC 1
EC_PME# PU +3V_LAN at LAN side
+3VS

111
125
22
33
96

67
9
+3VLP_EC UB1
GPU_ALERT RB23 1 2 10K_0402_5%

VCC0
VCC_LPC
VCC
VCC
VCC

VCC

AVCC
RB13 1 2 2.2K_0402_5% EC_SMB_CK1
RB14 1 2 2.2K_0402_5% EC_SMB_DA1
ESPI Bus Pin : 1~5.7.8.10.12.14 GPU_OVERT#RB24 1 2 10K_0402_5%
LPC Bus Pin : 3~5.7.8.10.12.13 SUSPWRDNACK 1 21 EC_VCCST_PG_R
<11> SUSPWRDNACK 2 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F 23 EC_VCCST_PG_R <11,40>
BEEP#
EC_SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 FAN_PWM1 BEEP# <32>
<9> EC_SERIRQ LPC_FRAME# 4 SERIRQ EC_FAN_PWM/GPIO12 27 CHG_CTL1 FAN_PWM1 <39>
<9> LPC_FRAME# LPC_AD3_R LPC_FRAME# PWM Output AC_OFF/GPIO13 CHG_CTL1 <35>
For turn off internal LPC module of KB9032 5
<9> LPC_AD3_R LPC_AD2_R 7 LPC_AD3
<9> LPC_AD2_R LPC_AD1_R 8 LPC_AD2 63 BATT_TEMP
ESPI@
1 2 ESPI_RST# <9> LPC_AD1_R LPC_AD0_R 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 VCIN1_BATT_DROP BATT_TEMP <42,43> +3VLP_EC
LPC & MISC

Co
<9> LPC_AD0_R LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 65 ADP_I VCIN1_BATT_DROP <42>
RB8 47K_0402_5%
CLK_LPC_EC 12 ADP_I/AD2/GPIO3A 66 AD_BID ADP_I <42,43>
<9> CLK_LPC_EC PLT_RST# CLK_PCI_EC AD Input AD_BID/AD3/GPIO3B WLAN_PME# LID_SW#
ESPI@ 13 75 RB15 1 2 100K_0402_1%
1 2 PLT_RST# <11,37> PLT_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 EC_PME# WLAN_PME# <31>
<39> EC_RST# EC_SCI# 20 EC_RST# AD5/GPIO43 EC_PME# <30>
RB9 47K_0402_5% Combine w/ SMI
<7> EC_SCI# WLAN_ON 38 EC_SCI#/GPIO0E
1 2 <31> WLAN_ON CLKRUN#/GPIO1D
CB5 ESD@ 100P_0402_50V8J 68 LAN_PWR_EN

mp
<37> KSI[0..7] DA0/GPIO3C 70 EC_TP_INT# LAN_PWR_EN <30>
DA Output EN_DFAN1/DA1/GPIO3D VR_PWRGD EC_TP_INT# <7,37>
KSI0 55 71
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72 KBL_EN VR_PWRGD <48>
1 2 AC_IN KSI2 57 KSI1/GPIO31 DA3/GPIO3F KBL_EN <37>
CB6 100P_0402_50V8J KSI3 58 KSI2/GPIO32 83 EC_MUTE#
59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84 USB_EN EC_MUTE# <32>
KSI4
KSI5 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 EC_TYPEC_EN USB_EN <35>
@EMI@ @EMI@
2 2 1 2 1 CLK_LPC_EC KSI6 61 KSI5/GPIO35 PSCLK2/GPIO4C 86 CHG_EN EC_TYPEC_EN <34> 2
PS2 Interface CHG_EN <35>

al
CB7 RB10 33_0402_5% KSI7 62 KSI6/GPIO36 PSDAT2/GPIO4D 87 TP_CLK SYS_PWROK_R 2 1
<37> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <37> SYS_PWROK <11,40>
22P_0402_50V8J KSO0 39 88 TP_DATA
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <37> WhĂƚWdWƐŝĚĞ
RB11 0_0402_5%
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL
43 KSO3/GPIO23 ENKBL/GPXIOA00 98 TP_PWR_EN ENBKL <7>
KSO4
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN TP_PWR_EN <37>
KSO5

Co
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN <10>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <42>
DB1
&Žƌ dŚĞƌŵĂů WŽƌƚĞĐƚ ^ŚƵƚĚŽǁŶ
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface SLP_WLAN#
RB751V-40_SOD323-2
3V_EN
KSO9 48 119 MAINPWON 1 2
KSO10 49 KSO9/GPIO29 MISO/GPIO5B 120 BT_ON SLP_WLAN# <11> 3V_EN <44>
50 KSO10/GPIO2A MOSI/GPIO5C 126 EC_CLR_CMOS BT_ON <31>
KSO11 SPI Flash ROM SPICLK/GPIO58
KSO12 51 KSO11/GPIO2B 128 FP_PWR_EN 3V_EN_R 1 2 RB17 1 2
KSO12/GPIO2C SPICS#/GPIO5A FP_PWR_EN <37>

nfi
KSO13 52 RB16 1M_0402_5%
KSO14 53 KSO13/GPIO2D 1K_0402_5%
KSO15 54 KSO14/GPIO2E 73 GPU_ALERT
81 KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 74 SYS_PWROK_R GPU_ALERT <21>
KSO16
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 BATT_4S
KSO17/GPIO49 GPIO50 90 BATT_BLUE_LED# BATT_4S <43>
BATT_CHG_LED#/GPIO52 91 CHG_CTL3 BATT_BLUE_LED# <35>

de
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 PWR_LED# CHG_CTL3 <35>
<42,43> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 GPIO PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED# <35>
78 93
<42,43> EC_SMB_DA1 SOC_SML1CLK 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_AMB_LED# <35>
<9,21> SOC_SML1CLK SOC_SML1DATA 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 VR_ON SYSON <14,40,45>
WhĂƚWhƐŝĚĞ <9,21> SOC_SML1DATA EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 CHG_ILMSEL VR_ON <40,48>
DPWROK_EC/GPIO59 CHG_ILMSEL <35>
SM Bus

nti
PM_SLP_S3# 6 100 EC_RSMRST#
<11,40> PM_SLP_S3# ESPI_RST# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 DGPU_AC_DETECT EC_RSMRST# <11>
<9> ESPI_RST# SPOK_3V_5V 15 GPIO07 GPXIOA04 102 VCIN1_ADP_PROCHOT DGPU_AC_DETECT <10,21,43>
3 <44,47> SPOK_3V_5V TP_EN 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT# VCIN1_ADP_PROCHOT <42> 3
<37> TP_EN TS_EN 17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104 MAINPWON
<12,28> TS_EN WL_OFF# 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 BKOFF# MAINPWON <39,42,44>

al
<31> WL_OFF# AC_PRESENT 19 GPIO0C BKOFF#/GPXIOA08 106 LAN_GPO BKOFF# <28>
<11> AC_PRESENT GPU_OVERT# AC_PRESENT/GPIO0D GPIO GPO GPXIOA09 3V_EN_R LAN_GPO <30>
25 107
<21,22> GPU_OVERT# FAN_SPEED1 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108 PM_SLP_S0#
For abnormal shutdown PM_SLP_S0# <11,37>
<39> FAN_SPEED1 TYPEC_3A_1P5A# 29 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11
<34> TYPEC_3A_1P5A# E51TXD_P80DATA FANFB1/GPIO15 T85 @
DB2 30
<31> E51TXD_P80DATA E51RXD_P80CLK 31 EC_TX/GPIO16 110 AC_IN
RB751V-40_SOD323-2
SPOK_3V_5V 1 2 EC_RSMRST# <31> E51RXD_P80CLK PCH_PWROK 32 EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 112 EC_ON AC_IN <43>
<11,40> PCH_PWROK PWR_SUSP_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 ON/OFFBTN# EC_ON <44>
RB25
<35> PWR_SUSP_LED# PM_SLP_A# 36 SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 115 LID_SW# ON/OFFBTN# <37> 2 1 VCOUT1_PROCHOT#
DB3 GPI
<11> PM_SLP_A# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP# LID_SW# <38>
RB751V-40_SOD323-2 0_0402_5%
1 2 PCH_PWROK SUSP#/GPXIOD05 117 SW_PROCHOT# SUSP# <14,40,43,45,47> DGPU_AC_DETECT SW_PROCHOT#
GPXIOD06 118 H_PECI_R 1 2
PBTN_OUT# PECI/GPXIOD07 H_PECI <7> QB1A @
122 RB19 43_0402_1%
<11> PBTN_OUT# PBTN_OUT#/GPIO5D

3
DB4 PM_SLP_S4# 123 124 2N7002KDW_SOT363-6 D D
<11,40> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC VCOUT1_PROCHOT# VCOUT1_PROCHOT#
RB751V-40_SOD323-2 2 5
EC_VCCST_PG_R
AGND

1 2 G G
GND
GND
GND
GND
GND

VCOUT1_PROCHOT# is QB1B
high active when QB1 S S 2N7002KDW_SOT363-6

4
KB9022QD_LQFP128_14X14 mount @
11
24
35
94
113

ECAGND 69

Board ID RB4 DVT@

20mil
+3VLP_EC
CO-LAY with KB9032QA (SA000080J00) 1 2 BATT_TEMP
2015/1/9 acer require:
12K_0402_5% CB8
SD028120280 100P_0402_50V8J reserved protact circuit when
LB2 2 1 adaptor 107% happen
2

RB4 PVT@ FBMA-L11-160808-800LMT_0603

RB1 15K_0402_1% WE͗^DϬϭϬϬϬ<ϱϬϬ
Ra 100K_0402_1% SD034150280

RB4 MP@
1

4 AD_BID 20K_0402_1% 2 1 VR_HOT# 4

VR_HOT# <48>
SD034200280 RB20 0_0402_5%
1

1 H_PROCHOT# SW_PROCHOT#
RB4 CB4 2 1
<7,43> H_PROCHOT#
Rb 0_0402_5% 0.1U_0201_10V6K RB21 0_0402_5%
EVT@ @
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title
Analog Board ID definition, EC ENE KB9022
Please see page 3. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 36 of 57
A B C D E
 A B C D E

<ŽŶŶ͘ dWͬŽŶŶ͘
KEͬK&&dE 30
GND2
JKB1
+3V_PTP
RK1 29 +3VS RK3
100K_0402_5% KSO16 28 GND1 +3VALW 0_0402_5%
2 1 KSO17 27 28 2 @ 1
+3VLP 27
KSO0 26

<36> ON/OFFBTN#
ON/OFFBTN# Vinafix.com KSO1
KSO2
KSO3
25
24
23
26
25
24 5
UK1
1 +3V_PTP
+3V_PTP

KSO4 22 23 IN OUT @ CK2

22 1
1 KSO5 21 2 0.1U_0201_10V6K 1
21 GND

2
KSO6 20 CK1 2 1 JTP1
KSO7 19 20 4 3 1
19 EN OC 4.7U_0402_6.3V6M 1
4 3 KSO8 18 2 RK4 TP_CLK 2
18 1 TP_DATA 2
Test Only KSO9 17 CK3 SY6288C20AAC_SOT23-5 10K_0402_5% 3
SWK1 EVT@ KSO10 16 17 W^Ϯ 4 3

1
SKRPABE010_4P KSO11 15 16 1U_0201_6.3V6M EC_TP_INT# I2C_1_SDA_R 5 4
TOP 2 1 KSO12 14 15 2 I2C_1_SCL_R 6 5
KSO13 13 14 TP_PWR_EN <36> W,/Ϯ EC_TP_INT# 7 6
12 13 <7,36> EC_TP_INT# TP_EN 8 7
KSO14 <36> TP_EN
KSO15 11 12 9 8
KSI0 10 11 dWͺWtZͺE ĨŽůůŽǁ ^z^KE ďĞŚĂǀŝŽƌ 10 GND
KSI1 9 10 GND
KSI2 8 9 ACES_51524-00801-001
KSI3 7 8 CONN@
KSI[0..7] KSI4 6 7
KSI[0..7] <36> KSI5 5 6 SP01001A900

Co
KSO[0..17] KSI6 4 5 +3V_PTP +3V_PTP
KSO[0..17] <36> 3 4 +3V_PTP
KSI7
2 3
ON/OFFBTN# 1 2
1

1
RK7 RK10

1
2.2K_0402_5% 2.2K_0402_5%

G
ACES_85201-2805

<ĂĐŬ>ŝŐŚƚ CONN@
QK1B
2N7002KDW_SOT363-6
RK5
4.7K_0402_5%
RK6
4.7K_0402_5%

mp SP01000GO00

2
3 4 I2C_1_SCL_R

S
<12> I2C_1_SCL

2
+5VS JBL1

D
U1 1
5 1 +5VS_BL 2 1 1 2 TP_CLK
IN OUT 3 2 <36> TP_CLK TP_DATA
RK8 @ 0_0402_5%
3 <36> TP_DATA

2
2 4

G
2 GND 4 2

al
4 3 5 QK1A
<36> KBL_EN EN OC GND
6 2N7002KDW_SOT363-6
SY6288C20AAC_SOT23-5 GND 6 1 I2C_1_SDA_R

S
<12> I2C_1_SDA
ACES_51524-0040N-001

D
1 CONN@
1 @ 2
SP010022M00

Co
C3 RK9 0_0402_5%
0.1U_0201_10V6K
2

dWDϮ͘Ϭ
nfi
+FP_VCC
Finger Print
JFP2
Power Souce Check ETU@ 1
1
USB20_P5_L RK19 1
EGIS ETU801 +FP_VCC=5V USB20_N5_L RK20 1
2
2
0_0201_5%
0_0201_5%
2
3 2

de
3
+3VALW +3VALW_TPM +3VS +3VS_TPM
ELAN SA464K-2200 +FP_VCC=3.3V +FP_VCC ETU@
4
5 4
ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ 6 5
1 TPM@ 2 1 TPM@ 2 RK16 1 FP3V@ 2 0_0603_5% UK6 7 6
+3VALW G1
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

RW1 0_0603_5% RW2 0_0603_5% +5VALW RK17 1 FP5V@ 2 0_0603_5% 5 1 8

IN OUT G2
0.1U_0201_10V6K
CW2 TPM@

0.1U_0201_10V6K
CW4 TPM@

0.1U_0201_10V6K
CW5 TPM@

0.1U_0201_10V6K
CW6 TPM@
TPM@ CW7

TPM@ CW1

TPM@ CW8

TPM@ CW3

1 1 1 1 1
1

nti
FP@ CONN@
GND CK12 ACES_51522-00601-001
4 3
ŶĞĂƌƉŝŶϭ 4.7U_0402_6.3V6M SP01001A800
2

2 2 2 2 EN OC 2
1
3 CK11 SY6288C20AAC_SOT23-5 3
FP@ FP@
1U_0201_6.3V6M

al
ĂĚĚ ϭ ĐĂƉ ĨŽƌ D> ĚŽǁŶƐŝnjĞ 2
FP_PWR_EN <36>
+3VALW_TPM ŶĞĂƌ ƉŝŶϴ͕ϮϮ

RW16 1 TPM@ 2 10K_0402_5% TPM_PIRQ#

+FP_VCC
UW1 JFP1
1 10 PIN ETU801 SA464K-2200
VSB +3VALW_TPM GND
2 TPM@ 1 29 LK2 FPEMC@ 9
<11,36> PM_SLP_S0#
RW10 0_0402_5% 30 SDA/GPIO0 8 USB20_P5 3 4 USB20_P5_L GND 1 +FP_VCC(5V) +FP_VCC(3V)
SCL/GPIO1 VHIO +3VS_TPM <13> USB20_P5 3 4
22 8
6 VHIO USB20_P5_L 7 8 2 USBP D+
GPIO3 2 USB20_N5 2 1 USB20_N5_L USB20_N5_L 6 7
RW5 2 TPM@ 1 51_0402_5% 24 NC 3
<13> USB20_N5 2 1 5 6 3 USBN D-
<9> SOC_SPI_SO MISO NC 5
RW13 2 TPM@ 1 51_0402_5% 21 5 DLM0NSN900HY2D_4P 4
GND GND
<9>
<12>
SOC_SPI_SI
TPM_PIRQ#
2 TPM@ 1 18 MOSI/GPIO7 NC 7 SM070005U00 3 4 4
RW11 0_0402_5% PIRQ/GPIO2 NC 9 2 3
NC 10 DK2 FPEMC@ 1 2 5 NC NC
RW14 2 TPM@ 1 51_0402_5% 19 NC 11 6 3 USB20_N5_L 1
<9> SOC_SPI_CLK
2 TPM@ 1 20 SCLK NC 12 I/O4 I/O2 JXT_FP201H-008G10M 6 NC NC
<9> SOC_SPI_CS#2 SCS/GPIO5 NC
RW15 2 TPM@ 10_0402_5% 17 14 CONN@
<11,36> PLT_RST# RW12 0_0402_5% 27 PLTRST NC 15 SP010020S00 7 NC
13 NC NC 26 5 2
GPIO4 NC 25
+FP_VCC VDD GND 8 NC
NC 28
4 NC 31
@ T283 PP/GPIO6 NC USB20_P5_L
32 4 1
4 NC I/O3 I/O1 4
16 AZC099-04S.R7G_SOT23-6
GND 23
GND 33
PGND
NPCT750AAAYX_QFN32_5X5
TPM@

^ϬϬϬϬYϮϯϬ͕^/EWdϳϱϬzyY&EϯϮWdWD;^W/ŝŶƚĞƌĨĂĐĞͿ
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB & TP & TPM & FP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 37 of 57
A B C D E
 A B C D E

LID
+3VLP

2
UG1
OUT
3 LID1_SW# Vinafix.com
2 1 LID_SW#
LID_SW# <36>
VDD 1 RG6 0_0402_5%
1 GND 1
1
APX8132AI_TSOT-23-3
CG2
0.1U_0201_10V6K
2

SA00008K800, S IC APX8132AI-TRG SOT-23 3P HALL SENSOR

+3VS

5
UR2
IN OUT
1
+3VS_CARD

Co +3VS_CARD
reserve RTS5227 for VPRO

mp
2 1 1
RR14 GND
1
1

1 2 4 3 CR23 CR22
10K_0402_5% EN OC CR24 CR21 4.7U_0402_6.3V6M 0.1U_0201_10V6K
2 2
10U_0402_6.3V6M

@ 1 SY6288C20AAC_SOT23-5 @ @ 0.1U_0201_10V6K @ @
2

@ 2
@ CR25
2 2
1U_0201_6.3V6M

al
2

Close to Pin 27
Close to Pin 11 +3VS_CARD UR1

11 30 CR_SD_CD# RR10 1 2

Co
3V3_IN SD_CD# SD_CD# <30>
@ 0_0201_5%
2 1
20 mils 18
+DV33_18 32 CR_WAKE#
1U_0201_6.3V6M @ CR20 DV33_18 WAKE#
2 1
20 mils 10
+AV12_DV12_S
0.1U_0201_10V6K @ CR18 AV12
2 1
20 mils 14 for project which need fine tune SD signal can change to R
4.7U_0402_6.3V6M@ CR19 DV12S

nfi
2 1
0.1U_0201_10V6K @ CR13 15 CR_SD_D1 RR4 1 2 SD_D1_R
+CARD_3V3 SP1 SD_D1_R <30>
@ 0_0201_5%
+3VS_CARD 40 mils 12 16 CR_SD_D0 RR5 1 2 SD_D0_R
Card_3V3 SP2 SD_D0_R <30>
@ 0_0201_5%
+3VS_CARD 17 CR_SD_CLK RR15 1 2 SD_CLK_R
CR_LED# SP3 SD_CLK_R <30>
RR11 1 2 20 mils 375mA 27 @ 10_0402_5%

de
10K_0402_5% 3V3aux 19 CR_SD_CMD RR6 1 2 SD_CMD_R
RR12 1 @ 2 CR_WAKE# 12 mils SP4 @ 0_0201_5%
SD_CMD_R <30>
10K_0402_5% 6.2K_0402_1% 1 2 RR1 RREF 9 20 CR_SD_D3 RR7 1 2 SD_D3_R
CR_SD_CD# RREF SP5 SD_D3_R <30>
RR13 1 @ 2 Close pin < 200mil @ 0_0201_5%
10K_0402_5% @ 21 CR_SD_D2 RR8 1 2 SD_D2_R
SP6 SD_D2_R <30>
@ @ 0_0201_5%
2 PCIE_PTX_CR_DRX_P
1 3 29 CR_SD_WP RR9 1 2

nti
<13> PCIE_CTX_DRX_P5 HSIP SP7 SD_WP# <30>
CR14 @ 0.1U_0201_10V6K @ 0_0201_5%
2 1 PCIE_PTX_CR_DRX_N 4
<13> PCIE_CTX_DRX_N5 HSIN
CR15 @ 0.1U_0201_10V6K
3 2 1 PCIE_PRX_CR_DTX_P 7 3
<13,30> PCIE_CRX_DTX_P5 HSOP
CR16 @ 0.1U_0201_10V6K
2 1 PCIE_PRX_CR_DTX_N 8 13

al
<13,30> PCIE_CRX_DTX_N5 HSON NC
CR17 @ 0.1U_0201_10V6K
22
NC
RR2 1 2 CLK_PCIE_CR_P 5 23
<11,30> CLK_PCIE_P1 REFCLKP NC
@ 0_0201_5%
RR3 1 2 CLK_PCIE_CR_N 6 24
<11,30> CLK_PCIE_N1 REFCLKN NC
@ 0_0201_5%
25
NC
1 26
<11,21,30,31> PLT_RST_BUF# PERST# NC
31
2 NC
<11,30> CLKREQ_PCIE#1 CLK_REQ#

CR_LED# 28 33
GPIO GND

RTS5227S-GRT_QFN32_4X4
pin28: @
If GPIO NO use for LED function and
GPIO must pull high

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LID/RTS5227
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 38 of 57
A B C D E
 A B C D E

&EϭŽŶŶ ^ĐƌĞǁ,ŽůĞ
+5VS
40mil
RF1 1
Vinafix.com
2 0_0603_5% +VCC_FAN1 H3 H4 H5 H6 H32 H33 H36
1 2 H_3P0 H_3P0 H_4P5X4P0 H_4P5X4P0 H_4P0 H_2P5 H_2P5
1 FD1 FD2 1
@EMI@ CF2 CF1
1000P_0402_50V7K 4.7U_0402_6.3V6M

1
2 1 @ @

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ @ @ @ @ @ @
FD3 FD4

H23 H37 H25 @ @

1
H_2P7X2P0N H_2P7X2P0N H_2P0N
+3VS FIDUCIAL_C40M80 FIDUCIAL_C40M80

@ @ @

1
1

RF2

Co
10K_0402_5%
40mil
JFAN1 H17
2

+VCC_FAN1 1 H11 H14 H15 H16 H12 H13 H_3P2

FAN_SPEED1 2 1 H_3P3 H_3P3 H_3P3 H_3P3 H_4P2 H_4P2
<36> FAN_SPEED1 FAN_PWM1 3 2
<36> FAN_PWM1 4 3
1

1
5 4

mp

1
6 G1
CF3 G2
2 1000P_0402_50V7K ACES_50278-00401-001 @
@EMI@ CONN@ @ @ @ @ @ @

SP02000RR00 WIFI stand off

CPU stand off GPU stand off
2 2

al
Co ZĞƐĞƚ ŝƌĐƵŝƚ

nfi +3VLP

RG1 1 @ 2 0_0402_5%
MAINPWON <36,42,44>

2
de
RG3 RG2 1 2 0_0402_5%
EC_RST# <36>
10K_0402_5%

6
D
BI_GATE# 2
G 2N7002KDW_SOT363-6

nti
/ͺ'dW,ƚŽнZdsĂƚWtZƐŝĚĞ QG1A

3
D S
1

1
BI_GATE 5
3 <42> BI_GATE G C70 3
QG1B 0.1U_0201_10V6K
2N7002KDW_SOT363-6 S 2

al

4
‡•‡–—––‘

SWG2
BI_GATE 1 2 BI_GATE

3 4

SKRPABE010_4P

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole & Reset
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 39 of 57
A B C D E
 A B C D E

/ŶƚĞƌĨĂĐĞ For Power ON/Off Sequence PM_SLP_S3

CQ5
.1U_0402_16V7K +3VALW

2
1 2

G
1
Q1A
UQ1 R24 2N7002KDW_SOT363-6
1 14 @ JPQ2 100K_0402_5%
+5VALW VIN1 VOUT1 +5VS_OUT1
2 13 2 1 6

S
+5VS
Vinafix.com
VIN1 VOUT1 1 2 EC_VCCST_PG_R <11,36>

D
RQ2 0_0402_5%

2
2 1 5VS_ON 3 12 1 2 JUMP_43X118 MOW14, For tCPU28 200us(max)
ON1 CT1 CQ1 1000P_0402_50V7K SLP_S3# to VCCST_PWRGD deassertion

5
1 2 @ CQ4 4 11

G
1 +5VALW VBIAS GND 1
.1U_0402_16V7K
SUSP# 2 1 3VS_ON 5 10 1 2 1000P_0402_50V7K Q1B
RQ1 0_0402_5% ON2 CT2 CQ3 @ JPQ1 Q2A 2N7002KDW_SOT363-6
6 9 +3VS_OUT
1 2 2N7002KDW_SOT363-6 4 3

S
+3VALW VIN2 VOUT2 1 2 +3VS VR_ON <36,48>

D
1 2 @ CQ2 7 8 D
VIN2 VOUT2 2
.1U_0402_16V7K JUMP_43X118
<11,36> PM_SLP_S3# MOW14, For tPLT17 200us(max)
15 G SLP_S3# to IMVP VR_ON deassertion
GPAD

5
1 2

G
AOZ1331DI_DFN14_2X3 S

1
CQ6 Q2B
.1U_0402_16V7K 2N7002KDW_SOT363-6
4 3 SUSP#

D
MOW14, For tPLT18 200us(max)
SLP_S3# to VCCIO VR disable

2
G
Q3A @

Co
+5VALW +0.6VS_VTT +1.2V_VDDQ +5VALW 2N7002KDW_SOT363-6
+2.5V 1 6

S
SYS_PWROK <11,36>
2

D
2
R25 R26 R27 R28

2
100K_0402_5% @ @ 470_0603_5% 470_0603_5% 100K_0402_5%

5
R31 @ @

G
470_0603_5% +3VALW Q3B @

mp
+0.6VS_VTT_R
1

1
SUSP @ 2N7002KDW_SOT363-6

1
1

1
Q4A @ Q4B @ +1.2V_VDDQ_R SYSON# 4 3

S
PCH_PWROK <11,36>

D
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 R29
6

D D Q5A @ Q5B @ 100K_0402_5%

D

1
2 5 SUSP 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
14,36,43,45,47> SUSP#

3
G G SYSON# 2 D D

2
2 G SYSON# 2 5 SYSON Q6A PM_SLP_S4 2
SYSON <14,36,45>

al
1

S S Q7 S G G 2N7002KDW_SOT363-6
1

5
R30 L2N7002LT1G_SOT23-3 D

G
10K_0402_5% @ S S 2 Q6B
<11,36> PM_SLP_S4#

4
@ G 2N7002KDW_SOT363-6
2

S 4 3 SYSON

S
1

D
Co
MOW14, For tPLT15 200us(max)
SLP_S4# to VDDQ ramp down

nfi
+5VS +1.05VS_1.0VSDGPU

+1.8VALW_PRIM RV162 1.8A

2
0_0805_5%
1 N17S@ 2 +3VS_1.8VALW_VIN R4916 R574 R574 N17S@
+3VS 100K_0402_5% 47_0603_5% 10_0603_1%

de
VGA@ N16X@ SD014100A80
RV163 1 N16X@ 2 0_0603_5% CV236 VGA@

1
UV16 .1U_0402_16V7K
CV258 1 2 1 14 1 2 PEX_VDD_EN# +1.05VSDGPU_R
DV9 VGA@ VGA@ 1U_0201_6.3V6M 2 VIN1 VOUT1 13
VIN1 VOUT1 +3VS_1.8VSDGPU_AON
2 BAV70W_SOT323-3
<12,22> DGPU_PWR_EN

6
1 DGPU_PWR_EN_AON 3 12 1 2

nti
680P_0402_50V7K
3 ON1 CT1 CV238 VGA@ PEX_VDD_EN 5 G
D D
G 2 PEX_VDD_EN#
<21,51> 1.35VS_DGPU_PG +5VALW <22,52> PEX_VDD_EN
RV164 CV259 1 2 4 11 Q2515A S S Q2515B
2 VGA@ 1 100K_0402_5% VGA@ 1U_0201_6.3V6M VBIAS GND PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6

1
3 3_1.8VSDGPU_MAIN_EN 5 10 1 2 680P_0402_50V7K N17S@ N17S@ 3
<21,22> 3_1.8VSDGPU_MAIN_EN ON2 CT2
CV235 1 2 CV239 VGA@
@ .1U_0402_16V7K 6 9 Q2515 N16X@
+3VS_1.8VSDGPU_MAIN

al
+3VS_1.8VALW_VIN 7 VIN2 VOUT2 8 1 2 2N7002KDW_SOT363-6
VIN2 VOUT2 SB00000EO00
CV262 1 2 15 CV237 +5VS +VGA_CORE
@ 1U_0201_6.3V6M GPAD .1U_0402_16V7K
EM5209VF_DFN14_2X3 VGA@

2
VGA@
R4911 R4910
100K_0402_5% 47_0603_5%
@ @

1
VGA_CORE_EN# +VGA_CORE_R +5VS +1.35VSDGPU

2
@
R1007 R571
100K_0402_5% 47_0603_5%
3

6
@
3_1.8VSDGPU_MAIN_EN 5 G
D D
G 2 VGA_CORE_EN#

1
Q2516A S S Q2516B
PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6 1.35VSDGPU_PWR_EN# +1.35VSDGPU_R
4

1
@
@

6
D D
1.35VSDGPU_PWR_EN 5 2 1.35VSDGPU_PWR_EN#
<21,51> 1.35VSDGPU_PWR_EN G G

S S

1
Q2513B Q2513A
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
4 @ @ 4
нϯs^ƚŽнϯs^'WhͺKEĨŽƌ'Wh

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
Date: Thursday, July 12, 2018 Sheet 40 of 57
A B C D E
 A B C D E

Vinafix.com
1 1

EMI 90W@ PL102

5A_Z120_25M_0805_2P

1 2

+19V_ADPIN 5A_Z120_25M_0805_2P
EMI@ PL101
+19V_VIN
1 2

@ PJP101
ACES_50305-00441-001_4P

1
1

1
EMI@ PC104

Co
2 EMI@ PC105 PC102 EMI@ 1000P_0402_50V7K

2
3 1000P_0402_50V7K 100P_0402_50V8J

2
4
GND
GND

2
mp 2

al
Co
@ PR101
0_0402_5%
1 2
+3VLP +CHGRTC

nfi
+RTCBATT

de 1
PR102
2

560_0603_5%
@RTC_CHG
1
PR103

560_0603_5%
@RTC_CHG
2
+RTCBATT_CHG

nti 3

al

4 4

Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ȁ”‡Ǧ…Šƒ”‰‡
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 41 of 57
A B C D E
 A B C D E

2013/07/23
change PC5 and PC6 function field from 37.1 to 47.1

+3VLP
Vinafix.com
1 1

1
@ PC205

1
PR207 100_0402_1% 0.1U_0402_25V7K
MB:Battery Con Put TOP Side

2
1 2
EC_SMB_DA1 <36,43>
PR205 100_0402_1% @ PR215 @ PR214
1 2 10K_0402_1% 10K_0402_1%
EC_SMB_CK1 <36,43> <45,47>

2
1
@ PU201
Battery Bot Side PR202 @ PR213 1 8
200K_0402_1% 100K_0402_1% VCC TMSNS1
1 2 2 7 2 1
PIN1 GND @ PJP201 +3VLP GND RHYST1

2
PIN2 GND 1 2
1
<36,39,44> MAINPWON
MAINPWON 3
OT1 TMSNS2
6 @ PR216

1
1 2 47K_0402_1%

Co
PIN3 SMD 2 3
3 4
EC_SMB_DA1-1 BATT_TEMP <36,43> 4
OT2 RHYST2
5
EC_SMB_CK1-1 PR203 1K_0402_1% @ PH202
PIN4 SMC 4 5 BATT_TS G718TM1U_SOT23-8 100K_0402_1%_NCP15WF104F03RC
5 6
PIN5 TEMP BATT_B/I

2
6 7
PIN6 BI 7 8
8 9 +RTCVCC
PIN7 Batt+ GND 10

mp
PIN8 Batt+ GND
CVILU_CI9908M2HR0-NH
2016/11/16 update

1
PR212
100K_0402_5% For KB9022
PQ201 Change to SB00000QO00,
sense 20mȍ Active Recovery
SB501380010(BSS138LT1G Del)

2
2 2

al
1
D
<39> BI_GATE 2 PQ201
G LBSS139LT1G 1N SOT-23-3 45W PR206 58.5W,0.61V Active=recovery
+12.6V_BATT+ S
10K ohm

3
EMI@ PL201 BI_S

2
Co
5A_Z120_25M_0805_2P
1 2 PR217
change PL201, PL202 +12.6V_BATT 65W PR206
SM01000C000 to comm PL202 0_0402_5% 84.5W,0.61V
1 2
19.1K ohm Active=recovery
part SM01000P200

1
5A_Z120_25M_0805_2P
90W PR206

nfi
EMI@
117W,0.61V
30.1K ohm Active=recovery
1

EMI@ PC201 EMI@ PC202

1000P_0402_50V7K 0.01U_0402_25V7K PH1 under CPU botten side :
2

PH1 2V 1V CPU thermal protection at 89 +-3 degree C

2013/06/07
Add for ENE9022 Battery Voltage drop detection. de Recovery at 56 +-3 degree C

3
Connect to ENE9022 pin64 AD1.

nti +3VLP_ECA 3

al
ADP_I <36,43>
+19VB_5V
VAL50/ZAL20 Battery is 3-cell NVDC design.

1
B+=9V PR204
Change PR12=50k if Battery is 2-cell NVDC design 16.9K_0402_1%
90W@ PR206
B+=6V
1

30.1K_0402_1%

2
PR209
VCIN0_PH <36>
750K_0402_1% 65W@
PR206
@ PR210 19.1K_0402_1%
2

0_0402_5%

1
1
1 2
VCIN1_BATT_DROP <36> PC203 must close to EC pin

2
PH201
VCIN1_ADP_PROCHOT <36>
@ PC203
100K_0402_1%_NCP15WF104F03RC 0.1U_0402_25V6

1
1

1
2
2

PC204 PR211 PR208

0.1U_0402_25V6 150K_0402_1%
T202 T201 must close to PH201
T202@ 10K_0402_1%
1

2
T201@

ECAGND <36>

4 4

Security Classification
2018/01/10
Compal Secret Data
2018/11/04 Title
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ǦȀ
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 42 of 57
A B C D E
 5 4 3 2 1

Module model information

ISL95520_Hybrid_Boost_V2.mdd

Protection for reverse input

Vinafix.com
Vgs = 20V
Vds = 60V
Id = 250mA

1
D D D
2 PQ301 max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W
G L2N7002WT1G_SC70-3
S
CSR rating: 1W +19VB

3
VCSIP-VCSIN spec < 81mV
1 2 1 2

PR301 PR302
1M_0402_1% 3M_0402_5%
PQ311
PQ310 +19V_P1 AON7506_DFN33-8-5
Need check the SOA for inrush EMB04N03H_EDFN5X6-8-5 PR303
1 1 +19V_P2 0.01_1206_1% EMI@ PL302 +19VB_CHG
2 2 FBMA-L11-201209-800LMA50T
5 3 3 5 1 4 1 2
+19V_VIN

PC305 @EMI@

PC324 @EMI@
EMI@
2200P_0402_25V7K
2 3 Isat: 10A

10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V6

0.1U_0402_25V6
CSIP_CHG_R
DCR: 14mohm

1
CSIN_CHG_R

PC302

PC303

PC304
@ PC322 @ PJP1

2
Co
1 2 1 2
1 2
1000P_0402_25V JUMP_43X118

1
2_0402_5%
Co-lay jump and ISN choke.

PR305
PR304
1 0_0402_5%
PR306

2
499K_0402_1%

2
mp
PC306
PQ312
2

4.02K_0402_1%

4.02K_0402_1%
1 2 AON7506_DFN33-8-5

1
L->H 0.1U_0402_25V6 2
2.04 vin min w/o 2M =17.41 5 3

C H->L PR309 C

PC307 0.22U_0603_25V7K
2.02 vin min w 2M =17.77 100_0402_1%

4
PR307

PR308
al
1 2 +12.6V_BATT
1

CMSRC_CHG
2200P_0402_50V7K
66.5K_0402_1%

@ PC308
1
PR310

PC301

1
ASGATE_CHG 1 2
2

Co

BGATE_CHG
2

OPCN_CHG 2
0.1U_0402_25V7K

CSIN_CHG
CSIP_CHG

OPCP_CHG

VBAT_CHG
0x3CH <BIT9> PSYS current gain
Rs1 = 10mȍ and Rs2 = 5mȍ o r Rs 1 = 10m ȍ a nd R s2 = 10ȍ
m @
1 VDD_CHG

PD301
BIT0 = 1.14uA/W PQ305
1 2 VDDP_CHG
BIT1 = 0.285uA/W

AON7506_DFN33-8-5
=========================================================
Rs1 = 20mȍ and Rs2 = 10mȍ or Rs1 = 20mȍ and Rs2 = 20 m
ȍ RB751V-40_SOD323-2
100K_0402_1%

support Turbo boost : 2200P Support max charge 3.5A

32

31

30

29

28

27

26

25
BIT0 = 2.28uA/W PU301
no support Turbo boost : 0.1u Choke 4.7uH SH00000YC00 (Common Part) Power loss: 0.245W

nfi
BIT1 = 0.57uA/W
PR311

CSIP

ASGATE

QPCP

BGATE
CSIN

CMSRC

OPCN

VBAT
PC309 4 (Size:6.6 x 7.3 x 3 mm) CSR rating: 1W
Ipsys = KPSYS ˢ x ˢVAD P x IAD P + VBA T
( Tˢ
x IBA ) PR312 0.47U_0402_25V6K (DCR:28m~33m) VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R
1 2
R_Psys = 1.2V / Ipsys
2

ACIN BOOT PR315

KPSYS = 1.14uA/W UG_CHG
adapter wattage = 45W 2 23 0_0603_5% PL301 0.01_1206_1%

3
2
1
<36> AC_IN @ PR314 0_0402_5% ACOK UGATE 4.7UH_PCMB063T-4R7MS_8A_20% +12.6V_BATT
Battery wattage = 40Wh
1

EC_SMB_DA1_R 3 LX_CHG +17.4V_BATT_CHG 1

158K_0402_1%

1 2 22 1 2 4
Ipsys = 1.14 x (45+40) = 96.9uA

de
<36,42> EC_SMB_DA1 SDA PHASE
PR313

@ PR316 0_0402_5%
R_Psys = 1.2V / 96.9uA = 12.3K-ohm. EC_SMB_CK1_R 4 LG_CHG

4.7_1206_5%
1 2 21 2 3
<36,42> EC_SMB_CK1 SCL LGATE

1
=====================================

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
@EMI@ PR320
PR317 0_0402_5% PQ306

5
adapter wattage = 65W 1 2 5 20 VDDP_CHG
2

<7,36> H_PROCHOT# PROCHOT# VDDP

1U_0201_6.3V6M
Battery wattage = 40Wh

AON7506_DFN33-8-5

1
2 1K_0402_1%AMON_ISL95520 6 VDD_CHG

PC310

PC311

PC312
Ipsys = 1.14 x (65+40) = 119.7uA PR318 1 19 1 2
<36,42> ADP_I AMON VDD

1U_0201_6.3V6M
PC326

PC314

PC325
R_Psys = 1.2V / 96.9uA = 10K-ohm.

2
2 1K_0402_1%BMON_ISL95520 7

1U_0201_6.3V6M
PR321 1 ISL88739AHRZ-T_QFN32_4X4 18 PR319 4.7_0402_5%

2
BMON DCIN

680P_0402_50V7K
**Design Notes** 4

nti BATGONE
Close to EC. 8 17 PC313
For 45W/65W /90W system, 2S/3S/4S battery NC NTC
1U_0201_6.3V6M
CCLIM

2
ACLIM
COMP

B Maximum Charging current 3.5A

1
PROG

B
AGND

CSON

CSOP

@EMI@ PC315
FSET
PR323

1
Maximum Battery discharge power 55W 100K_0402_1%

3
2
1
1

#Register Setting PC316 PC317

2
0.1U_0402_25V6 0.1U_0402_25V6 PR322 PD1
1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function
33

10

11

12

13

14

15

16
Follow adapter and 0_0402_5% PR324 10_1206_5% 3
+19V_VIN
2

2. Disable turbo when AC only battery wattage in 1 2 1

al 2
#Circuit Design Close to Vsys current source. 2
2

2
FSET_CHG

EC.

PC318
1U_0603_25V6
1. ACLIM and CCLIM are devider voltage control. Base on CPU Core VR design. @ VF = 0.38V For 4S per cell 4.35V battery
The resistor is pop on CPU VR schematic. S SCH DIO BAS40CW SOT-323
1

2. Use 7X7 choke and 3X3 H/L side MOSFET

1
PR326
Charge current 3A PR325 @
ACIN_CHG
10K_0402_1% 1 2
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) VDD_CHG +12.6V_BATT
Power density : 0.61 (23X16) VDD=5V
2

0_0603_5%
#Protect function

1
CCLIM_CHG
1. ACOVP : VCC voltage > 24V
200K_0402_1%

4S_BATT@ PR342
2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).
1

ACLIM_CHG 2M_0402_1%
3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).
PR328

PR329
PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R
4. CHGOCP : based on charge current setting 200K_0402_1%

2
5. BATOVP : 4.6V/Cell +3VS Pull high on HW side COMP_CHG PR330 2_0402_5%
2

1
6. BATLOWV : No.
@ PR331 PR333=0 ohm, Fs=500KHZ ~ +/- 15%
7. TSHUT : 150C PC319 4S_BATT@ PQ308
1

1
100_0402_1%

76.8K_0402_1% 0.1U_0402_25V6

2
PR332

1 2 PR333 LTC015EUBFS8TL_UMT3F
1

CSON_CHG CSON_CHG_R
150K_0402_1%

560P_0402_50V7K

22.6K_0402_1% 1 2
1

1
PR335

@VGA@ @VGA@ OCCP setting

1
PC320

PR340 PR341 @ PQ309

2

2
1

D 0_0402_5%
75K_0402_1%

10K_0402_1% 10K_0402_1% PR334

2
1

AC_IN
0.015U_0402_25V7K

2 PR337 4S_BATT@ PR343

2

G 100K_0402_1% @ BATT_TEMP <36,42> 100K_0402_1%

2

1
PR336

PC321

S 1 2 2
3

<36> BATT_4S
L2N7002WT1G_SC70-3 BATGONE(BATT_TEMP)
2

<10,21,36> DGPU_AC_DETECT logic high: above 2.4V

2

Hybrid boost power mode logic low: under 0.8V

Cell = 4s 4S_BATT@

3
1
PQ315 D
6

D 2
2 <14,36,40,45,47> SUSP# G
A A
G
@VGA@ @VGA@ @VGA@ 2N7002KW_SOT323-3 S

3
PQ314 PQ313B S PQ313A
1
1

RUM001L02_VMT3 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 ICClimit : 7.73A

Delta I : 1.44A
3

1C charge current :6.48A

D
H_PROCHOT# 2 AC_IN 5
G Battery current limimed by CCLIm ~ 3.89A.
Adapter current limimed by ACLIm ~ 4.33A.
S (PR779 and PQ741 are for change ACLIm when AC in)
4

Security Classification Compal Secret Data Compal Electronics, Inc.

3

(Rs1 = 10mȍ and Rs2 = 5mȍ or Rs1 = 20mȍ and Rs2 = 10mȍ) .
CC_LIM = VccLIM / 64 x Rs2 Issued Date 2018/01/10 2014/12/15 Title
=============================================================
Deciphered Date
WtZͺ,Z'Z
(Rs1 = 10mȍ and Rs2 = 10mȍ or Rs1 = 20mȍ and Rs2 = 20mȍ) . THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
CC_LIM = VccLIM / 32 x Rs2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
============================================================= MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AC_LIM = Vac_LIM / 32 x Rs1 Date: Thursday, July 12, 2018 Sheet 43 of 57
5 4 3 2 1
 A B C D E

H/S Rds(on):typ:12.4mOhm, max:15.8mOhm

Module model information Idsm(TA=25)=13A, Idsm(TA=70)=7.8A
Ploss=0.42W
RT6575D_DMOS_single_V1.mdd
RT6575D_DMOS_dual_V1.mdd L/S Rds(on):typ:9.1mOhm, max:11.6mOhm
Idsm(TA=25)=15A, Idsm(TA=70)=9A
Ploss=0.14W

Vinafix.com
CHOKE:4.7uH, DCR 35mOhm
1
Ploss=1.77W 1

+3VLP
PC401
4.7U_0402_6.3V6M
1 2

Output capacitor ESR need follow

@ PC402 @ PC403
100P_0402_50V8J 100P_0402_50V8J
below equation to make sure feed back
1 2 1 2 loop stability
ESR=20mV*L*fsw/2V
PR402 PR401

Co
13.3K_0402_1% 31.6K_0402_1%
1 2 1 2
VFB=2V VFB=2V

PR403 PR404
20K_0402_1% 20K_0402_1% +19VB_5V
1 2 1 2 +19VB @ PJ401

mp
JUMP_43X79
1 2
1 2

PR405 PR406
71.5K_0402_1% 105K_0402_1%

2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M
2 2

0.1U_0402_25V6
@ PJ402 1 2 1 2
+19VB

al
JUMP_43X79

1
+19VB_3V

@EMI@ PC404

EMI@ PC405

PC406

PC422
1 2
1 2

CS2_3V

CS1_5V
+3VLP

FB_3V

FB_5V
POK need pull high, it

2
2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6

will pull high on VS

transfer circuit
1

1
@EMI@ PC407

EMI@ PC408

PC409

PC421

Co
PU401

21
5

1
PR407 RT6575DGQW(2)_WQFN20_3X3
2

20K_0402_1%

CS2

FB2

LDO3

FB1

CS1

GND
1
PQ402 6 20 5V_EN PQ401
<36> 3V_EN EN2 EN1
AONH36334_DFN3X3A8-10 AONH36334_DFN3X3A8-10

nfi
7 19
<36,47> SPOK_3V_5V PGOOD VCLK
4

4
PL402 LX_3V 8 18 LX_5V
D1

D1

D1

G1

G1

D1

D1

D1
3.3UH_6.3A_20%_7X7X3_M PR408 PHASE2 PHASE1 PR409 PL401
PC411
2.2_0603_5% 2.2_0603_5% 3.3UH_MMD-10DZ-3R3M-X2

de
2 1 LX_3V 10 9 1 2 BST_3V_R 1 2 BST_3V 9 17 BST_5V 1 2 BST_5V_R 1 2 9 10 LX_5V 2 1
+3VALWP D1 D2/S1 BOOT2 BOOT1 D2/S1 D1 +5VALWP
PC410
0.1U_0402_25V7K
UG_3V UG_5V 0.1U_0402_25V7K
4.7_1206_5%

680P_0603_50V8J 4.7_1206_5%
10 16
G2

G2
S2

S2

S2

S2

S2

S2
UGATE2 UGATE1
1

1
@EMI@ PR410

@EMI@ PR411
LGATE2

LGATE1

220U_6.3V_ESR18M_6.3X4.5
5

5
220U_6.3V_ESR18M_6.3X4.5

LDO5

BYP1
nti
VIN
1 1
2

2
+ +
PC413

PC414
11

VIN_3/5V 12

13

14

15
680P_0603_50V8J

3 3
1

1
2 LG_3V LG_5V 2
@EMI@ PC416

@EMI@ PC417
al
PR412
2.2_1206_1% +5VALWP
2

2
+19VB 1 2
+5VLP

1U_0603_25V6K

4.7U_0402_6.3V6M
1

1
@ PC418

PC419
2

PR413 @ PJ403
2.2K_0402_5% +3VALWP 1 2 +3VALW
1 2 1 2
<36> EC_ON
JUMP_43X118
PR414
1 2
5V-OCP=13.5A
<36,39,42> MAINPWON
3V-OCP=8.9A
0_0402_5%
@ PJ404
4 5V_EN 1 2 4
+5VALWP 1 2 +5VALW
1M_0402_1%

4.7U_0402_6.3V6M

JUMP_43X118
1

1
PR415

PC420
2

Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

2

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ǧ͹Ǥ͹Ȁͻ
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 44 of 57
A B C D E
 A B C D E

Pin19 need pull separate from +1.35VP.

Vinafix.com
+19VB_1.2VP If you have +1.35V and +0.675V sequence question,
you can change from +1.35VP to +1.35VS.
0.6Volt +/- 5%
@ PJ503 TDC 0.7A
JUMP_43X79
1
1 2 +19VB_1.2VP PR502 Peak Current 1A 1

+19VB 1 2 2.2_0603_5%
BST_1.2VP_R 1 2 BST_1.2VP

10U_0603_25V6M

10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
+1.2VP

1
@EMI@ PC502

EMI@ PC503

PC504

PC505
UG_1.2VP +0.6VSP

2
PQ503
AON7408L_DFN8-5
LX_1.2VP

10U_0402_6.3V6M

10U_0402_6.3V6M
5

1
PC506

1
PC507

PC508
0.1U_0402_25V7K

16

17

18

19

20
2

2
Co

VLDOIN
PHASE

UGATE

BOOT

VTT
4 21
PAD
LG_1.2VP 15 1
LGATE VTTGND
PL502

1
2
3
14 2
PGND VTTSNS

mp
1UH_11A_20%_7X7X3_M PR503
30.9K_0402_1% PU501
1 2LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PC509 CS RT8207PGQW _W QFN20_3X3 GND

1
1U_0402_10V6K

5
1 2 12 4 VTTREF_1.2VP
@EMI@ PR504 PR505 VDDP VTTREF
2 4.7_1206_5% 5.1_0603_5% 2

al
1 2 VDD_1.2VP 11 5
+5VALW +1.2VP

1 2
VDD VDDQ

1
PGOOD
PC516
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

4 2 1

TON
1
@EMI@ PC518 PC517 0.033U_0402_16V7K
PC510

PC511

PC512

PC513

PC514

PC515

FB
S5

S3

2
1
680P_0402_50V7K @ PD501
2

2 PQ502 1U_0402_10V6K RB751V-40_SOD323-2

Co

10

6
AON7506_DFN3X3-8-5 PR511

1
2
3
2.2_0402_1%

FB_1.2VP
2

TON_1.2VP

EN_1.2VP
PR506
+5VALW

EN_0.6VSP
6.19K_0402_1%
PR507 1 2 +1.2VP
470K_0402_1%

nfi
+19VB_1.2VP 1 2

1
@ PR501
0_0402_5%
Vout=0.75V* (1+Rup/Rdown)
<14,36,40> SYSON
SYSON 1 2 PR508 =0.75*(1+(6.19/10))
10K_0402_1%

de
=1.21V

2
1
@ PC501
+5VALW 0.1U_0402_10V7K

2
+3VALW @ PR509
0_0402_5%

nti
1 2
<14,36,40,43,47> SUSP#
@ PJ505
3 JUMP_43X39 @ PR510 @ PJ501 3
1

1 2 VIN_2.5V PC524 0_0402_5% JUMP_43X118

1 2 1 2 1 2
+1.2VP +1.2V_VDDQ

al
1U_0201_6.3V6M <8> SM_PG_CTRL 1 2
2
1

1
@ PC519 @ PJ502
PC521 JUMP_43X39
4.7U_0402_6.3V6M 0.1U_0402_10V7K 1 2
+0.6VSP +0.6VS_VTT
2

2
PU502 1 2
G9661MF11U_SO8
@ PR515 4 5
3 VPP NC 6
0_0402_5%
EN_2.5V VIN VO +2.5VP MOSFET: 3x3 DFN
SYSON 1 2 2 7
H/S Rds(on): 27mohm(Typ), 32mohm(Max)
GND

1 VEN ADJ 8
22U_0603_6.3V6M
0.01U_0402_25V7K

POK GND Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

1
0.1U_0402_16V7K

PR517
PC522
9
1

PR516
PC520

PC523

21.5K_0402_1%
Rup L/S Rds(on): 13mohm(Typ), 15.8mohm(Max)
Vout=0.8V* (1+(21.5/10)) = 2.52V 0.8%Idsm: 12A@Ta=25C, 10.5A@Ta=70C
2

1M_0402_5%
2

2
2

FB_2.5V
@ Choke: 7x7x3
Rdc=14mohm(Typ), 15mohm(Max)
1

Mode Level +0.6VSP VTTREF_1.2V

PR518
S5 L off off Switching Frequency: 538kHz
10K_0402_1%
Rdown S3 L off on Ipeak=7.5A
S0 H on on Iocp=Ipeak*1.2A
2

4
OVP: 110%~120% 4
@ PJ504
Note: S3 - sleep ; S5 - power off VFB=0.75V, Vout=1.365V
JUMP_43X39
1 2
MOSFET footprint: SIS412DN
+2.5VP 1 2 +2.5V

Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
;͸Ͷͽ
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻͶͷȀǦ;Ϳ͸
Date: Thursday, July 12, 2018 Sheet 45 of 57
A B C D E
 A B C D E

EN pin don't floating

If have pull down resistor at HW side, pls delete PR702

Vinafix.com
1 нϭϵsͺϭs>t @EMI@ PR605 @EMI@ PC602
1

4.7_1206_5% 680P_0603_50V7K @ PJ601

@ PJ602 1 2 SNUB_1VALW 1 2 JUMP_43X118
PU601 1 2
JUMP_43X79
+19VB_1VALW +1.05VALWP 1 2 +1.05VALW_PRIM
нϭϵs 2
2 1
1 2
IN PG
9
PR606
0_0603_5%
PC603

10U_0603_25V6M
0.1U_0402_25V6
3 1 BST_1VALW 1 2 BST_1VALW_R1 2 PL602

2200P_0402_50V7K
IN BS

1
1UH_6.6A_20%_5X5X3_M

EMI@ PC604

@EMI@ PC605

PC606
>Kͺϯs LX_1VALW
4
IN LX
6
0.1U_0402_25V7K
1 2
нϭ͘Ϭϱs>tW

220U_B2_4VM_R35M
2

2
5 19 1

15.4K_0402_1%

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
IN LX
1

PR608

1
PR607 7 20 +

PC608

PC609

PC610

PC611

PC612

PC615

PC616
GND LX
0_0402_5% 8 14 FB_1VALW Rup

2
GND FB 2 @
2

2
ILMT_1VALW 18 17 LDO_3V
GND VCC
1

1
EN_1VALW 11 10
EN NC

Co
@ PR609 PC613 FB = 0.6V

1
ILMT_1VALW 13 12 2.2U_0402_6.3V6M

2
ILMT NC PR610
0_0402_5%
15 16
+3VALW Rdown
2

BYP NC 20K_0402_1%
21
Ipeak=9.5A

2
PAD Imax=6.65A
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.

1
The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC15

mp
PC614
is pull low, floating or pull high 1U_0201_6.3V6M

2
Vout=0.6V* (1+Rup/Rdown)
+3VALW =0.6*(1+(15.4/20))
Vout=1.062V
2 2
2

al
@ PR603
10K_0402_1%
1

PR602
EN_1VALW 1 2

Co
+1.8VALW_PG <47>

0_0402_5%
1

PR601
0.22U_0402_10V6K
2

1M_0402_1%
@ PC601
2

nfi
de
3

nti 3

al

4 4

Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 46 of 57
A B C D E
 A B C D E

@N17S_VGA@
Current limit = 4.7A(min) PR701
0_0402_5%
0.4% @N17S_VGA@ EN_1.8VALWP1 2
PR705 SPOK_3V_5V <36,44>
10K_0402_5%

1
2 1 @N17S_VGA@
нϯs>t @N17S_VGA@ PC703
PR703 0.1U_0402_16V7K @ PJ702

2
1M_0402_5% JUMP_43X39
1 2
+1.8VALWP +1.8VALW_PRIM

2
Vinafix.com
1 2
<46> +1.8VALW_PG

@N17S_VGA@
PU701
1 1
9
1 PGND 8
FB SGND (Common Part) SH00000YG00
+3VALW VIN_1.8V 2 7 4*4*2
PG EN
3 6 LX_1.8V 1 2
@ PJ701 IN LX +1.8VALWP

@N17S_VGA_EMI@
1 2 4 5 @N17S_VGA@

20.5K_0402_1%

68P_0402_50V8J

22U_0603_6.3V6M

22U_0603_6.3V6M
1 2 PGND NC

1
PL703

4.7_0603_5%

@N17S_VGA@

@N17S_VGA@

@N17S_VGA@

@N17S_VGA@
1
1UH_2.8A_30%_4X4X2_F

PR717

PR702

PC704
JUMP_43X79

1
SY8003ADFC_DFN8_2X2

PC705

PC727
Rup

1
@N17S_VGA@

2
PC702

2
22U_0603_6.3V6M

2
FB_1.8V

680P_0402_50V7K
@N17S_VGA_EMI@

1
@N17S_VGA@

1
FB=0.6V PR704

PC726
Co
Note:Iload(max)=3A 10K_0402_1%
Rdown

2
Function Field :
PWR.Plane.Regulator_1.8V - 35.15
Rest of support elements - 35.16

mp
+3VALW

2
+5VALW
@ PJ704

2
JUMP_43X39
2 @ PJ705 2

al 1
JUMP_43X39
VIN_1.8VALW +1.8VALWP
1 2
+1.8VALW_PRIM
1
1 2

1
VIN_1.8VALW PC701
1U_0201_6.3V6M

2
1

PC730
4.7U_0402_6.3V6M

Co
2

PU702
G9661MF11U_SO8
4 5
PR718 VPP NC
3 6
SPOK_3V_5V 1 2 EN_1.8VALW 2 VIN VO 7 +1.8VALWP

GND
1 VEN ADJ 8

0.01U_0402_25V7K
POK GND

PC729
0_0402_5%
1

1
PR721

9
@ 12.7K_0402_1%
Rup

nfi
PC728
2

2
PR719 0.1U_0402_16V7K

1
1M_0402_1% FB_1.8VS
2

+3VALW PC731
22U_0603_6.3V6M

2
1
2

de
PR720
PR722 10K_0402_1%
10K_0402_1%
Rdown

2
1

+1.8VALW_PG

Vout=0.8V* (1+Rup/Rdown)

nti
Vout=0.8V* (1+(12.7/10)) = 1.816V
3 3

+5VS

2s_battery@
PQ701
P-MOS
AON7403L_DFN8-5
1
@ PJ703
JUMP_43X79
1 2
2
al @2s_battery_EMI@
PC711
680P_0603_50V7K
2 1
5*5*H1.5
Idc: 3A
Isat: 4A

2
@2s_battery_EMI@
PR710
4.7_1206_5%
1

2s_battery@ PD701
SS1P4-M3-84A_DO-220AA2
1 2s_battery@ PL702
2 5 4.7UH_PCME051E-4R7MS_3A_20%
3 1 2 2 1 +12VSP 1 2
+5VALW +INVPWR_B+
SH00000OG00
10U_0603_25V6M
2s_battery@ PC714
1

LX_12VSP @2s_battery bead@

100P_0402_25V8K
1500P_0402_50V7K
4
1

PL701
2s_battery@ PC713

PC716
1

2s_battery@ PR711 2s_battery@ 2s_battery@ PC715 2s_battery@ PR712 5A_Z120_25M_0805_2P

2

100K_0402_1% PC712 10U_0603_25V6M 88.7K_0402_1%

PC717

PC719

PC718

PC720

PC721
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V6

2200P_0402_50V7K
2

0.022U_0402_25V7K
2

2
6

1
2 1
@2s_battery@
2
LX

LX
1

2s_battery@

2s_battery@

2s_battery@
2

2s_battery_EMI@
@2s_battery_EMI@
8 2FB_12VSP
2s_battery@ PR713 Vin FB
10K_0402_1%
9 10 SS_12VSP 1 2
2

FREQ SS
2s_battery@ PC722
1

1COMP_12VSP 0.01U_0402_16V7K
COMP
1

4 @2s_battery@ PR714 D EN_12VSP 3 4

1 2 2 2s_battery@ PQ702 EN 2s_battery@
<14,36,40,43,45> SUSP#
1

G 2N7002KW_SOT323-3 PR715
Vout=1.24*(1+88.7/10)=12.2V
GND

GND
PAD

0_0402_5% 2s_battery@ 10K_0402_1%

S
3

2
1

2s_battery@ PU703 PR716

@2s_battery@ RT9297GQW_WDFN10_3X3 10K_0402_1%
11

PC723 SA00004JV00
2

0.1U_0402_10V7K
1

2s_battery@
PC724
4700P_0402_25V7K
Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ
2

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
;Ͷ͹͸
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 47 of 57
A B C D E
 1 2 3 4 5

Module model information

Close IC
PRZ1 and PRZ22 are for debug only. RT3602AE_U22_RU42_colay_V1A.mdd for IC portion
VCCSSA_SENSE and VSSSA_SENSE need other resistor at HW side.
RT3602AE_U22_RU42_colay_V1B.mdd for SW portion
RT3602_VREF Vref=0.6V нsͺ^ PRZ1 PRZ8 PRZ10
100_0402_1% 10K_0402_1% 71.5K_0402_1% PCZ3
1 2 VCCSA_SENSE_R 1 2 1 2 0.1U_0402_25V6

1
2.15K_0402_1%
Vinafix.com
0_0402_5%

28K_0402_1%
2.15K_0402_1%
PRZ15
1 2 1 2

2
1

1
1 2
<14> VCCSA_SENSE <49> ISENSE1N_SA ISENSE1P_SA_R1 <49>
@ PCZ200 PCZ5 390P_0402_50V7K PCZ6 68P_0402_50V8J
PRZ2

PRZ3

PRZ4
0.1U_0402_25V6

2
A @ PCZ1 @ PRZ16 A

FB_SA FB_SA
0.1U_0402_10V6K 10K_0402_1% @ PCZ4
2

1
1 2 1 2 0.47U_0402_25V6K
@ PCZ203 1 2
1

1
0.1U_0402_25V6
10K_0402_1%

10K_0402_1%

10K_0402_1%

0.47U_0402_6.3V6K
Close IC RT3602_VREF
PRZ6

PRZ11

PCZ193
1
0_0402_5% PRZ94 1 2 1 2
PRZ5

1 2
<14> VSSSA_SENSE PRZ13 PRZ14
2

2
RT3602_SET1

2
1
PRZ22 48.7K_0402_1% 0_0402_5%
RT3602_SET2 1 2 @ PCZ199
RT3602_SET3
0.1U_0402_25V6
Close IC

RT3602_VREF 3.9_0402_1%
2

1
100_0402_1%

PRZ24
VR_PSYS
PRZ95
PRZ23 нϯs^
1

<16> VSSSENSE 1 2 100K_0402_1%

1K_0402_1%
665_0402_1%

665_0402_1%

10K_0402_1%

1 2
Close CORE1 choke
PRZ18

PRZ19

PRZ20

2
PRZ17

0_0402_5% PRZ21
@ PRZ107 PHZ1 PRZ26 1 2
VR_PWRGD <36> EN
2

0_0402_5% 100K_0402_1%_B25/50 4250K 40.2K_0402_1%

PRZ25 High: > 0.7V
@ PCZ7 1 2PHZ1_R1 1 2 PHZ1_R 1 2 100_0402_1%
0.1U_0402_25V6
RGND_MAIN 1 2
VR_ON
Low:
<36,40>
< 0.3V
2

RT3602_VREF
1

1
2K_0402_1%

2K_0402_1%

16.9K_0402_1%

нϭ͘Ϭϱsͺs^d

IMON_SA
PRZ29

PRZ30

1 2 IMON_CORE_R 1 2 0_0402_5%

RT3602_EN
PRZ28

VSEN_CORE
RGND_MAIN

FB_SA
PRZ33

COMP_SA
Co

RGND_SA
VR_PSYS
26.7K_0402_1% @ PCZ9 PRZ35 @ PCZ206
2

1
@ PCZ204 0.1U_0402_10V6K 3.3K_0402_1% @ PCZ201 0.1U_0402_25V6

PCZ194
110_0402_1%

0.1U_0402_25V6
1

1
0.1U_0402_25V6 U42@ PRZ45 @ PCZ207 1 2 0.1U_0402_25V6 1 2

75_0402_1%
100_0402_1%
45.3_0402_1%

1
33K_0402_1% 47P_0402_50V8J @

PRZ37
CORE1_LX <49>
CORE1_LX 1

2
@ PCZ8 @ PRZ40 2 1 2
2

0.1U_0402_10V6K 10K_0402_1% 1M_0402_1% PRZ108 PUZ1

49

48
47
46
45
44
43
42
41
40
39
38
37

PRZ36

PRZ38

PRZ39

2
1 2 1 2 @ RT3602AJGQW_WQFN48_6X6 @
Close IC

2
PRZ43 PRZ45 U22@

GND

RGND_MAIN
VSEN_MAIN

EN
PSYS
FB_SA
RGND_SA
COMP_SA

ISENN_SA
ISENP_SA
IMON_SA
VR_READY
VREF06/PSET
10K_0402_1% 23.2K_0402_1% SOC_SVID_CLK <16>
VSEN_CORE 1 2 1 2 SOC_SVID_ALERT#_R <16>
нsͺKZ PRZ41
IMON_CORE SOC_SVID_DAT <16>
100_0402_1% PCZ12 82P_0402_50V8J 1 36 PWM_SA <49>
RT3602_SET1 IMON_MAIN PWM_SA

mp
1 2 1 2 1 2 2 35 VR_HOT# <36>
FB_CORE SET1 DRVEN DRVEN_CPU <49>
3 34 1 2
PCZ13 4 COMP_CORE FB_MAIN VCLK 33 PRZ98 49.9_0402_1% RT3602_VREF
<49>
330P_0402_50V8J ISENSE1N_CORE RT3602_SET2 COMP_MAIN ALERT#
1 2 PCZ11 0.1U_0402_25V6 5 32 PRZ99 1 210_0402_1% PRZ48
<16> VCCSENSE
1 2 Ra 6 RT3602_SET3 SET2 VDIO 31 1
PRZ100 2
100_0402_1% 30K_0402_1% PRZ49 5.76k_0402_1%
SET3 VR_HOT# IMON_GT
1

U42@ PRZ106 7 30 1 2 1 2
PRZ47 0_0402_5% @ PCZ196 1 2 1 2 ISEN1N_MAIN 8 ISEN1N_MAIN IMON_AUXI 29 @ PCZ15 0.47U_0402_25V6K
Close IC
U42@ 0_0402_5% 9 ISEN2N_MAIN ISENP_AUXI 28 1 2
0.1U_0402_25V6
2

PCZ16 0.1U_0402_25V6 10 ISEN2P_MAIN ISENN_AUXI 27 VSEN_GT

<49> ISENSE2N_CORE TSEN_CORE 11 ISEN1P_MAIN VSEN_AUXI COMP_GT
26
RT3602_VIN 12 TSEN_MAIN COMP_AUXI ISENSE1P_GT_R1 <49>
25 0_0402_5%
Rb VIN RGND_AUXI ISENSE1N_GT <49> PRZ50

PWM1_MAIN
PWM2_MAIN
DRVEN_SET
B 1 2 B

TSEN_AUXI
PWM_AUXI
нϱs>t VSEN_GT

RGND_AUXI
U22@ PRZ105 10K_0402_1% 1 2 1 2
VCCGT_SENSE <16>

FB_AUXI
0.22U_0402_25V6K
1

1
PCZ18

al
2.2_0805_1%
<49> ISENSE2P_CORE_R1
0.1U_0402_25V6 PRZ54 PRZ56 PRZ59
PRZ41 and PRZ21 are for debug only.

VCC
27K_0402_1% 10K_0402_1% 100_0402_1% нsͺ'd

NC
NC

NC
NC
NC
Rc

PRZ53

PCZ19
2
VCCCORE_SENSE and VSSCORE_SENSE need other resistor нϱs>t
1 2 1 2 1 2 1 2
U22@ PRZ104 10K_0402_1%
at HW side.

13
14
15
16
17
DRVEN_SET 18
19
20
21
22
TSEN_GT 23
FB_GT 24

1
<49> ISENSE1P_CORE_R1
1 2 1 2 @ PCZ198
Ra Rb/Rc RT3602_VREF PRZ51 PRZ52 0.1U_0402_25V6

RT3602_VCC

2
110K_0402_1% 1.65K_0402_1% PCZ20 82P_0402_50V8J PCZ21
TSEN_CORE_R 1 2 1 2 270P_0402_50V7K
нϭϵsͺWh

Co
PHZ2
U22 N/A Stuff

1
1 2 1 2 1 2
15K_0402_1%

@ PCZ202
1

FB_GT
@ PRZ61 @ PCZ22 0.1U_0402_25V6
10K_0402_1%

100K_0402_1%_B25/50 4250K

2
10K_0402_1% 0.1U_0402_10V6K
U42 Stuff N/A
PRZ64

<49>
PWM_GT
Close CORE1 MOSFET
PRZ63

нϱs>t

<49>
<49>
PRZ65
Close IC

PWM_CORE2
PWM_CORE1
2

8.2_0402_1%
1 2 0_0402_5%
PRZ93
1

1
1K_0402_1%

2.87K_0402_1%

U22@ PRZ68 1 2
U42@ PRZ68

VSSGT_SENSE <16>

nfi
1K_0402_1%
PRZ67

1
нϱs>t PCZ23
2

1
4.7U_0402_6.3V6M PRZ66
TSEN_CORE_R TSEN_GT_R

2
110K_0402_1% @ PCZ197 PRZ60

1
100K_0402_1%_B25/50 4250K
0.1U_0402_25V6 100_0402_1%

2
1

2
1

@ PRZ72
2K_0402_1%

13K_0402_1%
U42@ PRZ71

10K_0402_5%
U22@ PRZ71
PRZ70

1
de
71.5K_0402_1%

PHZ3
2

DRVEN_SET PRZ69
2

1.65K_0402_1%
1

2
1

PRZ75
15K_0402_1%

10K_0402_1%
PRZ74

10K_0402_5%
Close GT MOSFET
PRZ73

TSEN_GT_R
PRZ59 and PRZ60 are for debug only.
2
2

VCCGT_SENSE and VSSGT_SENSE need other resistor

nti
at HW side.

C
Set DRVEN output function at PS4. Set to 5V DRVEN C
is floating, and set to GND DRVEN is low at PS4.

al
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2019/09/01 Title
CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 48 of 57
1 2 3 4 5
 5 4 3 2 1

нϭϵsͺWh

PRZ76
Vinafix.com @

1
PJZ1

1 2
2
нϭϵs
нϭϵsͺWh

33U_25V_M

33U_25V_M
10U_0603_25V6M

10U_0603_25V6M
JUMP_43X118

2200P_0402_50V7K
2.2_0603_5%

@EMI@ PCZ29

EMI@ PCZ30

PCZ31

PCZ32
CORE1_BST CORE1_BST_R 1 1

0.1U_0402_25V6
D D
1 2

1
+ + U42@ PRZ77

PCZ26

PCZ37

PCZ34
PCZ195

10U_0603_25V6M

10U_0603_25V6M
1

2200P_0402_50V7K
PQZ1 2.2_0603_5%

@EMIU42@ PCZ36

EMIU42@ PCZ33
CORE2_BST CORE2_BST_R

0.1U_0402_25V6
PCZ28 1 2
PUZ2

1
2 2

AON6380_DFN5X6-8-5
0.1U_0402_25V6

1
U42@
4 3 CORE1_UG 1 2 CORE1_UG_R 4 PCZ35

U42@

U42@
PUZ3

2
BOOT UGATE PRZ78 U42@ 0.1U_0402_25V6

2
5 2 0_0603_5%
<48> PWM_CORE1 PWM PHASE 4 3 CORE2_UG 1 2 CORE2_UG_R4
1 6 BOOT UGATE U42@ PRZ79 U42@
<48>
+5VALW DRVEN_CPU Rdc=0.9mohm

3
2
1
EN PGND +VCC_CORE 5 2 CORE2_LX
0_0603_5% PQZ3
VCC_CORE1 PLZ1 <48> PWM_CORE2 PWM PHASE
1 PRZ80 2 8 7 AON6380_DFN5X6-8-5
VCC LGATE 9 CORE1_LX 1 4 +5VALW DRVEN_CPU 1 6
Rdc=0.9 mohm

3
2
1
5.1_0402_1% GND EN PGND +VCC_CORE
ISENSE1P_CORE 2 3 1 2 VCC_CORE2 8 7 U42@ PLZ2
RT9610CGQW_WDFN8_2X2 VCC LGATE
1

PQZ2 9 1 4

@EMI@ PRZ82
4.7_1206_5%
GND

1
PCZ40 U42@ PRZ81
CORE1_LX <48> 0.15UH_NA__35A_20% ISENSE2P_CORE 2 3
1U_0402_10V6K 5.1_0402_1%
2

RT9610CGQW_WDFN8_2X2

1
AON6314_N_DFN56-8-5
U42@

@EMI@ PRZ84
4.7_1206_5%
5

1
Can be closed to choke PCZ41
0.15UH_NA__35A_20%
1U_0402_10V6K

1CORE1_SNUB 2

2
CORE1_LG 4 PCZ42
0.1U_0402_25V6
1 2 ISENSE1P_CORE_R1 2 1 2

1CORE2_SNUB 2
CORE2_LG 4 PRZ87 PRZ103 U42@ PCZ43

Co
PRZ85 PRZ102 @ PRZ88 750_0603_1% 750_0603_1% 0.1U_0402_25V6

3
2
1
750_0603_1% 750_0603_1% 3.57K_0402_1% 1 2 ISENSE2P_CORE_R
1 2 1 2
1 2 U42@

@EMI@ PCZ44
PQZ4 U42@ U42@ @ PRZ90

3
2
1
680P_0603_50V7K
AON6314_N_DFN56-8-5 3.57K_0402_1%
1 2

@EMI@ PCZ45
2

680P_0603_50V7K
Can be closed to choke

2
ISENSE1N_CORE <48>
ISENSE2N_CORE <48>

mp
ISENSE1P_CORE_R1 <48>
ISENSE2P_CORE_R1 <48>

C C

PRG2
al нϭϵsͺWh VCC_CORE
FSW=450kHz
Choke=0.15uH
DCR=0.9mohm +/- 5%
VCC_GT
FSW=450kHz
Choke=0.15uH
DCR=0.9 mohm +/- 5%
VCC_SA
FSW=600kHz
DCR=6.2 mohm +/- 5%

PCG5

PCG6
Co 2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M
2.2_0603_5%

PCG3

PCG4
GT_BST GT_BST_R U22

0.1U_0402_25V6
1 2
U22

1
LL=2.4 mohm U22 LL=10.3 mohm
1

PCG2 LL=3.1 mohm TDC=4A

EMI@
@EMI@
PUG1 TDC=21A
2

2
0.1U_0402_25V6
TDC=18A ICCMAX=4.5A
2

GT_UG ICCMAX=32A
4
BOOT UGATE
3
OCP=40A ICCMAX=31A OCP=9.5A
5 2 GT_LX PQG1 OCP=39A
<48> PWM_GT PWM PHASE
2

AON6962_DFN5X6D-8-7
+5VALW DRVEN_CPU 1 6 U42 U42
Rdc=0.9 mohm

nfi
D1

G1

VCC_GT
EN PGND
PLG1
+VCC_GT
LL=2.4 mohm U42 LL=10.3 mohm
1 PRG1 2 8 7
VCC LGATE 9 7 GT_LX 1 4 TDC=42A LL=3.1 mohm TDC=
GND D2/S1
5.1_0402_1%
ISENSE1P_GT 2 3 ISENSE1N_GT ICCMAX=64A TDC=12A ICCMAX=6A
RT9610CGQW_WDFN8_2X2 ICCMAX=31A OCP=9.5A
1

OCP=70A
@EMI@ PRG4
G2
S2

S2

S2

4.7_1206_5%
1

PCG1
0.15UH_NA__35A_20% OCP=39A
1U_0402_10V6K
2

de
2

PRG6 PRG9 PCG8

1K_0603_1% 1K_0603_1% 0.1U_0402_25V6
1 2 ISENSE1P_GT_R 1 2 1 2
1GT_SNUB

PRG7 PRG8
2.61K_0402_1% 10K_0402_1%
GT_LG 1 2 1 2
Can be closed to choke
@EMI@ PCG9

AVGT1_R
680P_0603_50V7K

nti
2

1 2
Close GT choke
PHG1
10K_0402_1%_B25/50 3370K
B ISENSE1N_GT <48> B

al
ISENSE1P_GT_R1 <48>

нϭϵsͺWh
10U_0603_25V6M

10U_0603_25V6M

2200P_0402_50V7K

PRA2
@EMI@ PCA6

PCA2
0.1U_0402_25V6

2.2_0603_5%
SA_BST SA_BST_R
1

1 2
PCA4

PCA5
1

EMI@
2

PCA3
PUA1
0.1U_0402_25V6
2

4 3 SA_UG
BOOT UGATE
5 2 SA_LX
<48> PWM_SA PWM PHASE
1

+5VALW DRVEN_CPU 1 6 PQA1

Rdc=6.2 mohm
G1

D1

D1

D1

EN PGND AONH36334_DFN3X3A8-10 +VCC_SA

1 2 VCC_SA 8 7 PLA1
VCC LGATE 9 9 10 1 4
PRA1 5.1_0402_1% GND D2/S1 D1
ISENSE1P_SA 2 3
RT9610CGQW_WDFN8_2X2
1

@EMI@ PRA4
G2

S2

S2

S2

4.7_1206_5%
1

PCA1
0.47UH_NA__12.2A_20%
1U_0402_10V6K
2

SA_LG
Can be closed to choke
2

PCA7
0.1U_0402_25V6
ISENSE1P_SA_R
1 SA_SNUB

1 2 1 2 1 2

PRA6 PRA9 PRA7 PRA8

A 750_0603_1% 750_0603_1% 866_0402_1% 1K_0402_1% A
1 2 1 2
@EMI@ PCA8

AVCCSA_R
680P_0402_50V7K

Close SA choke
2

1 2

PHA1
1K_0402_5%_TSM0B102J3652RE ISENSE1N_SA <48>

ISENSE1P_SA_R1 <48>
3650K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/10 Deciphered Date 2019/09/01 Title
CPU Power stage
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
ͻȀǦ
ͻ͸ͷ 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 12, 2018 Sheet 49 of 57
5 4 3 2 1
 1

0.1
Rev
Vinafix.com

57
of
50
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

Sheet
ͻȀǦ
ͻ͸ͷ
E

E
Thursday, July 12, 2018
‘™‡””ƒ‹
Document Number
+VCC_SA

PC9079
1U_0201_4V6M
+VCC_SA

1 2
PC9078

Date:
Title

Size
PC9052 1U_0201_4V6M
22U_0603_6.3V6M

C
1 2
1 2 PC9077
PC9051 1U_0201_4V6M
22U_0603_6.3V6M

22uF_0603*7

22uF_0603*1
1 2
1 2 PC9076

1uF_0201*7
PC9050 1U_0201_4V6M

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
22U_0603_6.3V6M
1 2

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1 2 PC9075

2018/11/04
PC9049 1U_0201_4V6M

unpop:
22U_0603_6.3V6M

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
1 2 PC9074

pop:

al
PC9022 PC9048 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
1 2
SA
1 2 1 2 PC9073
PC9021 PC9047 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
1 2

Deciphered Date
1 2 1 2

Compal Secret Data

nti
D

D
0.47uF*4
22uF*36

22uF *8
de 220uF*1

unpop:
1uF*9

1uF*1

2018/10/10
nfi
+VCC_GT

+VCC_GT

PC9020 PC9046 PC9072 PC9095 @ PC9109 PC9129 PC9153

@

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M 1U_0201_4V6M

Security Classification
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9019 PC9045 PC9071 PC9094 @ PC9108 PC9128 PC9152

Issued Date
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
Co

PC9018 PC9044 PC9070 PC9093 @ PC9107 PC9127 PC9151

@

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M 1U_0201_4V6M

1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9017 PC9043 PC9069 PC9092 @ PC9106 PC9126 PC9150
@

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M 1U_0201_4V6M

1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9016 PC9042 PC9063 PC9091 PC9125
@

+VCC_GT_VCORE
C

C
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2
PC9015 PC9041 PC9062 PC9090 PC9124
@

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

al

1 2 1 2 1 2 1 2 1 2
PC9014 PC9040 PC9061 PC9089 PC9123
@

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

1 2 1 2 1 2 1 2 1 2
PC9013 PC9039 PC9060 @ PC9088 PC9122
@

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

mp

1 2 1 2 1 2 1 2 1 2
PC9012 PC9038 PC9059 PC9087 PC9121
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
SOLDER_PREFORMS_0402

SOLDER_PREFORMS_0402

SOLDER_PREFORMS_0402

SOLDER_PREFORMS_0402

SOLDER_PREFORMS_0402
1 2 1 2 1 2 1 2 1 2
PC9011 PC9037 PC9058 PC9086 PC9120
2

2
ES1@ PR9003

ES1@ PR9004

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M

ES2@ PR9005

ES2@ PR9001

ES2@ PR9002
+
1

1 2 1 2 1 2 1 2 1 2
220U_D2 SX_2VY_R9M
PC9105
1

SGA20221D40
1

1
Co

VCORE Output Capacitor:

+VCC_CORE

+VCC_GT
+VCC_CORE
B

B
22uF_0603*29
1uF_0201*35

PC9001 PC9036 PC9068 PC9099 PC9104 PC9119 PC9139 PC9149 PC9158

@

+VCC_CORE

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

2017/07/03

22_0603*7

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
220uF *3

PC9010 PC9035 PC9067 PC9098 PC9103 PC9118 PC9138 PC9148 PC9157

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9009 PC9034 PC9066 PC9080 PC9117 PC9137 PC9147
UNPOP
@

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

+
1

U22

1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9008 PC9033 PC9065 PC9097 PC9116 PC9136 PC9146
220U_D2 SX_2VY_R9M
@

U42@ PC9102
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
+
1

1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9007 PC9032 PC9064 PC9115 PC9135 PC9145
220U_D2 SX_2VY_R9M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
@U42@ PC9101
+
1

2
+VCC_GT_VCORE

1 2 1 2 1 2 1 2 1 2 1 2
VCORE Output Capacitor:

PC9006 PC9031 PC9057 PC9114 PC9134 PC9144

220U_D2 SX_2VY_R9M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
U42@ PC9100

1 2 1 2 1 2 U42@ PC9084 1 2 1 2 1 2
PC9005 PC9030 PC9056 22U_0603_6.3V6M PC9113 PC9133 PC9143
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2
1 2 1 2 1 2 U42@ PC9083 1 2 1 2 1 2
PC9004 PC9029 PC9055 22U_0603_6.3V6M PC9112 PC9132 PC9142
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2
1 2 1 2 1 2 U42@ PC9082 1 2 1 2 1 2
PC9003 PC9028 PC9054 22U_0603_6.3V6M PC9111 PC9131 PC9141
@
A

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

1 2
1 2 1 2 1 2 U42@ PC9081 1 2 1 2 1 2
22uF_0603*35

PC9002 PC9027 PC9053 22U_0603_6.3V6M PC9110 PC9130 PC9140

@

+VCC_GT_VCORE

1uF_0201*35

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

1 2
2017/07/03

1 2 1 2 1 2 PC9156 1 2 1 2 1 2
22_0603*7

1U_0201_4V6M
220uF *2

1 2
PC9155 U42@ PC9096
1U_0201_4V6M 22U_0603_6.3V6M
UNPOP

1 2 1 2
PC9154 U42@ PC9085
U42

1U_0201_4V6M 22U_0603_6.3V6M
1 2 1 2
1

4
 A B C D E

Vinafix.com
1 1

EN pin don't floating

If have pull down resistor at HW side, pls delete PR2

<21,40> 1.35VS_DGPU_PG

PR1014
1 2
нϯs^ 10K_0402_5%

PL1002 from SH00000PJ00

Co
change to common part
SH00000YE00 2013/10/23
VGA@
@ PJ1001
+19VB JUMP_43X79
PU1001
@VGA@ @VGA_EMI@ @VGA_EMI@
1 2 +19VB_1.35VSDGPUP 2 9 PR1001 PC1001 VGA@ PR1004 PC1006
1 2 IN PG 0_0603_5% 0.1U_0402_25V7K 4.7_1206_5% 680P_0603_50V7K

10U_0603_25V6M
3 1 BST_1.35VSDGPUP
1 2 1 2 1 2 SNB_1.35VSDGPUP 1 2

VGA_EMI@ PC1003

@VGA_EMI@ PC1004
0.1U_0402_25V6
2200P_0402_50V7K
IN BS

1
VGA@ PC1005
mp
4 6 TDC=4.7A
IN LX
2
Ipeak=7.2A нϭ͘ϯϱs^'WhW

2
5 19 VGA@ PL1002
IN LX
7 20 LX_1.35VSDGPUP 1 2
GND LX
8 14 FB_1.35VSDGPUP PCMB063T-1R0MS 12A

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
@VGA@ GND FB

1
2 18 17 LDO_3V_1.35VSDGPUP 2
PR1002 GND VCC

al

@VGA@ PC1010

VGA@ PC1011

VGA@ PC1012

VGA@ PC1013

@VGA@ PC1016

VGA@ PC1017
1
<21,40> 1.35VSDGPU_PWR_EN 1 2 11 10 PC1014 VGA@

2
EN NC

1
@VGA@
ILMT_1.35VSDGPUP 13 12 2.2U_0402_6.3V6M PR1013

2
0_0402_5% ILMT NC
0_0402_5%
1

15 16
+3VALW BYP NC
1

VGA@ PR1003 VGA@

PC1015
1U_0201_6.3V6M

2
100K_0402_1% PC1002 21

Co
PAD

1
0.1U_0402_16V7K
2

GM4G need 1.35V 1 2

2

SY8286RAC_QFN20_3X3 FB_VDDQ_SENSE <24>

GT/GM2G need 1.5V

2
>Kͺϯsͺϭ͘ϯϱs^'WhW

1
@VGA@ @VGA@ PR1012 0_0402_5%
PR1015
VGA@ 0_0402_5%
1

1
VGA@
PR1005

1 2
PR1007 25.5K_0402_1%

nfi
0_0402_5% VGA@
PC1018
2

2
ILMT_1.35VSDGPUP
330P_0402_50V7K

2
1

1
@ @N17S_VGA@
PR1008 PR1010

de
0_0402_5% 105K_0402_1%
FB = 0.6V
2

@N17S_VGA@
(R1)

1
PR1009
0_0402_5% @N17S_VGA@ VGA@
VFB=0.6V

1
D PQ1001 PR1006
1 2 2 20K_0402_1%
Vout=0.6V* (1+R1/R2)
The current limit is set to 8A, 12A or 16A when this pin <21> VRAM_VDD_CTL 2N7002KW_SOT323-3
G
Rdown=25.5K Vout=1.365V

2
1
nti
is pull low, floating or pull high S (R2)

3
@N17S_VGA@ Rdown=97.6K Vout=1.525V

PC9159

0.1U_0402_16V7K
1
PR1011
10K_0402_1%

2
3 3

@N17S_VGA@
al

@
PJ1002
+1.35VSDGPUP 1 2 +1.35VSDGPU
1 2
JUMP_43X118

4 4

Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
‘™‡””ƒ‹
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 51 of 57
A B C D E
 A B C D E

Vinafix.com
1 1

Module model information

SY8032_V2.mdd

Co @ PJ1101
JUMP_43X79

mp
1 2
+1.05VSDGPUP 1 2 +1.05VS_1.0VSDGPU

VIN_1.05VS
VGA@
PC1101
22U_0603_6.3V6M (Common Part)
VGA@
2 1 2 PU1101 SH00000YG00 4*4*2 2

al
SY8032ABC_SOT23-6
@ PJ1102 PL1101 VGA@
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
1 2 VIN_1.05VS 4 3 LX_1.05VS 1 2
+3VS 1 2 IN LX +1.05VSDGPUP Imax= 0.8A, Ipeak= 2.1A

VGA@
5 2 PR1102
PG GND

1
<21> 1VS_DGPU_PG 1 2
нϯs^

68P_0402_50V8J
6 1 @VGA_EMI@

PR1103
N16S_VGA@
Co

7.68K_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M
FB EN

1
PR1107

PC1102

1
10K_0402_5% 4.7_0603_5%

PC1103

PC1104
2

2
@VGA@

2
PR1101

2
0_0402_5%

SNUB_1.05VS
1 2 EN_1.05VS Rup

VGA@

VGA@
<22,40> PEX_VDD_EN
FB_1.05VS

nfi
1

@VGA@ PR1104 VGA@ 1

10K_0402_1% PR1105 @VGA@ VGA@

1
1 2 1M_0402_1% PC1105 PC1106
+3VS_1.8VSDGPU_AON Function Field :

1
0.1U_0402_16V7K @VGA_EMI@ PR1106 N17S_VGA@
2

Rdown PR1103 PWR.Plane.Regulator_1.05VDGPU - 43.7

2

680P_0402_50V7K 10K_0402_1% 6.98K_0402_1%

Rest of support elements - 43.8

2
Note:

de
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)

nti
N16=>1.05V
=>0.6V*(1+(7.68/10)=1.061 (1.01%)
3
=>0.6V*(1+(7.32/10)=1.039 (-1%) 3

N17=>1.0V

al
Vout=0.6V*(1+(6.98/10)=1.019V (1.02%)

4 4

Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
‘™‡””ƒ‹
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 52 of 57
A B C D E
 A B C D E

unmount PRV5 for 2 phase select

R1, R2, R3, R4, R5, C are +19VB_GPU_NVVDD

based on VGA type to set. R2 +19VB

DGPU_PSI <21>
@
PJ1501
N17S_VGA@

PR1208
Vinafix.com +3VS @VGA@
2
2 1
1

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6

2200P_0402_50V7K
<21> DGPU_VID
20.5K_0402_1% PR1231

@EMI@ PC1220

EMI@ PC1221

PC1222

PC1223

PC1224

PC1225
JUMP_43X118

1
0_0402_5%
2 1
R1 VGA_EN 2 1
1 R1 R2 NVVDD_EN <22> 1

105

105
N17S_VGA@

0_0402_5%
10K_0402_5%

.1U_0402_16V7K

2
2

105

105
N16S_VGA@ PR1209 N16S_VGA@ PR1208 PR1209
R3

@VGA@
@VGA@ PR1203

PR1204

10K_0402_5%
2

1
20K_0402_1% 20K_0402_1% N17S_VGA@ 6.19K_0402_1%

@VGA@
@VGA@ PR1205

PC1209
2 1 2 1
PR1211 VGA@ VGA@ VGA@ VGA@
R3 R4

2
4.32K_0402_1%

2
1
N16S_VGA@ PR1211 N16S_VGA@ PR1210

1
2K_0402_1% 18K_0402_1%
N17S_VGA@
R4 PR1210 UG1_VGA VGA@
R5 C

1
16.5K_0402_1% N17S_VGA@

1 2
N16S_VGA@ PR1224 N16S_VGA@ PC1210 PC1210 PQ1201
C

1
0_0402_5% 2700P_0402_50V7K 4700P_0402_50V7K AON6962_DFN5X6D-8-7

2
N17S_VGA@ BST1_VGA 1 2 BST1_VGA_R

D1

G1
PR1224 PL1202
R5 309_0402_1% @VGA@ PR1201 0.22UH_24A_+-20%_7X7X4_M +VGA_CORE
0_0603_5% 7 LX1_VGA 2 1

2
D2/S1

1
NVVDD_GND_SENSE_R VGA@ PC1201
VGA@

UGATE1

BOOT1
VID

PSI

EN

2
Co
0.1U_0402_25V7K

G2

@VGA_EMI@
S2

S2

S2

4.7_1206_5%
2
REFADJ 6 20 LX1_VGA

PR1212
3

6
REFADJ PHASE1

1SNUB_VGA1 1
REFIN_VGA 7 19
REFIN LGATE1 @VGA@ PR1213
N16S_VGA@ LG1_VGA 0_0402_5%

1
VREF_VGA 8 PU1201 18 PVCC_VGA 1 2
VREF PVCC +5VS

mp
RT8812AGQW_WQFN20_3X3

10.5K_0402_1%
1
PC1214

N16S_VGA@
1

VGA@ PR1215 TON_VGA 9 17 LG2_VGA @VGA_EMI@

PR1225
PC1213 VGA@ 499K_0402_1% TON LGATE2 4.7U_0402_6.3V6M PC1215

2
1U_0201_6.3V6M +19VB_GPU_NVVDD 2 1
+19VB_GPU_NVVDD 680P_0603_50V7K
2

2
10 16 +19VB_GPU_NVVDD
RGND PHASE2

UGATE2
PGOOD

BOOT2
VSNS
N17S_VGA@

GND
PU1201

SS
2 VGA@ PR1216 RT8816AGQW_WQFN20_3X3 LX2_VGA 2

al
100_0402_1%

21

11

12

13

14

15
1 2

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6

2200P_0402_50V7K
@EMI@ PC1226

EMI@ PC1227

PC1228

PC1229

PC1230

PC1231
1

1
VGA@ PC1216
@VGA@ PR1218 @VGA@
0_0402_5% PR1217 0.1U_0402_25V7K

2
<23> VSSSENSE_VGA NVVDD_GND_SENSE_R

105

105

105

105
1 2 0_0603_5%
BST2_VGA 1 2 BST2_VGA_R UG2_VGA

Co
VGA@

PC1218
@N16S_VGA@

.1U_0402_16V7K
VGA@ VGA@ VGA@ VGA@
1

1
@VGA@ PC1217
PQ1202

1
@VGA@ PR1220 1000P_0402_50V7K UG2_VGA AON6962_DFN5X6D-8-7
2

2
0_0402_5%

D1

G1
<23> VCCSENSE_VGA 1 2 PL1203
NVVDD_SENSE_R
VGA_CORE_PG <22> LX2_VGA
0.22UH_24A_+-20%_7X7X4_M +VGA_CORE
7 2 1
VGA@ PR1221 D2/S1

@VGA_EMI@
4.7_1206_5%
nfi

2
100_0402_1% VGA@
1 2 VGA@ PR1232

PR1222
G2
+VGA_CORE

S2

S2

S2
1 2 10K_0402_1%
2 1 +3VS_1.8VSDGPU_AON

6
N17S_VGA@

1SNUB_VGA2 1
PR1228
0_0402_5% @VGA@ PR1223

de
10K_0402_1%
1 2 2 1 +3VS

N16S_VGA@
PR1226 LG2_VGA @VGA_EMI@
1

0_0402_5% N17S_VGA@ PC1219

1

PR1230 680P_0603_50V7K

2
N17S_VGA@ 93.1K_0402_1%

nti
PC1232
2

0.033U_0402_16V7K
2

3 3

al

4 4

Security Classification Compal Secret Data ‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

Issued Date 2018/01/10 Deciphered Date 2018/11/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
‘™‡””ƒ‹
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ͻȀǦ
ͻ͸ͷ
Date: Thursday, July 12, 2018 Sheet 53 of 57
A B C D E
 4
3
2
1

A
A

2 1 2 1
2 1
VGA@ PC1315 VGA@ PC1301
@VGA@ PC1319 1U_0402_10V7 4.7U_0402_6.3V6M
0.1U_0402_25V6 2 1 2 1

2 1 VGA@ PC1316 VGA@ PC1326

1U_0402_10V7 4.7U_0402_6.3V6M
@VGA@ PC1320 2 1 2 1

+VGA_CORE
0.1U_0402_25V6
VGA@ PC1317 VGA@ PC1332

B
B

2 1 1U_0402_10V7 4.7U_0402_6.3V6M
+VGA_CORE Under

2 1 2 1
@VGA@ PC1321
0.1U_0402_25V6 VGA@ PC1318 VGA@ PC1324
1U_0402_10V7 4.7U_0402_6.3V6M
2 1 2 1 2 1
Vinafix.com

@VGA@ PC1322 N17S_VGA@ PC1338 VGA@ PC1305

0.1U_0402_25V6 1U_0402_10V7 4.7U_0402_6.3V6M
2 1
2 1
VGA@ PC1306
Co

@ESD_VGA@ PC1323 4.7U_0402_6.3V6M

GPU Core

0.1U_0402_25V6 2 1

2 1 VGA@ PC1307
4.7U_0402_6.3V6M
@ESD_VGA@ PC1304 2 1
0.1U_0402_25V6
VGA@ PC1308
2 1
GB4-128 package

4.7U_0402_6.3V6M
2 1
@ESD_VGA@ PC1325
0.1U_0402_25V6 VGA@ PC1309
2 1 4.7U_0402_6.3V6M
2 1
mp

@ESD_VGA@ PC1302
0.1U_0402_25V6 VGA@ PC1310
4.7U_0402_6.3V6M
2 1

N17S_VGA@ PC1330
4.7U_0402_6.3V6M
2 1
al

N17S_VGA@ PC1337
4.7U_0402_6.3V6M

C
C

2 1
22U_0603_6.3V6M
PC1339 N17S_VGA@
2 1 2 1

N17S_VGA@
10U_0402_6.3V6M 22U_0603_6.3V6M
PC1340 PC1335 VGA@
2 1 2 1
Co

N17S_VGA@
10U_0402_6.3V6M 22U_0603_6.3V6M
+VGA_CORE

PC1341 PC1328 VGA@

Issued Date
2 1 2 1
10U_0402_6.3V6M 22U_0603_6.3V6M
N17S_VGA@

Security Classification
PC1342 PC1327 VGA@
2 1
2 1 PC1311
N17S_VGA@ 220U_D2 SX_2VY_R9M
10U_0402_6.3V6M
PC1343
VGA@ PC1329 VGA@
nfi
2
1
+

2 1 4.7U_0402_6.3V6M
2 1
N17S_VGA@
10U_0402_6.3V6M
VGA@ PC1336
PC1344
2 1 4.7U_0402_6.3V6M VGA@
2
1
+

2 1

2018/01/10
N17S_VGA@
10U_0402_6.3V6M
+VGA_CORE

PC1345
N17S_VGA@ PC1331 PC1312
2 1 4.7U_0402_6.3V6M 220U_D2 SX_2VY_R9M
2 1
Near GPU Core

N17S_VGA@ VGA@
10U_0402_6.3V6M
de
2
1
+

N17S_VGA@ PC1303
PC1346
2 1 4.7U_0402_6.3V6M
2 1 PC1313
10U_0402_6.3V6M
N17S_VGA@ 220U_D2 SX_2VY_R9M
N17S_VGA@ PC1333
PC1347
2 1 4.7U_0402_6.3V6M VGA@
2
1
+

2 1
N17S_VGA@
10U_0402_6.3V6M
PC1348
N17S_VGA@ PC1334 PC1314

D
D

2 1 4.7U_0402_6.3V6M 220U_D2 SX_2VY_R9M

nti

Compal Secret Data N17S_VGA@

10U_0402_6.3V6M

Deciphered Date
PC1349
2 1

N17S_VGA@
10U_0402_6.3V6M
PC1350
al

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2018/11/04

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
C
Size
Title

Date:
Document Number
‘™‡””ƒ‹

Thursday, July 12, 2018

E
E

ͻȀǦ
ͻ͸ͷ
Sheet
‘’ƒŽŽ‡…–”‘‹…•ǡ…Ǥ

54
of
57
Rev
0.1
4
3
2
1