My ID is : 20203229 (last digit is 9, second last is 2, third last is 2)

In terms of explanations, can express in schematic, input and output waveforms for your circuits,
calculations, and reasoning to show the understanding

Please use quartus simulation for questions 2(c)

Please use only the below mentions which is what this module covers to work out the questions as it
is a requirement to apply what I have learnt in the module to design both question 1 and 2 circuits
(e.g can use ic like 74LS221,74HC390, Digital-to-Analog Converters)

LU 1 =

LU 2 =

LU 3 = Light Controller Circuit

LU 4 = Schmitt Trigger, Comparison between Standard Inverter and Schmitt Trigger Inverter, Crystal
Oscillators, Pierce-Gate Crystal Oscillator, One-Shot (Monostable Multivibrator), 74LS221 -
Nonretriggerable One Shot, 74LS123 - Retriggerable One Shot.

LU 5 = Ripple Counter, Implementing a Frequency Divider Using a J-K Flip-flop, Modulus (MOD) of a
counter, State Transition Diagram, any -Bit Ripple UP Counter, any -Bit Ripple DOWN Counter, 4020
IC - 14-stage binary counter, 74HC390 IC – Decade Counter

LU 6 = Flip-Flop Timing, Set-up Time, Propagation Delay Times, Hold Time, Pulse Width, Maximum
Clock Frequency of a Flip Flop, Propagation Delay in a Ripple Counter, Maximum allowable
frequency of clock signal of a ripple counter

LU 7 = Binary-Coded Decimal, Frequency Division using the 4020 IC, 74HC390, 74HC390 as a MOD 10
Counter, 74HC390 as a MOD 6 Counter, Cascaded 74HC390 to achieve Minute and Seconds Section
of Digital Clock, binary to seven segment decoder, seven segment display, 74HC08.

LU 8 = Digital-to-Analog Converters, D/A Converter circuitry – Binary-weighted summing amplifier,

D/A Converter circuitry – R/2R Ladder, Resolution (Step Size), Percentage Resolution, DAC
Specifications, Reconstruction Filter, DAC Circuit,

LU 9 = Sequential Circuit – Synchronous, For Synchronous Design – D FF Excitation Table & State
table, For Synchronous Design - JK FF Excitation Table & State Table, Synchronous Counter Design
Procedure, Design a 101 sequence detector

LU 10-14 I don’t have it yet, but if you can’t solve with using any of the above mentions, can let me
know first before you start doing if not using what is not covered in the module is consider wrong
answer.