ign Course CLOCK TREE SYNTHESIS Learning Objectives: Get familiar with the clock tree synthesis Set options and exceptions for CTS 3. Use the applied design constraints and perform Clock Tree Synthesis 4. Generate and analyze clock tree reports Tasks: Invoke the Tool . Open the Library and Placement Block Check Design - pre clock tree stage Define routing rule Specify Clock Cell List Set Clock Target Skew/Lateney Specify Routing Rule Synthesize and Optimize Clock Tree Logically connect PG nets with the pins 10. View the Clock Tree 11, Report Clock Tree eeregbepe Open the project directory ux > ed dt t Invoke the tool To see the blocks present in the library » BangaPhysical Design Course Now, open the powerplan_done block created in the previous lab ) block placement_done Open the Graphical User Interface (GUI) icc2_shell > start_gui Check Design - pre clock tree stage Before performing CTS, execute the following command and analyze the report ice2_shell > check_design -checks pre_clock_tree stage Activity 1 List the clocks and period using the commands 1. icc2_shell > get_clock or all clocks Name of the Clocks used in the design : icc2_she. > report_clock Frequency of p_clk : Define routing rule Lets define Non Default Rules for metal 4 to metal 7 ice2_shell > create routing rule clk_rule -widths {m4 0.11 0.056 M5 0.056 M6 0.056 0.112 M6 0.112 M7 0.112 } -spacings {M4 M7 0.056 } Specify Clock Cell List The Clock tree is built by using Inverters / Buffers depending on the project requirement. Set the choice of buffers that the clock tree must use during CTS. shel ice. > set_lib_cell_purpose -exclude cts [get_lib_cells. © icc2_shell > set_lib_cell_purpose Chipedge Techr Pvt Led., BangalorePhysical Design Course saed32rvt_c/NBUFFX4_RVT saed32rvt_, saed32rvt_c/NBUFFX16_RVI"] NBUFEX8_RVT ‘Activity 2: Run icc? shell > get_lib cells */NBUPF* Note the different Buffers available in the library. Specify Max Fanout ice2_shell > set_app options -name cts.common.max_fanout -value 30 Set Clock Target Skew/Latency Set target skew/latency constraints for clock trees, Activity 3: 1. What is Lateney ? 2. What is Skew ? Specify Routing Rule Set the clock routing rules in terms of the Metal layers to be used for clock synthesis, the NDR rules, clocks to be routed. [all_clo }- -min_routing layer M4 - ice net_type {internal} -rules clk_ru max_routing layer [all_clo lock ules clk_rule -min_routing layer M4 - ice routing rules net_type {root} max_routing layer M7 Synthesize and Optimize Clock Tree Chipedge Technolo; Pvt Led., BangalorePhysical Design Course Now, we have set the Buffers to be used, Clock routing rules, target latency, target skew run. the Clock_opt command. It is the main core command to synthesize clock tree, routing of clock nets, extraction, optimization and hold time violation fixing of the design. 2 shell > man clock_opt Note down the steps involved in this command, 1. 2. 3 Logically connect PG nets with the pins ‘Make the logical connection of PG nets for all the standard cells ell > connect_pg_net -net VDD [get_pins -hier * -filter connect_pg_net -net VSS [get_pins -hier * -filter 3] After clock_opt is executed you can inspect the clock tree and query for the various attributes. Chipedge Technolo; Pvt Led., Bangalore1, View the Clock Tree In GUI Select, Highlight > Color By > Clock Tree Look for Max_Tran and Max_Cap violations in the design.Chipedge Physical Design Course 3. Report the Clock Tree ice2 shell > report_clock_tree options ‘pare + tanger aeee 20a istenay Seance (nose deeeuie) — Seeaule os ice2_shell > report_clock_qor 6 Chipedye Technologies Pvt Ltd., BangalorePhysical Design Course > create _utilization_configuration -scope block zation -. clude {all} ice2_shell > report_utilization -config core_utilization 5, Report Quality of Results ice2_shell > report_gor -summary Note the WNS, TNS and Number of violating paths : 6. Report Timing shell > report_timing -delay type min 1 > report _timing -delay type max Analyze the reports generated. Activity 5 Define 1. Setup Time : 2. Hold Time Saving the block if vv save J she. close | shell FAERAAEEAAEAEEEAEEAAEEAEEE END #4444 REEAEEEEEEAEEEEEEAEEEEEE v S a a & Chipedge Technolo: Pvt Led., Bangalore