Clock Tree Synthesis © Chipedge Technologies Pvt.Ltd. wwnwichipedge.comContents Chipledge . What is CTS . CTS Prerequisite . Post CTS . Inputs Required Outputs of CTS . Terminology . CTS Methodologies - Cluster Based . CTS Methodologies — H tree . CTS Methodologies - Clock Mesh 10.Implications of Power 11.Signal Integrity 12.Implications of Signal Integrity 13.Implications of Area 14.Analyze CTS Results © Chipedge Technologies Pvt.Ltd, Poenaunsone wwnwichipedige.comWhat is CTS? Delivering Clock to all sequential elements Meeting clock constraint requirements (meeting timing goals) Requirements : clock skew, insertion delay, clock transition Buffering of clock tree usually automated process © What is special about clock nets ? > Heart of Synchronous circuit designs > Usually very high fanout > High fanout nets in the design : Reset, Scan-Enable * Big impact on Power/Timing/Routing > Clock power forms substantial portion in total active power > Skew will impact both setup and hold timing > Non Default Rules on clock nets can cause congestion © Chipedge Technologies Pvt.Ltd. wwnwichipedge.comCTS Prerequisite + The Clock sources are identified with create_clock or create_generated_clock commands + The block is placed. Check legality to verify that the placement is legal + Congestion, Cell Density and Pin Density are analyzed and in control + The power and ground nets are prerouted. © Source clock pin driving huge number of pins o During placement clock path delay was treated as Ideal (zero delay) © Design is closed for Setup violations only. © Chipedge Technologies Pvt.Ltd. wwnwichipedge.comInputs Required ChipEdge * Detailed placement database + Target for Latency and Skew * List of Buffers and Inverters for building the clock tree * Clocks to balance + Non Default Rules definitions * Setting clock transition, capacitance & fan-out + In some cases (critical clocks): Shielding * Metal layers for CTS © Chipedge Technologies Pvt.Ltd. wwnwichipedge.comPost CTS Chipedgs + Tree kind of structure built to meet Load/Slew on clock path + Each buffer/Inverter can drive specific amount of load depending on Drive strength. * Can analyze design for “Hold” violations + Timing analysis with Real clock delays + All Timing and DRV should be closed from now onward. [ crcct source © Chipedge Technologies Pvt.Ltd. wwnwichipedige.comTerminology * Clock Insertion Delay (ID) Delay taken from clock source pin to Any clock sink * Global Skew ( Skew) Difference between Max ID and Min ID * Local Skew Difference between Max ID and Min ID of flops in the timing path * stop Pins Pins which are considered as Clock pins and CTS will not trace further. se hs * Ignore Pins Pins that are not considered for Skew balancing * Float Pins Pins that are forced explicit insertion delay numbers \ + Exclude Pins : Exclude pins are similar to ignore pins, but the clock net mare will not be buffered upto exclude pin. © Chipedge Technologies Pvt.Ltd. wwnwichipedge.comTerminology Through pins : Through pins are pins , which would otherwise be considered stop pins but we want the clock to propagate through them. Skew group : Skew groups are basically groups of sink-pins (clock end-points) which need to be balanced against each other. Ordo MSc CL om molt et oar Moe A eae ee) Peed Stop Pin Yes Yes Yes No Ignore Pin Yes Yes No No Exclude Pin No No No No Through Pin Yes Yes No Yes Float Pin Yes Yes Yes — according No (insertion_delay) to constraint © Chipedge Technologies Pvt.Ltd. www.chipedge.com© Chipedge Technologies Pvt.Ltd. CTS Methodologies - Cluster Based + Most commonly used approach * Based on location of clock sinks, group them into clusters * Build Tree for all individual clusters * Balance clusters by adding buffers at the root of the cluster __ wwnwichipedge.comCTS Methodologies - H-Tree + Called Binary tree + Each driver has 2 symmetric sinks + Load/Routing all aspects should be matched at every level. + Can achieve very low skew with reasonable buffer/inv count + May not be suitable when related logic on same clock domain have to be scattered © Chipedge Technologies Pvt.Ltd. wwnwichipedge.comCTS Methodologies - Clock Mesh Chip * Generally used on very high speed design (like Microprocessors) * Clock gating cells are spread uniformly in design area irrespective of clock sinks. * Based on placement, clock sinks are connected to clock gating cells. + Require advanced analysis (Spice simulations?) to find actual insertion delay and skew © Chipedge Technologies Pvt.Ltd. wwnwichipedge.comImplications of Power © Lets remember how to calculate dynamic power: The clock capacitance consists of : © Clock generation (i.e.,PLL,clock dividers, etc.) © Clock elements (buffers,muxes,clock gates) © Clock wires © Clock load of sequential elements © Clock network are huge © And therefore, the clock is responsible for a large percentage of the total chip power © Chipedge Technologies Pvt.Ltd. wwnwichipedge.comSignal Integrity Chipedgé © Signal integrity during routing is synonymous with crosstalk. a Na _{% © A switching signal may affect a neighbouring en net. Victim © The switching net is called the Aggressor. ioe ee © The affected net is called the victim. speed Up Delay Two major effects: © Crosstalk Gliteh: This refers to noise/glitch caused on a steady victim signal due to the coupling of switching activity of the neighboring aggressors : Overshoot, fall glitch, Undershoot and rise glitch. © Crosstalk Delay: This is due to the coupling between the switching activity of the victim and the switching activity of the aggressors, which results in the change of timing on a particular victim signals : Positive and Negative crosstalk delta delay. © Chipedge Technologies Pvt.Ltd. wenwichipedge.comImplications of Signal Integrity Chipledgé Signal integrity is an obvious requirement for the clock network: Noise on the clock network can cause: © In the worst case , additional clock edges © Lower coupling can still slow down or speed up clock propagation © Irregular clock edges can impede register operation Slow clock transitions(slew rate): © Susceptibility to noise(weak driver) © Poor register functionality( worse tcq,tsetup, thold) Too fast clock transitions © Overdesign - Power and Area © Bigger aggressor to other signals * Unbalanced drivers lead to increase skew ipedge Technologies Pvt.Ltd, wwnwichipedge.comImplications of Area Chipledge + To reiterate, clock network consists of * Clock generators * Clock elements + Clock wires + All of these consume area + Clock generators (e.g PLL)can be very large + Clock buffers are distributed all over the place + Clock wires consume a lot of routing resources + Routing resources are most vital + Require low RC(for transition and power) + Benefit of using high, wide metals + Need to connect to every flip-flop and clock element + Distribution all over the chip + Need via stack to go down from higher metals ipedge Technologies Pvt. Lt, wwnwichipedge.comAnalyse CTS Results + Report clock tree build quality * Global & Local skew + Late/Early insertion delay + Number of Clock-cells + Report the clock timing for the paths that are related + Based on the report, adjust/relax the setting if necessary and then optimize the clock tree incrementally + General Vectors + Timing (Setup and Hold) * Congestion estimate with clock nets + Power * Clock Shielding coverage © Chipedge Technologies Pvt.Ltd. wwnwichipedge.comSummary © What is CTS and its Prerequisite * Post CTS with Inputs & Outputs Required CTS Terminology CTS Methodologies - Cluster Based, H tree & Clock Mesh Implications of Power © Signal Integrity and its Implications ¢ Implications of Area ¢ Analyze CTS Results © Chipedge Technologies Pvt.Ltd. wwnwichipedge.com