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  • Deld - Unit IV

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    ashvini patil
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    This document contains an assignment for a Digital Electronics and Logic Design course. The assignment includes: 1) Explaining algorithmic state machine (ASM) technique for designing sequential circuits; 2) Drawing an ASM chart and circuit for a 2-bit up-down counter with a mode control input; 3) Drawing an ASM chart and state table for a 2-bit up-down counter with mode control; and 4) Explaining the architecture of a programmable logic device (PLD) and designing a combinational circuit using a PROM.

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    Deld- Unit IV

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    This document contains an assignment for a Digital Electronics and Logic Design course. The assignment includes: 1) Explaining algorithmic state machine (ASM) technique for designing sequential circuits; 2) Drawing an ASM chart and circuit for a 2-bit up-down counter with a mode control input; 3) Drawing an ASM chart and state table for a 2-bit up-down counter with mode control; and 4) Explaining the architecture of a programmable logic device (PLD) and designing a combinational circuit using a PROM.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    12 views1 page

    Deld - Unit IV

    Uploaded by

    ashvini patil
    This document contains an assignment for a Digital Electronics and Logic Design course. The assignment includes: 1) Explaining algorithmic state machine (ASM) technique for designing sequential circuits; 2) Drawing an ASM chart and circuit for a 2-bit up-down counter with a mode control input; 3) Drawing an ASM chart and state table for a 2-bit up-down counter with mode control; and 4) Explaining the architecture of a programmable logic device (PLD) and designing a combinational circuit using a PROM.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    Genba Sopanroa Moze College Of Engineering

    Subject : Digital Electronics & Logic Design


    (210245)

    Assignment 4
    Algorithmic state machine & programmable Logic design

    1. Explain in details, ASM technique of designing the sequential ckts.

    2. Draw an ASM charts for 2-bit up down counter with mode control i/p M
    such that for M=1 counter counts up. For M=0 counter holds present
    state also design the ckt with the help of D f/f

    3. Draw an ASM chart & state table for 2 bit up- down counter having mode
    control i/p M

    4. Explain in details the architecture of a PLD

    5. Design a combinational ckt using PROM that accepts a 3- bit binary


    number & produces its equivalent XS-3 code.

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