Reg.No.

Faculty of Engineering
School of Computing and IT
Department of Computer Science and Engineering
III SEM. B.Tech.
Odd Semester End Term Examination 2021-22
CS2102 COMPUTER SYSTEM ARCHITECTURE

Time: 2 Hours MAX.MARKS: 40

Instructions to Students:
• Attempt any full four questions.
• Missing or wrong data, if any, may be assumed suitably after duly mentioning at proper place.
• Calculator is allowed.
• Start every question from a fresh page. Submit scanned copies of answer in sequence order.
• Mention page no on every page.

Q. No. Question Script Marks

1 A 2-bit binary adder sums two numbers, A1A0 and B1B0 to yield the unsigned
result Y2Y1Y0, where the zero subscript indicates the least significant bit (LSB).
(i) Write down the truth table for the required outputs Y2, Y1 and Y0.
(ii) Using a Karnaugh map (K map), give the simplified sum of products
[3+3+4] CO2
expression for Y2.
(iii) Using a K map, determine a simplified product of sums expression
for Y2 and show how the circuit can be implemented using only NOR
gates.
2 (a) Show the connections between two 4-bit binary counters with parallel load to
produce an 8-bit binary counter with parallel load. Use a block diagram for each
4-bit counter. [5] CO3
Explain with the help of above circuit, how it can be used as divide-by-250 counter
(counter that counts from 0 to 249).
2 (b) A byte-addressable processor uses the big-endian representation and 32-bit integer
value -13 is stored at the memory address 100 and same value is stored at register
R0 and R1.
i. Determine the 8-bit binary contents of memory locations 100, 101, 102
and 103? [2+1+2] CO4
ii. Show the integer value in R0 and R1 after execution of instruction
Compare R0, R1?
iii. What will be the integer value in R0 after execution of instruction AShiftR
#2, R0?

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3 (a) Calculate the gate delays for 32-bit × 32-bit multiplication in Carry save addition
of summands method, given that 8 CSA levels are needed to reduce 32 summands
to 2 summands. For final addition of 2 summands of 64 bits, use 64 -bit adder built [5] CO5
from a cascade of four 16-bit CLA adders. Here, 16-bit CLA are developed using
second-level block generate and propagate function.
3 (b) Use non-restoring division algorithm to perform 29 ÷ 3. [5] CO5
4 (a) Consider that floating point numbers are represented in a 14-bit format with
a 6-bit exponent. The 7-bit mantissa is normalized as in the IEEE format,
with an implied 1 to the left of the binary point. Represent the decimal [5] CO5
numbers A = 25 and B = -5 in the above format. Also perform A + B, using
arithmetic operation rules on floating-point numbers.
4 (b) Convert the Multiplicand M = (+31)10 and Multiplier Q = (-24)10 represented as
decimal numbers, in 6-bit, signed, 2’s complement binary numbers. Use Booth [5] CO5
and bit-pair multiplication methods to multiply them.
5. Consider byte addressable machine with 32-bit word size. An integer array of
order m × n is stored starting from memory location LIST in column major order
(that is, the elements of array are stored column-wise at successive memory
location starting from LIST).
i. Write an assembly language program for computing the sum of integers
of each row of the array and store these sums in the memory word
locations at addresses SUM, SUM+4, SUM +8…. (. i.e., m successive
CO1 &
locations starting from SUM). Assume that values of m and n are stored [6+4]
CO4
at memory location M and N respectively.
ii. The assembly code of part (i) is executed on a processor having a clock
rate of 1 GHz. The processor can execute an instruction that access
memory for reading or writing data with an average of 5 steps, and other
instructions that do not require operand access from or to main memory
can execute with an average of 3 steps (each step completes in one clock
cycle). Calculate the execution time for the assembly code.

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