NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA

Department of Computer Science and Engineering

B.Tech. (2nd Yr.) End Semester Examination April, 2022

Subject: Computer Organization and Architecture (CS 2002)

Full Marks: 50 Time: 3Hours

Answer all questions (2-page Question Paper).

1. (a) Divide −42 by +8 using two’s complement binary integer division method (restoration
method).
(b) Show the steps to compute following floating-point subtraction where significant are trun-
cated to 4 decimal digits. Apply ’Rounding to Even Number’ for rounding the results and
show normalized result. (Numbers are in normalized form.)
9.944 × 10−3 − 3.333 × 10−1 . [5 + 5]
2. (a) Consider a machine with byte addressable main memory of 216 bytes and block size of 16
bytes. Assume that 4-way set-associative mapping is used with a cache of size 512 bytes.
The machine generates a main memory address 1A1F in hexadecimal to access the content.
In which set in cache memory will this content be mapped? The machine consecutively
refers following bytes 1A1F, 1A20, 1A21, 1A22. Find the hit ratio. Assume that cache was
empty before the set of reference and LRU block replacement is used. [2 + 3]
(b) If a direct mapping scheme is used instead of associative mapping mentioned in Question
2a, calculate Tag value for an address 1A1F. [2]
(c) If an associative mapping scheme is used instead of associative mapping mentioned in
Question 2a, calculate Tag value for an address 1A20. [1]
(d) What is the advantage of write-back protocol of cache update? [2]
3. (a) A larger memory system of 64x8 is built using smaller memory modules of 8x8 in inter-
leaved fashion. Processor generates two memory address 101101 and 101110. In which
memory module(s) will the contents corresponding to the referred addresses locate? [2]
(b) Consider an L1 cache with an access time of 1 ns and a hit ratio of H=0.95. A new cache
design is offered such that H increases to 0.97 and cache access time increases to 1.5 ns.
What conditions need to be met for performance improvement due to this change? [3]
(c) Clearly mention the operation of DMA. Show and justify the DMA breakpoints during an
instruction cycle. [3+1]
(d) Consider a memory system with following parameters:
Cache Memory: Access Time( Tc ) = 100 ns; Cost Cc = 100 INR/ bit
Main Memory: Access Time ( Tm ) = 1200 ns; Cost (Cm ) = 10 INR/bit.
What is the cost of 1Mbyte of main memory? [1]
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4. (a) What does register IR hold? Draw the single-bus organization of the data-path inside a
processor. [1+2]
(b) Write the sequence of control steps required for an instruction given below with the single-
bus CPU organization taught in the class.
ADDI#90, R1 (Immediate Mode of Instruction adding 90 with the content of R1 and result
stored into R1) [3]
(c) Define Control word and micro-routine. [2]
(d) What is the difference between memory mapped I/O and isolated I/O? [2]

5. (a) Given the following sequence of instructions to be executed in a 4-stage pipeline. Each stage
takes 1 clock cycle.

ADD R2, R0, R1; (source, destination)

MUL R5, R3, R4;
SUB R2, R5, R2;
DIV R5, R2, R6;

Show diagrammatically how the instructions are executed in the 4-stage pipeline. If MUL
instruction takes 2 cycles, how will the operation of pipeline be affected? [2+2]
(b) Data forwarding is a solution to data hazard in which a register (buffer register) RSLT is
used to store the intermediate result and value of RSLT is forwarded back to ALU directly.
Consider the two instructions and value of R1, R2, R3 and RSLT are 30, 100, 45 and 198,
respectively. Draw a timing diagram for 4-stage pipeline and show the content of RSLT at
each clock cycle.
I1 : AddR1, R2, R3
I2 : Shi f t-le f t R3 [2]
(c) Consider the following assembly language codes which add finite consecutive numbers
staring from 0.
MV I A, 0; MV I C, 10; MV I S, 0 ;
LOOP : ADD A, S; I NC A; DCR C;BR > 0 LOOP; END;
Rewrite the assemble language codes so that a pipe-lined processor can use delayed branch-
ing with two delay slots. Show timing diagram of the execution of the code with 4-stage
pipeline. [4]

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