Code No: 07A3EC03 R07 Set No.

2
II B.Tech I Semester Examinations,December 2011
SWITCHING THOERY AND LOGIC DESIGN
Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain the Timing specifications of the flip flops. Define Rise time and Fall
time.
(b) Convert SR flip flop to D flip flop. [8+8]

2. Implement the function of converting a Binary number to a BCD number in a

ROM. Write the size of ROM required implementing this function. Give the ROM
truth table. Give the internal connections for the function. [16]

3. (a) If for example the following events are listed in a ASM block, compare the
execution with respect to conventional flow chart and ASM chart.
i. Register A is incremented
ii. Value of E is verified.
iii. If E=1, then Register R is cleared and control goes to state T4.
iv. If E=0, then the value of F is verified.
v. Depending upon the value of F the control goes to state T2 or T3
(b) Draw the State diagram of a Mod-6 counter. Implement the same in the ASM
chart. Explain the sequence of operation in each ASM block. [8+8]

4. (a) Differentiate Encoders and Priority encoders.

(b) Design a 8 : 1 multiplexer using 4:1 multiplexers and other logic. [8+8]

5. Reduce the given function using Quine McC lusky method

F(A,B,C,D,E,F)=Σm (0,1,2,4,6,9,12,16,21,25,29,32,37,41,43,45,56,58,62,63) [16]

6. (a) State the capabilities and limitations of Finite state machine

(b) Explain the procedure to minimize the incompletely specified machine using
Merger Table. [8+8]

7. Explain the following Huntingtons Postulates with suitable examples

(a) Commutative Law

(b) Distributive Law
(c) Intersection Law
(d) Complements Law [16]

8. (a) Convert the following decimal numbers to BCD and perform BCD addition
i. 14 + 20

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Code No: 07A3EC03 R07 Set No. 2
ii. 10 + 22
iii. 24 + 60
iv. 44 + 55
(b) Write short notes on Excess-3 codes [12+4]

?????

2
Code No: 07A3EC03 R07 Set No. 4
II B.Tech I Semester Examinations,December 2011
SWITCHING THOERY AND LOGIC DESIGN
Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) If for example the following events are listed in a ASM block, compare the
execution with respect to conventional flow chart and ASM chart.
i. Register A is incremented
ii. Value of E is verified.
iii. If E=1, then Register R is cleared and control goes to state T4.
iv. If E=0, then the value of F is verified.
v. Depending upon the value of F the control goes to state T2 or T3
(b) Draw the State diagram of a Mod-6 counter. Implement the same in the ASM
chart. Explain the sequence of operation in each ASM block. [8+8]

2. (a) Explain the Timing specifications of the flip flops. Define Rise time and Fall
time.
(b) Convert SR flip flop to D flip flop. [8+8]

3. (a) Differentiate Encoders and Priority encoders.

(b) Design a 8 : 1 multiplexer using 4:1 multiplexers and other logic. [8+8]

4. Explain the following Huntingtons Postulates with suitable examples

(a) Commutative Law

(b) Distributive Law
(c) Intersection Law
(d) Complements Law [16]

5. (a) Convert the following decimal numbers to BCD and perform BCD addition
i. 14 + 20
ii. 10 + 22
iii. 24 + 60
iv. 44 + 55
(b) Write short notes on Excess-3 codes [12+4]

6. Implement the function of converting a Binary number to a BCD number in a

ROM. Write the size of ROM required implementing this function. Give the ROM
truth table. Give the internal connections for the function. [16]

3
Code No: 07A3EC03 R07 Set No. 4
7. Reduce the given function using Quine McC lusky method
F(A,B,C,D,E,F)=Σm (0,1,2,4,6,9,12,16,21,25,29,32,37,41,43,45,56,58,62,63) [16]

8. (a) State the capabilities and limitations of Finite state machine

(b) Explain the procedure to minimize the incompletely specified machine using
Merger Table. [8+8]

?????

4
Code No: 07A3EC03 R07 Set No. 1
II B.Tech I Semester Examinations,December 2011
SWITCHING THOERY AND LOGIC DESIGN
Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. Implement the function of converting a Binary number to a BCD number in a

ROM. Write the size of ROM required implementing this function. Give the ROM
truth table. Give the internal connections for the function. [16]
2. Reduce the given function using Quine McC lusky method
F(A,B,C,D,E,F)=Σm (0,1,2,4,6,9,12,16,21,25,29,32,37,41,43,45,56,58,62,63) [16]
3. (a) State the capabilities and limitations of Finite state machine
(b) Explain the procedure to minimize the incompletely specified machine using
Merger Table. [8+8]
4. (a) Convert the following decimal numbers to BCD and perform BCD addition
i. 14 + 20
ii. 10 + 22
iii. 24 + 60
iv. 44 + 55
(b) Write short notes on Excess-3 codes [12+4]
5. (a) If for example the following events are listed in a ASM block, compare the
execution with respect to conventional flow chart and ASM chart.
i. Register A is incremented
ii. Value of E is verified.
iii. If E=1, then Register R is cleared and control goes to state T4.
iv. If E=0, then the value of F is verified.
v. Depending upon the value of F the control goes to state T2 or T3
(b) Draw the State diagram of a Mod-6 counter. Implement the same in the ASM
chart. Explain the sequence of operation in each ASM block. [8+8]
6. Explain the following Huntingtons Postulates with suitable examples
(a) Commutative Law
(b) Distributive Law
(c) Intersection Law
(d) Complements Law [16]
7. (a) Explain the Timing specifications of the flip flops. Define Rise time and Fall
time.

5
Code No: 07A3EC03 R07 Set No. 1
(b) Convert SR flip flop to D flip flop. [8+8]

8. (a) Differentiate Encoders and Priority encoders.

(b) Design a 8 : 1 multiplexer using 4:1 multiplexers and other logic. [8+8]

?????

6
Code No: 07A3EC03 R07 Set No. 3
II B.Tech I Semester Examinations,December 2011
SWITCHING THOERY AND LOGIC DESIGN
Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. Reduce the given function using Quine McC lusky method

F(A,B,C,D,E,F)=Σm (0,1,2,4,6,9,12,16,21,25,29,32,37,41,43,45,56,58,62,63) [16]

2. (a) Convert the following decimal numbers to BCD and perform BCD addition
i. 14 + 20
ii. 10 + 22
iii. 24 + 60
iv. 44 + 55
(b) Write short notes on Excess-3 codes [12+4]

3. Implement the function of converting a Binary number to a BCD number in a

ROM. Write the size of ROM required implementing this function. Give the ROM
truth table. Give the internal connections for the function. [16]

4. (a) If for example the following events are listed in a ASM block, compare the
execution with respect to conventional flow chart and ASM chart.
i. Register A is incremented
ii. Value of E is verified.
iii. If E=1, then Register R is cleared and control goes to state T4.
iv. If E=0, then the value of F is verified.
v. Depending upon the value of F the control goes to state T2 or T3
(b) Draw the State diagram of a Mod-6 counter. Implement the same in the ASM
chart. Explain the sequence of operation in each ASM block. [8+8]

5. Explain the following Huntingtons Postulates with suitable examples

(a) Commutative Law

(b) Distributive Law
(c) Intersection Law
(d) Complements Law [16]

6. (a) Explain the Timing specifications of the flip flops. Define Rise time and Fall
time.
(b) Convert SR flip flop to D flip flop. [8+8]

7. (a) Differentiate Encoders and Priority encoders.

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Code No: 07A3EC03 R07 Set No. 3
(b) Design a 8 : 1 multiplexer using 4:1 multiplexers and other logic. [8+8]

8. (a) State the capabilities and limitations of Finite state machine

(b) Explain the procedure to minimize the incompletely specified machine using
Merger Table. [8+8]

?????