S.V.

National Institute of Technology, Surat

B.Tech (III)EC 6TH Sem., END-SEM EXAMINATION May, 2021
EC306: Embedded Systems
Time: 3 Hrs.] [Total Marks: 50
Note: (1) State your assumptions clearly
(2) Program code must be well commented

Q.1 (a) State whether following statement is true or false. [2]

(i) 8051 uses only direct addressing mode to access SFRs
(ii) 8051 can access maximum of 16KB of external RAM
(iii) Interrupts of Cortex M0 are either low level or negative edge triggered
(iv) In Cortex M0, the priority of NMI interrupt is not programmable
(b) Distinguish between the role of locator and linker in embedded software [2]
development tool.
(c) Describe the VLIW CPU architecture. How it differs from superscalar CPU? [2]
(d) ASCII codes of four BCD digits are available in external RAM. Write embedded C [2]
code to form tow packed BCD numbers from these ASCII codes and stored them in
DPL and DPH registers.
(e) Explain how would you measure width of external pulse (ON period) received via [2]
INT1 pin of 8051. No code is to be written.
Q.2 (a) A system to control tail light of a car needs to be designed with the following [4]
specifications:
The car is initially in the ‘static’ state. If a non-zero value is received from the
speedometer, it goes to a ‘moving’ state otherwise it is in ‘static’ state. If the left-
turn signal is received in the ‘moving’ state, the left tail light should blink.
Similarly, if the right-turn signal is received in the ‘moving’ state, the right tail light
should blink. Both tail lights should go off if a wheel-straight signal is received in
the ‘moving’ state or if the car goes to the ‘static’ state. If the emergency signal is
turned on, both tail lights should blink irrespective of whether the car is static or
moving. Emergency signal should override turn and wheel-straight signals. The left
and right turn signals cannot happen simultaneously.
List various ‘tests’ (on signals) and ‘actions’ to be taken for the above system and
draw state diagram specifying tests and actions on state transitions.
(b) We want to use following 18 bytes data structure to implement a FIFO queue. The [5]
first byte stores count variable and next two nibbles contain two pointers (WR and
RD) for managing queue. The last 16 bytes constitute buffer area which contains
data items of 8-bit size. The value of WR and RD indices are relative to start of
buffer area. WR points to next empty location to be written and R0 points to start of
data structure. Write 8051 assembly routine that writes a data byte (available in R1)
to this queue. If queue is full, the subroutine should exit with R2=0x80. The
subroutine should update related control fields of the data structure. The routine can
only use A, R0, R1 and R2 registers

(c) What causes Control and Structural hazards in pipeline CPU? How to overcome [3]
these hazards?
Q.3 (a) Write in brief the purpose of following Cortex M0 registers. [2]
LR, APSR, PRIMASK, CONTROL
 (b) Explain the simple interrupt handling process of Cortex M0 with waveforms of [3]
interrupt source, pending status, processor modes/operation. Also mark various
events on waveforms.
When interrupt occurs the stacking saves few registers in stack automatically. How
would you save other registers in stack?
(c) Write Cortex M0 assembly code to enable IRQ#5 and IRQ#23 and then set priority [3]
Level 1 for IRQ#5 and Level 3 for IRQ#23
(d) Draw flow chart and write Cortex M0 assembly code to find Cube root of 32-bit [3]
number (available in R3). Store the result in R2.
(e) Write Cortex M0 assembly program with no more than 4 instructions to order bytes [2]
of 32-bit register from R0 (B3B2B1B0) to R0 (B2B1B0 B3)
OR
Assuming that current values of Cortex M0 stack pointer MSP is 0x2000FFF8.
Write the stack addresses (in hex) of locations where R12, LR (R14), PC (R15) and
xPSR will be saved when an exception/ interrupt occurs.
(f) What is the use of PSP and MSP of Cortex M0? What is the advantage using two [2]
stack pointers?
Q.4 (a) What is WIC (wake up interrupt controller)? How it helps reducing power in Cortex [2]
M0 processor?
(b) Explain the sleep mode operation achieved with WFI in Cortex M0. How Sleep-on- [2]
exit feature works?
(c) A preemptive scheduler is invoked at every 0.5 unit of time and selects a process [5]
from ready queue. Deadlines shown in table are with respect to 0 time.
Process --> P1 P2 P3
Released Time 1 3 2
Run time 3 1 2
Deadline 5.5 5 4.5

Show how processes are scheduled if it uses Least Slack Time First policy. Also
compute the waiting time of each process.
If there is a tie, it will be resolved with following criteria in that order
 A process already running will be preferred
 A process with earlier deadline time will be preferred.
(d) Explain the concept of process (task) and thread. What is context switching? [2]

(e) Explain Round Robin Scheduling with Time Slicing. [2]