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    The document discusses memory hierarchy and caching techniques like critical word first and early restart. It provides an example to calculate the number of cycles needed to service an L2 cache miss with and without these techniques. Critical word first and early restart would be more important for L1 caches since L1 cache misses have higher latency and reducing them is more critical for performance. These techniques are still useful for L2 caches by partially hiding the longer miss latency.

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    The document discusses memory hierarchy and caching techniques like critical word first and early restart. It provides an example to calculate the number of cycles needed to service an L2 cache miss with and without these techniques. Critical word first and early restart would be more important for L1 caches since L1 cache misses have higher latency and reducing them is more critical for performance. These techniques are still useful for L2 caches by partially hiding the longer miss latency.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    7 views24 pages

    Memory Structure

    Uploaded by

    Food Feed
    The document discusses memory hierarchy and caching techniques like critical word first and early restart. It provides an example to calculate the number of cycles needed to service an L2 cache miss with and without these techniques. Critical word first and early restart would be more important for L1 caches since L1 cache misses have higher latency and reducing them is more critical for performance. These techniques are still useful for L2 caches by partially hiding the longer miss latency.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 24

    Memory Structure

    Memory
    Hierarchy
    Example
    60 ns
    Cache
    Cache Mapping
    Intro:
    https://www.youtube.com/watch?v=
    1U4v_2J0Qwk

    Pipelining & Examples:


    Pipelining Hazards https://www.youtube.com/watch?v=
    1knWyCGjppQ

    https://www.youtube.com/watch?v=
    EW9vtuthFJY

    https://www.youtube.com/watch?v=
    8yxrT1isnpE
    Fundamentals of https://youtube.com/playlist?list=PLe
    WkeA7esB-MuCn8XQWAarM7zvimE0
    yme
    Computer
    Architecture
    Memory Hierarchy https://youtube.com/playlist?list=PLe
    WkeA7esB-PN8dBeEjWveHwnpQk7o
    Design d0m
    Parallelism https://youtube.com/playlist?list=PLe
    WkeA7esB-OgNoVkE2lW2cVBxpDbu9
    2h
    Consider the usage of critical word first and early restart on L2 cache
    misses. Assume a 1 MB L2 cache with 64-byte blocks and a refill path
    that is 16 bytes wide. Assume that the L2 can be written with 16 bytes
    every 4 processor cycles, the time to receive the first 16-byte block from
    the memory controller is 120 cycles, each additional 16-byte block from
    main memory requires 16 cycles, and data can be bypassed directly into
    the read port of the L2 cache. Ignore any cycles to transfer the miss
    request to the L2 cache and the requested data to the L1 cache.
    a) How many cycles would it take to service an L2 cache miss with
    and without critical word first and early restart?
    b) Do you think critical word first and early restart would be more
    important for L1 caches or L2 caches, and what factors would
    contribute to their relative importance?
    Consider the usage of critical word first and early restart on L2 cache
    misses. Assume a 1 MB L2 cache with 64-byte blocks and a refill path
    that is 16 bytes wide. Assume that the L2 can be written with 16 bytes
    every 4 processor cycles, the time to receive the first 16-byte block from
    the memory controller is 120 cycles, each additional 16-byte block from
    main memory requires 16 cycles, and data can be bypassed directly into
    the read port of the L2 cache. Ignore any cycles to transfer the miss
    request to the L2 cache and the requested data to the L1 cache.
    a) How many cycles would it take to service an L2 cache miss with
    and without critical word first and early restart? 120 + (3 × 16) = 168 cycles
    b) Do you think critical word first and early restart would be more
    important for L1 caches or L2 caches, and what factors would
    contribute to their relative importance?

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