Exam OS 2 – Ready !

Part I: Multiple-Choice Questions. (Circle only ONE choice)

(e) 1. Which is not the necessary condition of a deadlock?

a. Mutual exclusion
b. Hold and wait
c. No preemption
d. Circular wait
e. None of above

(e) 2. Which is not the method for handing deadlocks?

a. Deadlock Prevention
b. Deadlock Avoidance
c. Deadlock Detection and Recovery
d. Deadlock Ignorance
e. None of above

(b) 3. In connection with memory management, the term "dynamic loading"

refers to:

a. Preloading of routines which will likely be needed into memory

b. The routine will not be loaded into memory until needed
c. Loading part of the routine into memory while the calling program
runs
d. None of above

(b) 4. Which of the memory allocation schemes are subject to external

fragmentation?

a. Multiple Contiguous Fixed Partitions

b. Multiple Contiguous Variable Partitions
c. Paging
d. None of above

(a) 5. Which of the memory allocation schemes are subject to internal

fragmentation?

a. Multiple Contiguous Fixed Partitions

b. Multiple Contiguous Variable Partitions
c. Segmentation
d. None of above

(b) 6. A computer provides the user with virtual address space of 2^32
(2 to the power 32) bytes. Pages of size 4096 (4K or 2^12) bytes
are used for implementing virtual memory where the total physical
memory is equal to 2^18 bytes. If the hexadecimal virtual
address is 23456111, the page number in hexadecimal would be:

a. 3456
b. 23456
c. 56111
d. 4096

(c) 7. In paging system where page size is 2048 words, and the available
physical memory is equal to 2 ^ 17 = 128 K words, the length of the
physical address is equal to:

a. 16 bits b. 28 bits c. 17 bits d. None of the above

(c) 8. If normal memory access time is 100 nanoseconds and the cache search
time is 20 nanoseconds and all 80% of the page table entries are
found in the cache memory the paged memory access time is equal to:

a. 100 ns b. 120 ns c. 140 ns d. 200 ns

(b) 9. When inverted paging is used, there is/are:

a. One global page table sorted by process id

b. One global page table sorted by the frame number
c. One global page table sorted by the virtual address
d. Page tables for each process sorted by the frame number

(b) 10. With paging, the internal fragmentation is possible when:

a. Page does not quite fit the frame

b. The last page of the job is less than maximum page size
c. The cache memory assigned to the page table entry is not
the same as normal memory assigned to the page table entry
d. There is no such thing as internal fragmentation with paging

(c) 11. If there are 64 segments, and the maximum segment size is 1024
words, the length of logical address is:

a. 12 bits b. 14 bits c. 16 bits d. 18 bits

Part II: Questions and Answers

1. List the necessary conditions for a deadlock.

Ans:

o Mutual exclusion: Only one process at a time can use a resource.

o Hold and wait: A process holding at least one resource is waiting to
acquire additional resources held by other processes.
o No preemption: A resource can be released only voluntarily by the
process holding it, after that process has completed its task.
o Circular wait: There exists a set {P0, P1, ., P0} of waiting processes
such that P0 is waiting for a resource that is held by P1, P1 is waiting
for a resource that is held by P2,..., Pn-1 is waiting for a resource
that
is held by Pn, and P0 is waiting for a resource that is held by P0.

2. P is a set of processes. R is a set of resources. E is a set of

request or assignment edges. The sets P, R, and E are as follows:

P = {P1, P2, P3}

R = {R1, R2, R3}
E = {P1 -> R1, P2 -> R3, P3-> R2, R1 -> P2, R2 -> P2, R2 -> P1, R3 ->
P3}

R1 has one instance. R2 has two instances. R3 has one instance.

a. Draw the resource-allocation graph.

b. Is there any deadlock in this situation? Briefly Explain.
Ans:

a. See Figure 8.2.

b. Consider the resource-allocation graph in Figure 8.2. Two cycles
exist in the system.

P1 -> R1 -> P2 -> R3 -> P3 -> R2 -> P1

P2 -> R3 -> P3 -> R2 -> P2

P1, P2, and P3 are deadlocked.

3. List methods for handling deadlocks.

Ans:

o Deadlock Prevention/Avoidance: Ensure that the system will never enter

a deadlock state.
o Deadlock Detection and Recovery: Allow the system to enter a deadlock
state and then recover.
o Deadlock Ignorance: Ignore the problem and pretend that deadlocks never
occur in the system; used by most operating systems, including UNIX.

4. a) What is the difference between a logical address and a physical

address?
b) What is associative memory (translation look-aside buffer, TLB)?
Why do some systems use associative memory in addition to page
tables?
c) Explain the difference between internal and external fragmentation.
d) What type of fragmentation occurs in simple paging systems? Explain.
e) What type occurs in systems that use pure segmentation? Explain.

Ans:

a) A logical address is an address generated by the CPU; also referred to

as
virtual address, whereas a physical address is an address seen by the
memory unit.

b) Associative memory is a special, small, fast-lookup hardware cache

which stores page tables.
Accessing page tables in memory is slow. Using associative memory can
reduce effective access time.

c) Internal fragmentation is the wasted memory (hole) that is internal to a

allocated memory partition. External fragmentation is the wasted memory
(hole) that is external to a allocated memory partitions.

d) Internal fragmentation occurs in simple paging systems.

Because each page has the fixed size, holes (unused memory) occur
within each page.

e) External fragmentation occurs in systems that use pure segmentation.

Because each segment has varied size to fit each program size, the
holes (unused memory) occur external to the allocated memory partition.

5. Consider a swapping system in which memory consists of 500K

as shown below.

+---+-----+------+--------+--------+-----+--+
 |xxx| P3 | xxxx | P5 | xxxxxx | P7 |xx|
+---+-----+------+--------+--------+-----+--+
0 50 160 240 320 420 480 500

Note that P3, P5, and P7 are processes in memory. Assume that process
P3 was just swapped into memory. Consider each of the four swapping
algorithms discussed in class: first fit, best fit and worst fit,
Complete the table showing where each of the processes will be
loaded.

Assume that new processes arrive in the order P8, P9, P10, and are of
size 50K, 70K, and 45K, respectively.

If a process won't fit, write "out of memory" in the appropriate

slot, then indicate if compaction could be used to correct the
problem.

Ans:

First fit:

+---+-----+----+-+--------+---+----+-----+--+
|P8 | P3 | P9 |x| P5 |P10| xx | P7 |xx|
+---+-----+----+-+--------+---+----+-----+--+
0 50 160 230 240 320 365 420 480 500

Best fit:

+---+-----+----+-+--------+---+----+-----+--+
|P8 | P3 | P9 |x| P5 |P10| xx | P7 |xx|
+---+-----+----+-+--------+---+----+-----+--+
0 50 160 230 240 320 365 420 480 500

Worst fit:

+---+-+-----+----+-+--------+---+----+-----+--+
|P10|x| P3 | P9 |x| P5 |P8 | xx | P7 |xx|
+---+-+-----+----+-+--------+---+----+-----+--+
0 45 50 160 230 240 320 370 420 480 500

6. Consider 16-bit machine where total addressable physical memory size

64K words (e.g. 2^16 = 65,538). If we would like to run processes
as big as 128K using 2K (2048-word) pages, how would logical address
look like (show page number and displacement fields in bits)?

Ans:

There 17 bits in logical address and 11 bits in each page.

So page number has 6 bits and page offset 11 bits.

7. Consider a logical address space of 64 pages of 2048 words each, mapped

unto a physical memory of 32 frames.

a) How many bits are there in logical address?

b) How many bits are there in physical address?

Ans:

a) 64 (2^6) pages need 6 bits. 2048 (2^11) words need 11 bits.

 So there are 6 + 11 = 17 bits in logical address.

b) 32 (2^5) frames need 5 bits. 2048 (2^11) words need 11 bits.

So there are 5 + 11 = 16 bits in physical address.

8. The overhead required to read an entry in a page table (including

the time to access associative memory) is 60 nanoseconds. To reduce
this overhead, the computer has an associative memory that can hold
16 entries and can be accessed in 10 nanoseconds.

a) Find a formula that expresses the effective access time as a

function of the hit ratio.
b) What hit ratio is needed to reduce the effective access time to
70 nanoseconds?

Ans:

a) Let E = associative memory lookup time

T = memory cycle time
p = hit ratio.

Effective Access Time (EAT)

= p * (E + T) + (1 - p) * (E + 2 * T)
= p * E + p * T + E + 2 * T - p * E - 2 * p * T
= (2 - p) * T + E

In this case, E + T = 60. E = 10. T = 50.

EAT = (2 - p) * 50 + 10 = 110 - 50 * p

b) 110 - 50 * p < 70
50 * p > 40
p > 80%