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B.

Tech - Winter Semester


Academic Year: 2022-2023
CSE4001- Parallel and Distributed Computing

Assignment-1

1. An instruction pipeline consists of 4 stages: Fetch (F), Decode field (D), Execute (E), and Result-
Write (W). The five instructions (I1-I5) in a certain instruction sequence need these stages for the
different number of clock cycles as shown by the table below.

a. Find the number of clock cycles needed to perform the 5 instructions.


b. How many clock cycles are required to complete the following loop?
For(i=1 to 2) { I1; I2; I3; I4; I5 }

2. What is the purpose of parallel algorithms? What are the key characteristics of a parallel algorithm?

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