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VL2022230504003 Da
VL2022230504003 Da
Assignment-1
1. An instruction pipeline consists of 4 stages: Fetch (F), Decode field (D), Execute (E), and Result-
Write (W). The five instructions (I1-I5) in a certain instruction sequence need these stages for the
different number of clock cycles as shown by the table below.
2. What is the purpose of parallel algorithms? What are the key characteristics of a parallel algorithm?