WEEK 8-TFF USING JK AND 3 BIT BINARY COUNTER-RAKSHITH SRIDHAR 21BAI1017

Experiment No(sw): 8

Register number: 21BAI1017

Name: Rakshith Sridhar

Date: 20/10/22

Aim: design of TFF using JK FF, 3 bit binary counter using TFF, MOD 6 asynchronous counter and to
carry out the simulation output of the above three.

Trainer Kit/tool: Digital IC Trainer/model sim

IC pin diagram:

IC pin diagram of TFF using JK ff:

IC pin diagram of 3 bit binary counter using t flip flop:

IC pin diagram of Mod 6 asynchronous counter:

 WEEK 8-TFF USING JK AND 3 BIT BINARY COUNTER-RAKSHITH SRIDHAR 21BAI1017

Design(Truth table/Schematic/simplification):
Design of TFF using JK flip flop:
truth table:

Logic diagram:
 WEEK 8-TFF USING JK AND 3 BIT BINARY COUNTER-RAKSHITH SRIDHAR 21BAI1017

Excitation table for T flip flop:

Combination of excitation table and characteristic table of t flip flop:

Design of 3 bit binary counter using tff:

 WEEK 8-TFF USING JK AND 3 BIT BINARY COUNTER-RAKSHITH SRIDHAR 21BAI1017

Transition state:
 WEEK 8-TFF USING JK AND 3 BIT BINARY COUNTER-RAKSHITH SRIDHAR 21BAI1017

Table/excitation:
 WEEK 8-TFF USING JK AND 3 BIT BINARY COUNTER-RAKSHITH SRIDHAR 21BAI1017

Simplification:

Mod 6 asynchronous counter using jk design:

 WEEK 8-TFF USING JK AND 3 BIT BINARY COUNTER-RAKSHITH SRIDHAR 21BAI1017

Verilog codes:
Verilog code for TFF using JK flip flop:

behavioural

testbench
 WEEK 8-TFF USING JK AND 3 BIT BINARY COUNTER-RAKSHITH SRIDHAR 21BAI1017

output:

Verilog code for 3 bit binary counter using t flip flop:

behavioral:

Normal behavioral output:

Now after behavioral performing test bench:

Test bench input:

 WEEK 8-TFF USING JK AND 3 BIT BINARY COUNTER-RAKSHITH SRIDHAR 21BAI1017

MOD 6 ASYNCHRONOUS COUNTER VERILOG CODE:

 WEEK 8-TFF USING JK AND 3 BIT BINARY COUNTER-RAKSHITH SRIDHAR 21BAI1017

Output:

Result:

Hence Verilog code, simulation output is implemented for t flip flop using jk, 3 bit counters and mod
6.