ALTERA CORP FEATURES ‘© High density logic ropiacoment for TTL and TAHC.. ‘© Functional and pin compatible with the Altera EPOt0. «High speed, tod = 45 ns. ‘© Asynchronous clocking of all registos or banked roglstor operation from 2 synchronaus clocks. ‘© 24 Macrocells with configurable 1/0 architecture allowing 98 inputs and 24 outputs. «© "Zero Power" (typlcaly 201A standby). Programmable registers providing D,TSR or JK flipflops with Individual Asynchronous. Clear contr 100% genoricaly tostablo—provides 100% pro- gramming yield ‘ Programmable “Security Bit” allows total pro- {ection of proprietary designs. ‘ Package options Include both a 40 pin, 00 mil DIP and a 44 pin Jleaded chip cart © Full software support featuring Schematic Capturo, Notlist, Boolean Equation and Stato ‘Machine design ‘entry methods COME ‘gamadezaaae “eco y4orm oir marinsico Bue D Peer) m@™ 0595372 OOOLL00 7 mm Ub-1B-7 Er CEES ‘The Altera EP900 Isa pin-compatible version of the popular EPO10 Erasable Programmable Logio Bovico (EPLO), Avaliable in 40-pin DIP and 4¢-pin «leaded chip carrer packages, the EP900 contains ‘24 Macrocais with user-configurable /0 architec- {ure ellowing up to 36 Inputs and 24 outputs Each of the 24 Macrocells contains a program- able AND and fixed OF PLA structure, see Figure 4, with @ maximum eight produot terms for logic Implementation. in addition, single product torms ‘control Output Enable/Asynchronous Clock and ‘Asynchronous Clear functions. ‘The Altera proprietary programmable /O archi- tecture allows the EP90O usar to program output ‘and feedback paths for both combinatorial or registered operation, active high or active low, For increased flexibly, the EP900 also Includes h of the 24 internal ters may be programmed to be DT, SR or JK {pfiop. In addition, each register may be clocked asynchronously on an individual basis or syn chronously on a banked register basis. For proper operation, standard high performance design practices should be followed. It Is recom ‘mended that opaque labels be placed over device Window. Input and output pins must be constalr to tho range GND = (Vw or Vou) = Veo: Unused Inputs must always be fled to an appropriate logic level (9, elther Voc.or GND). Each set of Vox GND pine must be shorted together airectly device, Power supply decoupling capactiors of at ast -2uF must be connected between each Voc pin and GND. For the most effective decoupling, Connect one capacitor between each set of Voc land GND pins, directly at the device, Programming the EP900 is accomplished by using the Altera A*PLUS PC-based development software whlch supports schematic capture, not- lit, stato machine and Boolean equation design entry methods, Once the design Is. entered, ‘ASPLUS automatically performs translation Into logical equations, Boolean minimization, and do- sign fiting directly to an EP900. The device may then be programmed to achleve customized work Ing silicon within minutes at the designer's own desktop. For full £P900 function ‘consult the EPB10 datasheet, description please REV 40 8 P3900ALTERA CORP 24E D mm 0595372 0001101 9 mm T=Ho- 13-4 CNT ‘COMMERCIAL, INDUSTRIAL, MILITARY OPERATING RANGES Note: Seo Design Recommendations EI EE coma ma ma war Vee ‘Supply valags ‘Wath epact. 20 70 v Sane oe = a ¥ uw ‘DC INPUT voltage cee 20, 70 Vv aa Teo ea = + i 7 TC OTF ee pr Ey = [a te For dato 7a co [te Sg: ena a % oe co To el egal Tara s oe oa Pe yaar RETR Soa cu cg war Ye Salas 0) ass) | SG v ri TPT vas t Ne v. 1 ‘UTP vege t v 1 pti er Fo oa t ® co 1 Tyg oar Forno = % a % Coan operas Fortin = a % TET 70) wy is ‘2 TET aw oo Ea) is Pea (Veo = 5V 45%, Ta =0°C to 70°C for Commercial) (Woo=V 30h, Ya = 40°C to 850 for Indust) ‘Wop= BV 410% To=-85%C to 125° for Miltary) ‘Note (1) and (6) a ae xan oe or |e HIGH Tevel input voltage 20 203 Vv i TOW eg aigs 3 ov cm HH vel lt va Tera [a cl Ye HH el OS ep lage —| ——Igr=-ona 06 —| —Sat v cm TOW rel ouput loge igankoc | ~¥ 4. ‘Input leakage current ‘Vie Woe oF GND 10. 10, oA Ce Sst opl sta cet | —Vyg r0—[ 0 a We Veo to osu carer andy) Need s ‘0 roe) Te Veo hee ‘ee suply caren (nero) Nolones= “ome 5 15@) | om ot TE Vos or GHD. tes ee soppy cuenta) Noose.» see 45 | recom | om ot Raa os cational ‘Note (4) OL TST a a ur Cu ‘Input Capacitance a Ca Sour Output Capacitance a oF ox Clock Pin Capacitance a oFALTERA CORP 24E D mm 0595372 0001102 0 mm COU : crac, e002. crams |B, (oo =5V + 5%, Ta =0°C to 70° or Commercial ase & eo Wh e-ar eC or ntia, T 46 eal (Veg = BV 10%, Te -B5°C to 25°C for Miitary)*| crews | ema _ oy aC ET Ts |_| |) [ty —_[ ipsa ered apa 6 @ S| Pe Tog ene ob 2 s Co ipa 0a tmx _| Batons e S oS ei ig 10g Gar ® vva_| Beasts ro e e ose ‘ca | Soom ore 5 ® 6 e|[ 3 [ms ‘a | VO ie ea a z H ote SMT =f aT) os rae ‘ron ra si Tana aT | a | mA T_|_ | ee) — | a ius | Waray bs a 0 ar ig | pl ep 8 a =a] 3 ae [igo ort in a i 0 [te Cook ins us w os ig | Gkion to is a 7 Te | ea urea zB =| Hi ck ped to | oomteebacte eps 2 5 ee lin ft ap tox | granite Teen | aw we a7 | wie ~ aT ms | _ ero ‘oak na Ta aS a oan | — nt) oe ig] ae Ea [aa a oe gi [hos opt spe at" % fe ign [eto pt # # 5 oe ior bet ws ms at z oe i eon is a} a i tar bk i 7 z 5 o[ ste Wain ck pid Fie Yuoe | et esa ear 2 5 melee gt: rl pa) = Tei maxim eo} E ton_| faa om | ao co 87 fw "Tina vas or. 256, ae 5 Sh ested ny for neti age of OO. EE AIMRBUTY 5 nue gat Dr rae, eps may oan Te? eT —| ita i a cero bm pacar eases 225 Sates ny. Clock pla Tet tet cds eh a tat ra ‘olay cin rogram as opine pF a me ~ §. Sn tot pono. a, ee Fats psn itary aginst tpt veri, Tease whe permed sa 4b snr & En atomteay conn sandy mods en tnatins loser wan pone modern Hoe a Gece tn ‘Tht Ye Show reset get ec tr vid a 35ALTERA CORP i 24e D mm 0595372 0001103 2 mm T-#6-13-44 Figure 1. Logie Array Macrocelt Pl numbers aie 4 pin DIP = lay In which Logle Array Input Is rom feedback eth Figure 2. tog v8. Fuax Figure 3, Output Drive Currents 1 A tT. fot i 2 Nol cutpat Curent (A) Tp. Vo Our wage